1 #ifndef __NVKM_PMU_MEMX_H__
2 #define __NVKM_PMU_MEMX_H__
5 #include <core/device.h>
19 memx_out(struct nvkm_memx *memx)
21 struct nvkm_pmu *pmu = memx->pmu;
25 nv_wr32(pmu, 0x10a1c4, (memx->c.size << 16) | memx->c.mthd);
26 for (i = 0; i < memx->c.size; i++)
27 nv_wr32(pmu, 0x10a1c4, memx->c.data[i]);
34 memx_cmd(struct nvkm_memx *memx, u32 mthd, u32 size, u32 data[])
36 if ((memx->c.size + size >= ARRAY_SIZE(memx->c.data)) ||
37 (memx->c.mthd && memx->c.mthd != mthd))
39 memcpy(&memx->c.data[memx->c.size], data, size * sizeof(data[0]));
45 nvkm_memx_init(struct nvkm_pmu *pmu, struct nvkm_memx **pmemx)
47 struct nvkm_memx *memx;
51 ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
56 memx = *pmemx = kzalloc(sizeof(*memx), GFP_KERNEL);
60 memx->base = reply[0];
61 memx->size = reply[1];
63 /* acquire data segment access */
65 nv_wr32(pmu, 0x10a580, 0x00000003);
66 } while (nv_rd32(pmu, 0x10a580) != 0x00000003);
67 nv_wr32(pmu, 0x10a1c0, 0x01000000 | memx->base);
72 nvkm_memx_fini(struct nvkm_memx **pmemx, bool exec)
74 struct nvkm_memx *memx = *pmemx;
75 struct nvkm_pmu *pmu = memx->pmu;
78 /* flush the cache... */
81 /* release data segment access */
82 finish = nv_rd32(pmu, 0x10a1c0) & 0x00ffffff;
83 nv_wr32(pmu, 0x10a580, 0x00000000);
85 /* call MEMX process to execute the script, and wait for reply */
87 pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_EXEC,
91 nv_debug(memx->pmu, "Exec took %uns, PMU_IN %08x\n",
98 nvkm_memx_wr32(struct nvkm_memx *memx, u32 addr, u32 data)
100 nv_debug(memx->pmu, "R[%06x] = 0x%08x\n", addr, data);
101 memx_cmd(memx, MEMX_WR32, 2, (u32[]){ addr, data });
105 nvkm_memx_wait(struct nvkm_memx *memx,
106 u32 addr, u32 mask, u32 data, u32 nsec)
108 nv_debug(memx->pmu, "R[%06x] & 0x%08x == 0x%08x, %d us\n",
109 addr, mask, data, nsec);
110 memx_cmd(memx, MEMX_WAIT, 4, (u32[]){ addr, mask, data, nsec });
111 memx_out(memx); /* fuc can't handle multiple */
115 nvkm_memx_nsec(struct nvkm_memx *memx, u32 nsec)
117 nv_debug(memx->pmu, " DELAY = %d ns\n", nsec);
118 memx_cmd(memx, MEMX_DELAY, 1, (u32[]){ nsec });
119 memx_out(memx); /* fuc can't handle multiple */
123 nvkm_memx_wait_vblank(struct nvkm_memx *memx)
125 struct nvkm_pmu *pmu = memx->pmu;
126 u32 heads, x, y, px = 0;
129 if (nv_device(pmu)->chipset < 0xd0) {
130 heads = nv_rd32(pmu, 0x610050);
131 for (i = 0; i < 2; i++) {
132 /* Heuristic: sync to head with biggest resolution */
133 if (heads & (2 << (i << 3))) {
134 x = nv_rd32(pmu, 0x610b40 + (0x540 * i));
135 y = (x & 0xffff0000) >> 16;
146 nv_debug(memx->pmu, "WAIT VBLANK !NO ACTIVE HEAD\n");
150 nv_debug(memx->pmu, "WAIT VBLANK HEAD%d\n", head_sync);
151 memx_cmd(memx, MEMX_VBLANK, 1, (u32[]){ head_sync });
152 memx_out(memx); /* fuc can't handle multiple */
156 nvkm_memx_train(struct nvkm_memx *memx)
158 nv_debug(memx->pmu, " MEM TRAIN\n");
159 memx_cmd(memx, MEMX_TRAIN, 0, NULL);
163 nvkm_memx_train_result(struct nvkm_pmu *pmu, u32 *res, int rsize)
165 u32 reply[2], base, size, i;
168 ret = pmu->message(pmu, reply, PROC_MEMX, MEMX_MSG_INFO,
174 size = reply[1] >> 2;
178 /* read the packet */
179 nv_wr32(pmu, 0x10a1c0, 0x02000000 | base);
181 for (i = 0; i < size; i++)
182 res[i] = nv_rd32(pmu, 0x10a1c4);
188 nvkm_memx_block(struct nvkm_memx *memx)
190 nv_debug(memx->pmu, " HOST BLOCKED\n");
191 memx_cmd(memx, MEMX_ENTER, 0, NULL);
195 nvkm_memx_unblock(struct nvkm_memx *memx)
197 nv_debug(memx->pmu, " HOST UNBLOCKED\n");
198 memx_cmd(memx, MEMX_LEAVE, 0, NULL);