2 * Tiny Code Generator for QEMU
4 * Copyright (c) 2009, 2011 Stefan Weil
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
25 #include "tcg-be-null.h"
28 * - See TODO comments in code.
31 /* Marker for missing code. */
34 fprintf(stderr, "TODO %s:%u: %s()\n", \
35 __FILE__, __LINE__, __func__); \
39 /* Bitfield n...m (in 32 bit value). */
40 #define BITS(n, m) (((0xffffffffU << (31 - n)) >> (31 - n + m)) << m)
42 /* Macros used in tcg_target_op_defs. */
45 #if TCG_TARGET_REG_BITS == 32
50 #if TARGET_LONG_BITS > TCG_TARGET_REG_BITS
58 /* TODO: documentation. */
59 static const TCGTargetOpDef tcg_target_op_defs[] = {
60 { INDEX_op_exit_tb, { NULL } },
61 { INDEX_op_goto_tb, { NULL } },
62 { INDEX_op_br, { NULL } },
64 { INDEX_op_ld8u_i32, { R, R } },
65 { INDEX_op_ld8s_i32, { R, R } },
66 { INDEX_op_ld16u_i32, { R, R } },
67 { INDEX_op_ld16s_i32, { R, R } },
68 { INDEX_op_ld_i32, { R, R } },
69 { INDEX_op_st8_i32, { R, R } },
70 { INDEX_op_st16_i32, { R, R } },
71 { INDEX_op_st_i32, { R, R } },
73 { INDEX_op_add_i32, { R, RI, RI } },
74 { INDEX_op_sub_i32, { R, RI, RI } },
75 { INDEX_op_mul_i32, { R, RI, RI } },
76 #if TCG_TARGET_HAS_div_i32
77 { INDEX_op_div_i32, { R, R, R } },
78 { INDEX_op_divu_i32, { R, R, R } },
79 { INDEX_op_rem_i32, { R, R, R } },
80 { INDEX_op_remu_i32, { R, R, R } },
81 #elif TCG_TARGET_HAS_div2_i32
82 { INDEX_op_div2_i32, { R, R, "0", "1", R } },
83 { INDEX_op_divu2_i32, { R, R, "0", "1", R } },
85 /* TODO: Does R, RI, RI result in faster code than R, R, RI?
86 If both operands are constants, we can optimize. */
87 { INDEX_op_and_i32, { R, RI, RI } },
88 #if TCG_TARGET_HAS_andc_i32
89 { INDEX_op_andc_i32, { R, RI, RI } },
91 #if TCG_TARGET_HAS_eqv_i32
92 { INDEX_op_eqv_i32, { R, RI, RI } },
94 #if TCG_TARGET_HAS_nand_i32
95 { INDEX_op_nand_i32, { R, RI, RI } },
97 #if TCG_TARGET_HAS_nor_i32
98 { INDEX_op_nor_i32, { R, RI, RI } },
100 { INDEX_op_or_i32, { R, RI, RI } },
101 #if TCG_TARGET_HAS_orc_i32
102 { INDEX_op_orc_i32, { R, RI, RI } },
104 { INDEX_op_xor_i32, { R, RI, RI } },
105 { INDEX_op_shl_i32, { R, RI, RI } },
106 { INDEX_op_shr_i32, { R, RI, RI } },
107 { INDEX_op_sar_i32, { R, RI, RI } },
108 #if TCG_TARGET_HAS_rot_i32
109 { INDEX_op_rotl_i32, { R, RI, RI } },
110 { INDEX_op_rotr_i32, { R, RI, RI } },
112 #if TCG_TARGET_HAS_deposit_i32
113 { INDEX_op_deposit_i32, { R, "0", R } },
116 { INDEX_op_brcond_i32, { R, RI } },
118 { INDEX_op_setcond_i32, { R, R, RI } },
119 #if TCG_TARGET_REG_BITS == 64
120 { INDEX_op_setcond_i64, { R, R, RI } },
121 #endif /* TCG_TARGET_REG_BITS == 64 */
123 #if TCG_TARGET_REG_BITS == 32
124 /* TODO: Support R, R, R, R, RI, RI? Will it be faster? */
125 { INDEX_op_add2_i32, { R, R, R, R, R, R } },
126 { INDEX_op_sub2_i32, { R, R, R, R, R, R } },
127 { INDEX_op_brcond2_i32, { R, R, RI, RI } },
128 { INDEX_op_mulu2_i32, { R, R, R, R } },
129 { INDEX_op_setcond2_i32, { R, R, R, RI, RI } },
132 #if TCG_TARGET_HAS_not_i32
133 { INDEX_op_not_i32, { R, R } },
135 #if TCG_TARGET_HAS_neg_i32
136 { INDEX_op_neg_i32, { R, R } },
139 #if TCG_TARGET_REG_BITS == 64
140 { INDEX_op_ld8u_i64, { R, R } },
141 { INDEX_op_ld8s_i64, { R, R } },
142 { INDEX_op_ld16u_i64, { R, R } },
143 { INDEX_op_ld16s_i64, { R, R } },
144 { INDEX_op_ld32u_i64, { R, R } },
145 { INDEX_op_ld32s_i64, { R, R } },
146 { INDEX_op_ld_i64, { R, R } },
148 { INDEX_op_st8_i64, { R, R } },
149 { INDEX_op_st16_i64, { R, R } },
150 { INDEX_op_st32_i64, { R, R } },
151 { INDEX_op_st_i64, { R, R } },
153 { INDEX_op_add_i64, { R, RI, RI } },
154 { INDEX_op_sub_i64, { R, RI, RI } },
155 { INDEX_op_mul_i64, { R, RI, RI } },
156 #if TCG_TARGET_HAS_div_i64
157 { INDEX_op_div_i64, { R, R, R } },
158 { INDEX_op_divu_i64, { R, R, R } },
159 { INDEX_op_rem_i64, { R, R, R } },
160 { INDEX_op_remu_i64, { R, R, R } },
161 #elif TCG_TARGET_HAS_div2_i64
162 { INDEX_op_div2_i64, { R, R, "0", "1", R } },
163 { INDEX_op_divu2_i64, { R, R, "0", "1", R } },
165 { INDEX_op_and_i64, { R, RI, RI } },
166 #if TCG_TARGET_HAS_andc_i64
167 { INDEX_op_andc_i64, { R, RI, RI } },
169 #if TCG_TARGET_HAS_eqv_i64
170 { INDEX_op_eqv_i64, { R, RI, RI } },
172 #if TCG_TARGET_HAS_nand_i64
173 { INDEX_op_nand_i64, { R, RI, RI } },
175 #if TCG_TARGET_HAS_nor_i64
176 { INDEX_op_nor_i64, { R, RI, RI } },
178 { INDEX_op_or_i64, { R, RI, RI } },
179 #if TCG_TARGET_HAS_orc_i64
180 { INDEX_op_orc_i64, { R, RI, RI } },
182 { INDEX_op_xor_i64, { R, RI, RI } },
183 { INDEX_op_shl_i64, { R, RI, RI } },
184 { INDEX_op_shr_i64, { R, RI, RI } },
185 { INDEX_op_sar_i64, { R, RI, RI } },
186 #if TCG_TARGET_HAS_rot_i64
187 { INDEX_op_rotl_i64, { R, RI, RI } },
188 { INDEX_op_rotr_i64, { R, RI, RI } },
190 #if TCG_TARGET_HAS_deposit_i64
191 { INDEX_op_deposit_i64, { R, "0", R } },
193 { INDEX_op_brcond_i64, { R, RI } },
195 #if TCG_TARGET_HAS_ext8s_i64
196 { INDEX_op_ext8s_i64, { R, R } },
198 #if TCG_TARGET_HAS_ext16s_i64
199 { INDEX_op_ext16s_i64, { R, R } },
201 #if TCG_TARGET_HAS_ext32s_i64
202 { INDEX_op_ext32s_i64, { R, R } },
204 #if TCG_TARGET_HAS_ext8u_i64
205 { INDEX_op_ext8u_i64, { R, R } },
207 #if TCG_TARGET_HAS_ext16u_i64
208 { INDEX_op_ext16u_i64, { R, R } },
210 #if TCG_TARGET_HAS_ext32u_i64
211 { INDEX_op_ext32u_i64, { R, R } },
213 #if TCG_TARGET_HAS_bswap16_i64
214 { INDEX_op_bswap16_i64, { R, R } },
216 #if TCG_TARGET_HAS_bswap32_i64
217 { INDEX_op_bswap32_i64, { R, R } },
219 #if TCG_TARGET_HAS_bswap64_i64
220 { INDEX_op_bswap64_i64, { R, R } },
222 #if TCG_TARGET_HAS_not_i64
223 { INDEX_op_not_i64, { R, R } },
225 #if TCG_TARGET_HAS_neg_i64
226 { INDEX_op_neg_i64, { R, R } },
228 #endif /* TCG_TARGET_REG_BITS == 64 */
230 { INDEX_op_qemu_ld_i32, { R, L } },
231 { INDEX_op_qemu_ld_i64, { R64, L } },
233 { INDEX_op_qemu_st_i32, { R, S } },
234 { INDEX_op_qemu_st_i64, { R64, S } },
236 #if TCG_TARGET_HAS_ext8s_i32
237 { INDEX_op_ext8s_i32, { R, R } },
239 #if TCG_TARGET_HAS_ext16s_i32
240 { INDEX_op_ext16s_i32, { R, R } },
242 #if TCG_TARGET_HAS_ext8u_i32
243 { INDEX_op_ext8u_i32, { R, R } },
245 #if TCG_TARGET_HAS_ext16u_i32
246 { INDEX_op_ext16u_i32, { R, R } },
249 #if TCG_TARGET_HAS_bswap16_i32
250 { INDEX_op_bswap16_i32, { R, R } },
252 #if TCG_TARGET_HAS_bswap32_i32
253 { INDEX_op_bswap32_i32, { R, R } },
259 static const int tcg_target_reg_alloc_order[] = {
264 #if 0 /* used for TCG_REG_CALL_STACK */
270 #if TCG_TARGET_NB_REGS >= 16
282 #if MAX_OPC_PARAM_IARGS != 5
283 # error Fix needed, number of supported input arguments changed!
286 static const int tcg_target_call_iarg_regs[] = {
291 #if 0 /* used for TCG_REG_CALL_STACK */
295 #if TCG_TARGET_REG_BITS == 32
296 /* 32 bit hosts need 2 * MAX_OPC_PARAM_IARGS registers. */
299 #if TCG_TARGET_NB_REGS >= 16
304 # error Too few input registers available
309 static const int tcg_target_call_oarg_regs[] = {
311 #if TCG_TARGET_REG_BITS == 32
317 static const char *const tcg_target_reg_names[TCG_TARGET_NB_REGS] = {
326 #if TCG_TARGET_NB_REGS >= 16
335 #if TCG_TARGET_NB_REGS >= 32
357 static void patch_reloc(tcg_insn_unit *code_ptr, int type,
358 intptr_t value, intptr_t addend)
360 /* tcg_out_reloc always uses the same type, addend. */
361 assert(type == sizeof(tcg_target_long));
364 if (TCG_TARGET_REG_BITS == 32) {
365 tcg_patch32(code_ptr, value);
367 tcg_patch64(code_ptr, value);
371 /* Parse target specific constraints. */
372 static int target_parse_constraint(TCGArgConstraint *ct, const char **pct_str)
374 const char *ct_str = *pct_str;
377 case 'L': /* qemu_ld constraint */
378 case 'S': /* qemu_st constraint */
379 ct->ct |= TCG_CT_REG;
380 tcg_regset_set32(ct->u.regs, 0, BIT(TCG_TARGET_NB_REGS) - 1);
390 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
391 /* Show current bytecode. Used by tcg interpreter. */
392 void tci_disas(uint8_t opc)
394 const TCGOpDef *def = &tcg_op_defs[opc];
395 fprintf(stderr, "TCG %s %u, %u, %u\n",
396 def->name, def->nb_oargs, def->nb_iargs, def->nb_cargs);
400 /* Write value (native size). */
401 static void tcg_out_i(TCGContext *s, tcg_target_ulong v)
403 if (TCG_TARGET_REG_BITS == 32) {
411 static void tcg_out_op_t(TCGContext *s, TCGOpcode op)
417 /* Write register. */
418 static void tcg_out_r(TCGContext *s, TCGArg t0)
420 assert(t0 < TCG_TARGET_NB_REGS);
424 /* Write register or constant (native size). */
425 static void tcg_out_ri(TCGContext *s, int const_arg, TCGArg arg)
428 assert(const_arg == 1);
429 tcg_out8(s, TCG_CONST);
436 /* Write register or constant (32 bit). */
437 static void tcg_out_ri32(TCGContext *s, int const_arg, TCGArg arg)
440 assert(const_arg == 1);
441 tcg_out8(s, TCG_CONST);
448 #if TCG_TARGET_REG_BITS == 64
449 /* Write register or constant (64 bit). */
450 static void tcg_out_ri64(TCGContext *s, int const_arg, TCGArg arg)
453 assert(const_arg == 1);
454 tcg_out8(s, TCG_CONST);
463 static void tci_out_label(TCGContext *s, TCGLabel *label)
465 if (label->has_value) {
466 tcg_out_i(s, label->u.value);
467 assert(label->u.value);
469 tcg_out_reloc(s, s->code_ptr, sizeof(tcg_target_ulong), label, 0);
470 s->code_ptr += sizeof(tcg_target_ulong);
474 static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg1,
477 uint8_t *old_code_ptr = s->code_ptr;
478 if (type == TCG_TYPE_I32) {
479 tcg_out_op_t(s, INDEX_op_ld_i32);
484 assert(type == TCG_TYPE_I64);
485 #if TCG_TARGET_REG_BITS == 64
486 tcg_out_op_t(s, INDEX_op_ld_i64);
489 assert(arg2 == (int32_t)arg2);
495 old_code_ptr[1] = s->code_ptr - old_code_ptr;
498 static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg)
500 uint8_t *old_code_ptr = s->code_ptr;
502 #if TCG_TARGET_REG_BITS == 32
503 tcg_out_op_t(s, INDEX_op_mov_i32);
505 tcg_out_op_t(s, INDEX_op_mov_i64);
509 old_code_ptr[1] = s->code_ptr - old_code_ptr;
512 static void tcg_out_movi(TCGContext *s, TCGType type,
513 TCGReg t0, tcg_target_long arg)
515 uint8_t *old_code_ptr = s->code_ptr;
516 uint32_t arg32 = arg;
517 if (type == TCG_TYPE_I32 || arg == arg32) {
518 tcg_out_op_t(s, INDEX_op_movi_i32);
522 assert(type == TCG_TYPE_I64);
523 #if TCG_TARGET_REG_BITS == 64
524 tcg_out_op_t(s, INDEX_op_movi_i64);
531 old_code_ptr[1] = s->code_ptr - old_code_ptr;
534 static inline void tcg_out_call(TCGContext *s, tcg_insn_unit *arg)
536 uint8_t *old_code_ptr = s->code_ptr;
537 tcg_out_op_t(s, INDEX_op_call);
538 tcg_out_ri(s, 1, (uintptr_t)arg);
539 old_code_ptr[1] = s->code_ptr - old_code_ptr;
542 static void tcg_out_op(TCGContext *s, TCGOpcode opc, const TCGArg *args,
543 const int *const_args)
545 uint8_t *old_code_ptr = s->code_ptr;
547 tcg_out_op_t(s, opc);
550 case INDEX_op_exit_tb:
551 tcg_out64(s, args[0]);
553 case INDEX_op_goto_tb:
554 if (s->tb_jmp_offset) {
555 /* Direct jump method. */
556 assert(args[0] < ARRAY_SIZE(s->tb_jmp_offset));
557 s->tb_jmp_offset[args[0]] = tcg_current_code_size(s);
560 /* Indirect jump method. */
563 assert(args[0] < ARRAY_SIZE(s->tb_next_offset));
564 s->tb_next_offset[args[0]] = tcg_current_code_size(s);
567 tci_out_label(s, arg_label(args[0]));
569 case INDEX_op_setcond_i32:
570 tcg_out_r(s, args[0]);
571 tcg_out_r(s, args[1]);
572 tcg_out_ri32(s, const_args[2], args[2]);
573 tcg_out8(s, args[3]); /* condition */
575 #if TCG_TARGET_REG_BITS == 32
576 case INDEX_op_setcond2_i32:
577 /* setcond2_i32 cond, t0, t1_low, t1_high, t2_low, t2_high */
578 tcg_out_r(s, args[0]);
579 tcg_out_r(s, args[1]);
580 tcg_out_r(s, args[2]);
581 tcg_out_ri32(s, const_args[3], args[3]);
582 tcg_out_ri32(s, const_args[4], args[4]);
583 tcg_out8(s, args[5]); /* condition */
585 #elif TCG_TARGET_REG_BITS == 64
586 case INDEX_op_setcond_i64:
587 tcg_out_r(s, args[0]);
588 tcg_out_r(s, args[1]);
589 tcg_out_ri64(s, const_args[2], args[2]);
590 tcg_out8(s, args[3]); /* condition */
593 case INDEX_op_ld8u_i32:
594 case INDEX_op_ld8s_i32:
595 case INDEX_op_ld16u_i32:
596 case INDEX_op_ld16s_i32:
597 case INDEX_op_ld_i32:
598 case INDEX_op_st8_i32:
599 case INDEX_op_st16_i32:
600 case INDEX_op_st_i32:
601 case INDEX_op_ld8u_i64:
602 case INDEX_op_ld8s_i64:
603 case INDEX_op_ld16u_i64:
604 case INDEX_op_ld16s_i64:
605 case INDEX_op_ld32u_i64:
606 case INDEX_op_ld32s_i64:
607 case INDEX_op_ld_i64:
608 case INDEX_op_st8_i64:
609 case INDEX_op_st16_i64:
610 case INDEX_op_st32_i64:
611 case INDEX_op_st_i64:
612 tcg_out_r(s, args[0]);
613 tcg_out_r(s, args[1]);
614 assert(args[2] == (int32_t)args[2]);
615 tcg_out32(s, args[2]);
617 case INDEX_op_add_i32:
618 case INDEX_op_sub_i32:
619 case INDEX_op_mul_i32:
620 case INDEX_op_and_i32:
621 case INDEX_op_andc_i32: /* Optional (TCG_TARGET_HAS_andc_i32). */
622 case INDEX_op_eqv_i32: /* Optional (TCG_TARGET_HAS_eqv_i32). */
623 case INDEX_op_nand_i32: /* Optional (TCG_TARGET_HAS_nand_i32). */
624 case INDEX_op_nor_i32: /* Optional (TCG_TARGET_HAS_nor_i32). */
625 case INDEX_op_or_i32:
626 case INDEX_op_orc_i32: /* Optional (TCG_TARGET_HAS_orc_i32). */
627 case INDEX_op_xor_i32:
628 case INDEX_op_shl_i32:
629 case INDEX_op_shr_i32:
630 case INDEX_op_sar_i32:
631 case INDEX_op_rotl_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
632 case INDEX_op_rotr_i32: /* Optional (TCG_TARGET_HAS_rot_i32). */
633 tcg_out_r(s, args[0]);
634 tcg_out_ri32(s, const_args[1], args[1]);
635 tcg_out_ri32(s, const_args[2], args[2]);
637 case INDEX_op_deposit_i32: /* Optional (TCG_TARGET_HAS_deposit_i32). */
638 tcg_out_r(s, args[0]);
639 tcg_out_r(s, args[1]);
640 tcg_out_r(s, args[2]);
641 assert(args[3] <= UINT8_MAX);
642 tcg_out8(s, args[3]);
643 assert(args[4] <= UINT8_MAX);
644 tcg_out8(s, args[4]);
647 #if TCG_TARGET_REG_BITS == 64
648 case INDEX_op_add_i64:
649 case INDEX_op_sub_i64:
650 case INDEX_op_mul_i64:
651 case INDEX_op_and_i64:
652 case INDEX_op_andc_i64: /* Optional (TCG_TARGET_HAS_andc_i64). */
653 case INDEX_op_eqv_i64: /* Optional (TCG_TARGET_HAS_eqv_i64). */
654 case INDEX_op_nand_i64: /* Optional (TCG_TARGET_HAS_nand_i64). */
655 case INDEX_op_nor_i64: /* Optional (TCG_TARGET_HAS_nor_i64). */
656 case INDEX_op_or_i64:
657 case INDEX_op_orc_i64: /* Optional (TCG_TARGET_HAS_orc_i64). */
658 case INDEX_op_xor_i64:
659 case INDEX_op_shl_i64:
660 case INDEX_op_shr_i64:
661 case INDEX_op_sar_i64:
662 case INDEX_op_rotl_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
663 case INDEX_op_rotr_i64: /* Optional (TCG_TARGET_HAS_rot_i64). */
664 tcg_out_r(s, args[0]);
665 tcg_out_ri64(s, const_args[1], args[1]);
666 tcg_out_ri64(s, const_args[2], args[2]);
668 case INDEX_op_deposit_i64: /* Optional (TCG_TARGET_HAS_deposit_i64). */
669 tcg_out_r(s, args[0]);
670 tcg_out_r(s, args[1]);
671 tcg_out_r(s, args[2]);
672 assert(args[3] <= UINT8_MAX);
673 tcg_out8(s, args[3]);
674 assert(args[4] <= UINT8_MAX);
675 tcg_out8(s, args[4]);
677 case INDEX_op_div_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
678 case INDEX_op_divu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
679 case INDEX_op_rem_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
680 case INDEX_op_remu_i64: /* Optional (TCG_TARGET_HAS_div_i64). */
683 case INDEX_op_div2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
684 case INDEX_op_divu2_i64: /* Optional (TCG_TARGET_HAS_div2_i64). */
687 case INDEX_op_brcond_i64:
688 tcg_out_r(s, args[0]);
689 tcg_out_ri64(s, const_args[1], args[1]);
690 tcg_out8(s, args[2]); /* condition */
691 tci_out_label(s, arg_label(args[3]));
693 case INDEX_op_bswap16_i64: /* Optional (TCG_TARGET_HAS_bswap16_i64). */
694 case INDEX_op_bswap32_i64: /* Optional (TCG_TARGET_HAS_bswap32_i64). */
695 case INDEX_op_bswap64_i64: /* Optional (TCG_TARGET_HAS_bswap64_i64). */
696 case INDEX_op_not_i64: /* Optional (TCG_TARGET_HAS_not_i64). */
697 case INDEX_op_neg_i64: /* Optional (TCG_TARGET_HAS_neg_i64). */
698 case INDEX_op_ext8s_i64: /* Optional (TCG_TARGET_HAS_ext8s_i64). */
699 case INDEX_op_ext8u_i64: /* Optional (TCG_TARGET_HAS_ext8u_i64). */
700 case INDEX_op_ext16s_i64: /* Optional (TCG_TARGET_HAS_ext16s_i64). */
701 case INDEX_op_ext16u_i64: /* Optional (TCG_TARGET_HAS_ext16u_i64). */
702 case INDEX_op_ext32s_i64: /* Optional (TCG_TARGET_HAS_ext32s_i64). */
703 case INDEX_op_ext32u_i64: /* Optional (TCG_TARGET_HAS_ext32u_i64). */
704 #endif /* TCG_TARGET_REG_BITS == 64 */
705 case INDEX_op_neg_i32: /* Optional (TCG_TARGET_HAS_neg_i32). */
706 case INDEX_op_not_i32: /* Optional (TCG_TARGET_HAS_not_i32). */
707 case INDEX_op_ext8s_i32: /* Optional (TCG_TARGET_HAS_ext8s_i32). */
708 case INDEX_op_ext16s_i32: /* Optional (TCG_TARGET_HAS_ext16s_i32). */
709 case INDEX_op_ext8u_i32: /* Optional (TCG_TARGET_HAS_ext8u_i32). */
710 case INDEX_op_ext16u_i32: /* Optional (TCG_TARGET_HAS_ext16u_i32). */
711 case INDEX_op_bswap16_i32: /* Optional (TCG_TARGET_HAS_bswap16_i32). */
712 case INDEX_op_bswap32_i32: /* Optional (TCG_TARGET_HAS_bswap32_i32). */
713 tcg_out_r(s, args[0]);
714 tcg_out_r(s, args[1]);
716 case INDEX_op_div_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
717 case INDEX_op_divu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
718 case INDEX_op_rem_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
719 case INDEX_op_remu_i32: /* Optional (TCG_TARGET_HAS_div_i32). */
720 tcg_out_r(s, args[0]);
721 tcg_out_ri32(s, const_args[1], args[1]);
722 tcg_out_ri32(s, const_args[2], args[2]);
724 case INDEX_op_div2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
725 case INDEX_op_divu2_i32: /* Optional (TCG_TARGET_HAS_div2_i32). */
728 #if TCG_TARGET_REG_BITS == 32
729 case INDEX_op_add2_i32:
730 case INDEX_op_sub2_i32:
731 tcg_out_r(s, args[0]);
732 tcg_out_r(s, args[1]);
733 tcg_out_r(s, args[2]);
734 tcg_out_r(s, args[3]);
735 tcg_out_r(s, args[4]);
736 tcg_out_r(s, args[5]);
738 case INDEX_op_brcond2_i32:
739 tcg_out_r(s, args[0]);
740 tcg_out_r(s, args[1]);
741 tcg_out_ri32(s, const_args[2], args[2]);
742 tcg_out_ri32(s, const_args[3], args[3]);
743 tcg_out8(s, args[4]); /* condition */
744 tci_out_label(s, arg_label(args[5]));
746 case INDEX_op_mulu2_i32:
747 tcg_out_r(s, args[0]);
748 tcg_out_r(s, args[1]);
749 tcg_out_r(s, args[2]);
750 tcg_out_r(s, args[3]);
753 case INDEX_op_brcond_i32:
754 tcg_out_r(s, args[0]);
755 tcg_out_ri32(s, const_args[1], args[1]);
756 tcg_out8(s, args[2]); /* condition */
757 tci_out_label(s, arg_label(args[3]));
759 case INDEX_op_qemu_ld_i32:
760 tcg_out_r(s, *args++);
761 tcg_out_r(s, *args++);
762 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
763 tcg_out_r(s, *args++);
765 tcg_out_i(s, *args++);
767 case INDEX_op_qemu_ld_i64:
768 tcg_out_r(s, *args++);
769 if (TCG_TARGET_REG_BITS == 32) {
770 tcg_out_r(s, *args++);
772 tcg_out_r(s, *args++);
773 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
774 tcg_out_r(s, *args++);
776 tcg_out_i(s, *args++);
778 case INDEX_op_qemu_st_i32:
779 tcg_out_r(s, *args++);
780 tcg_out_r(s, *args++);
781 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
782 tcg_out_r(s, *args++);
784 tcg_out_i(s, *args++);
786 case INDEX_op_qemu_st_i64:
787 tcg_out_r(s, *args++);
788 if (TCG_TARGET_REG_BITS == 32) {
789 tcg_out_r(s, *args++);
791 tcg_out_r(s, *args++);
792 if (TARGET_LONG_BITS > TCG_TARGET_REG_BITS) {
793 tcg_out_r(s, *args++);
795 tcg_out_i(s, *args++);
797 case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
798 case INDEX_op_mov_i64:
799 case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
800 case INDEX_op_movi_i64:
801 case INDEX_op_call: /* Always emitted via tcg_out_call. */
805 old_code_ptr[1] = s->code_ptr - old_code_ptr;
808 static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, TCGReg arg1,
811 uint8_t *old_code_ptr = s->code_ptr;
812 if (type == TCG_TYPE_I32) {
813 tcg_out_op_t(s, INDEX_op_st_i32);
818 assert(type == TCG_TYPE_I64);
819 #if TCG_TARGET_REG_BITS == 64
820 tcg_out_op_t(s, INDEX_op_st_i64);
828 old_code_ptr[1] = s->code_ptr - old_code_ptr;
831 /* Test if a constant matches the constraint. */
832 static int tcg_target_const_match(tcg_target_long val, TCGType type,
833 const TCGArgConstraint *arg_ct)
835 /* No need to return 0 or 1, 0 or != 0 is good enough. */
836 return arg_ct->ct & TCG_CT_CONST;
839 static void tcg_target_init(TCGContext *s)
841 #if defined(CONFIG_DEBUG_TCG_INTERPRETER)
842 const char *envval = getenv("DEBUG_TCG");
844 qemu_set_log(strtol(envval, NULL, 0));
848 /* The current code uses uint8_t for tcg operations. */
849 assert(ARRAY_SIZE(tcg_op_defs) <= UINT8_MAX);
851 /* Registers available for 32 bit operations. */
852 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I32], 0,
853 BIT(TCG_TARGET_NB_REGS) - 1);
854 /* Registers available for 64 bit operations. */
855 tcg_regset_set32(tcg_target_available_regs[TCG_TYPE_I64], 0,
856 BIT(TCG_TARGET_NB_REGS) - 1);
857 /* TODO: Which registers should be set here? */
858 tcg_regset_set32(tcg_target_call_clobber_regs, 0,
859 BIT(TCG_TARGET_NB_REGS) - 1);
861 tcg_regset_clear(s->reserved_regs);
862 tcg_regset_set_reg(s->reserved_regs, TCG_REG_CALL_STACK);
863 tcg_add_target_add_op_defs(tcg_target_op_defs);
865 /* We use negative offsets from "sp" so that we can distinguish
866 stores that might pretend to be call arguments. */
867 tcg_set_frame(s, TCG_REG_CALL_STACK,
868 -CPU_TEMP_BUF_NLONGS * sizeof(long),
869 CPU_TEMP_BUF_NLONGS * sizeof(long));
872 /* Generate global QEMU prologue and epilogue code. */
873 static inline void tcg_target_qemu_prologue(TCGContext *s)