qemu/target-xtensa/overlay_tool.h

   1 /*
   2  * Copyright (c) 2011, Max Filippov, Open Source and Linux Lab.
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are met:
   7  *     * Redistributions of source code must retain the above copyright
   8  *       notice, this list of conditions and the following disclaimer.
   9  *     * Redistributions in binary form must reproduce the above copyright
  10  *       notice, this list of conditions and the following disclaimer in the
  11  *       documentation and/or other materials provided with the distribution.
  12  *     * Neither the name of the Open Source and Linux Lab nor the
  13  *       names of its contributors may be used to endorse or promote products
  14  *       derived from this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  17  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  18  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  19  * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  20  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  21  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  23  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  25  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26  */
  27
  28 #define XTREG(idx, ofs, bi, sz, al, no, flags, cp, typ, grp, name, \
  29         a1, a2, a3, a4, a5, a6) \
  30     { .targno = (no), .type = (typ), .group = (grp), .size = (sz) },
  31 #define XTREG_END { .targno = -1 },
  32
  33 #ifndef XCHAL_HAVE_DIV32
  34 #define XCHAL_HAVE_DIV32 0
  35 #endif
  36
  37 #ifndef XCHAL_UNALIGNED_LOAD_HW
  38 #define XCHAL_UNALIGNED_LOAD_HW 0
  39 #endif
  40
  41 #ifndef XCHAL_HAVE_VECBASE
  42 #define XCHAL_HAVE_VECBASE 0
  43 #define XCHAL_VECBASE_RESET_VADDR 0
  44 #endif
  45
  46 #ifndef XCHAL_HW_MIN_VERSION
  47 #define XCHAL_HW_MIN_VERSION 0
  48 #endif
  49
  50 #define XCHAL_OPTION(xchal, qemu) ((xchal) ? XTENSA_OPTION_BIT(qemu) : 0)
  51
  52 #define XTENSA_OPTIONS ( \
  53     XCHAL_OPTION(XCHAL_HAVE_DENSITY, XTENSA_OPTION_CODE_DENSITY) | \
  54     XCHAL_OPTION(XCHAL_HAVE_LOOPS, XTENSA_OPTION_LOOP) | \
  55     XCHAL_OPTION(XCHAL_HAVE_ABSOLUTE_LITERALS, XTENSA_OPTION_EXTENDED_L32R) | \
  56     XCHAL_OPTION(XCHAL_HAVE_MUL16, XTENSA_OPTION_16_BIT_IMUL) | \
  57     XCHAL_OPTION(XCHAL_HAVE_MUL32, XTENSA_OPTION_32_BIT_IMUL) | \
  58     XCHAL_OPTION(XCHAL_HAVE_MUL32_HIGH, XTENSA_OPTION_32_BIT_IMUL_HIGH) | \
  59     XCHAL_OPTION(XCHAL_HAVE_DIV32, XTENSA_OPTION_32_BIT_IDIV) | \
  60     XCHAL_OPTION(XCHAL_HAVE_MAC16, XTENSA_OPTION_MAC16) | \
  61     XCHAL_OPTION(XCHAL_HAVE_NSA, XTENSA_OPTION_MISC_OP_NSA) | \
  62     XCHAL_OPTION(XCHAL_HAVE_MINMAX, XTENSA_OPTION_MISC_OP_MINMAX) | \
  63     XCHAL_OPTION(XCHAL_HAVE_SEXT, XTENSA_OPTION_MISC_OP_SEXT) | \
  64     XCHAL_OPTION(XCHAL_HAVE_CLAMPS, XTENSA_OPTION_MISC_OP_CLAMPS) | \
  65     XCHAL_OPTION(XCHAL_HAVE_CP, XTENSA_OPTION_COPROCESSOR) | \
  66     XCHAL_OPTION(XCHAL_HAVE_BOOLEANS, XTENSA_OPTION_BOOLEAN) | \
  67     XCHAL_OPTION(XCHAL_HAVE_FP, XTENSA_OPTION_FP_COPROCESSOR) | \
  68     XCHAL_OPTION(XCHAL_HAVE_RELEASE_SYNC, XTENSA_OPTION_MP_SYNCHRO) | \
  69     XCHAL_OPTION(XCHAL_HAVE_S32C1I, XTENSA_OPTION_CONDITIONAL_STORE) | \
  70     XCHAL_OPTION(XCHAL_HAVE_S32C1I && XCHAL_HW_MIN_VERSION >= 230000, \
  71         XTENSA_OPTION_ATOMCTL) | \
  72     /* Interrupts and exceptions */ \
  73     XCHAL_OPTION(XCHAL_HAVE_EXCEPTIONS, XTENSA_OPTION_EXCEPTION) | \
  74     XCHAL_OPTION(XCHAL_HAVE_VECBASE, XTENSA_OPTION_RELOCATABLE_VECTOR) | \
  75     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_EXCEPTION, \
  76         XTENSA_OPTION_UNALIGNED_EXCEPTION) | \
  77     XCHAL_OPTION(XCHAL_HAVE_INTERRUPTS, XTENSA_OPTION_INTERRUPT) | \
  78     XCHAL_OPTION(XCHAL_HAVE_HIGHPRI_INTERRUPTS, \
  79         XTENSA_OPTION_HIGH_PRIORITY_INTERRUPT) | \
  80     XCHAL_OPTION(XCHAL_HAVE_CCOUNT, XTENSA_OPTION_TIMER_INTERRUPT) | \
  81     /* Local memory, TODO */ \
  82     XCHAL_OPTION(XCHAL_ICACHE_WAYS, XTENSA_OPTION_ICACHE) | \
  83     XCHAL_OPTION(XCHAL_ICACHE_LINE_LOCKABLE, \
  84             XTENSA_OPTION_ICACHE_INDEX_LOCK) | \
  85     XCHAL_OPTION(XCHAL_DCACHE_WAYS, XTENSA_OPTION_DCACHE) | \
  86     XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \
  87             XTENSA_OPTION_DCACHE_INDEX_LOCK) | \
  88     XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \
  89     /* Memory protection and translation */ \
  90     XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \
  91             XTENSA_OPTION_REGION_PROTECTION) | \
  92     XCHAL_OPTION(XCHAL_HAVE_XLT_CACHEATTR, \
  93             XTENSA_OPTION_REGION_TRANSLATION) | \
  94     XCHAL_OPTION(XCHAL_HAVE_PTP_MMU, XTENSA_OPTION_MMU) | \
  95     XCHAL_OPTION(XCHAL_HAVE_CACHEATTR, XTENSA_OPTION_CACHEATTR) | \
  96     /* Other, TODO */ \
  97     XCHAL_OPTION(XCHAL_HAVE_WINDOWED, XTENSA_OPTION_WINDOWED_REGISTER) | \
  98     XCHAL_OPTION(XCHAL_HAVE_DEBUG, XTENSA_OPTION_DEBUG) |\
  99     XCHAL_OPTION(XCHAL_NUM_MISC_REGS > 0, XTENSA_OPTION_MISC_SR) | \
 100     XCHAL_OPTION(XCHAL_HAVE_THREADPTR, XTENSA_OPTION_THREAD_POINTER) | \
 101     XCHAL_OPTION(XCHAL_HAVE_PRID, XTENSA_OPTION_PROCESSOR_ID))
 102
 103 #ifndef XCHAL_WINDOW_OF4_VECOFS
 104 #define XCHAL_WINDOW_OF4_VECOFS         0x00000000
 105 #define XCHAL_WINDOW_UF4_VECOFS         0x00000040
 106 #define XCHAL_WINDOW_OF8_VECOFS         0x00000080
 107 #define XCHAL_WINDOW_UF8_VECOFS         0x000000C0
 108 #define XCHAL_WINDOW_OF12_VECOFS        0x00000100
 109 #define XCHAL_WINDOW_UF12_VECOFS        0x00000140
 110 #endif
 111
 112 #if XCHAL_HAVE_WINDOWED
 113 #define WINDOW_VECTORS \
 114    [EXC_WINDOW_OVERFLOW4] = XCHAL_WINDOW_OF4_VECOFS + \
 115        XCHAL_WINDOW_VECTORS_VADDR, \
 116    [EXC_WINDOW_UNDERFLOW4] = XCHAL_WINDOW_UF4_VECOFS + \
 117        XCHAL_WINDOW_VECTORS_VADDR, \
 118    [EXC_WINDOW_OVERFLOW8] = XCHAL_WINDOW_OF8_VECOFS + \
 119        XCHAL_WINDOW_VECTORS_VADDR, \
 120    [EXC_WINDOW_UNDERFLOW8] = XCHAL_WINDOW_UF8_VECOFS + \
 121        XCHAL_WINDOW_VECTORS_VADDR, \
 122    [EXC_WINDOW_OVERFLOW12] = XCHAL_WINDOW_OF12_VECOFS + \
 123        XCHAL_WINDOW_VECTORS_VADDR, \
 124    [EXC_WINDOW_UNDERFLOW12] = XCHAL_WINDOW_UF12_VECOFS + \
 125        XCHAL_WINDOW_VECTORS_VADDR,
 126 #else
 127 #define WINDOW_VECTORS
 128 #endif
 129
 130 #define EXCEPTION_VECTORS { \
 131         [EXC_RESET] = XCHAL_RESET_VECTOR_VADDR, \
 132         WINDOW_VECTORS \
 133         [EXC_KERNEL] = XCHAL_KERNEL_VECTOR_VADDR, \
 134         [EXC_USER] = XCHAL_USER_VECTOR_VADDR, \
 135         [EXC_DOUBLE] = XCHAL_DOUBLEEXC_VECTOR_VADDR, \
 136         [EXC_DEBUG] = XCHAL_DEBUG_VECTOR_VADDR, \
 137     }
 138
 139 #define INTERRUPT_VECTORS { \
 140         0, \
 141         0, \
 142         XCHAL_INTLEVEL2_VECTOR_VADDR, \
 143         XCHAL_INTLEVEL3_VECTOR_VADDR, \
 144         XCHAL_INTLEVEL4_VECTOR_VADDR, \
 145         XCHAL_INTLEVEL5_VECTOR_VADDR, \
 146         XCHAL_INTLEVEL6_VECTOR_VADDR, \
 147         XCHAL_INTLEVEL7_VECTOR_VADDR, \
 148     }
 149
 150 #define LEVEL_MASKS { \
 151         [1] = XCHAL_INTLEVEL1_MASK, \
 152         [2] = XCHAL_INTLEVEL2_MASK, \
 153         [3] = XCHAL_INTLEVEL3_MASK, \
 154         [4] = XCHAL_INTLEVEL4_MASK, \
 155         [5] = XCHAL_INTLEVEL5_MASK, \
 156         [6] = XCHAL_INTLEVEL6_MASK, \
 157         [7] = XCHAL_INTLEVEL7_MASK, \
 158     }
 159
 160 #define INTTYPE_MASKS { \
 161         [INTTYPE_EDGE] = XCHAL_INTTYPE_MASK_EXTERN_EDGE, \
 162         [INTTYPE_NMI] = XCHAL_INTTYPE_MASK_NMI, \
 163         [INTTYPE_SOFTWARE] = XCHAL_INTTYPE_MASK_SOFTWARE, \
 164     }
 165
 166 #define XTHAL_INTTYPE_EXTERN_LEVEL INTTYPE_LEVEL
 167 #define XTHAL_INTTYPE_EXTERN_EDGE INTTYPE_EDGE
 168 #define XTHAL_INTTYPE_NMI INTTYPE_NMI
 169 #define XTHAL_INTTYPE_SOFTWARE INTTYPE_SOFTWARE
 170 #define XTHAL_INTTYPE_TIMER INTTYPE_TIMER
 171 #define XTHAL_INTTYPE_TBD1 INTTYPE_DEBUG
 172 #define XTHAL_INTTYPE_TBD2 INTTYPE_WRITE_ERR
 173 #define XTHAL_INTTYPE_WRITE_ERROR INTTYPE_WRITE_ERR
 174 #define XTHAL_INTTYPE_PROFILING INTTYPE_PROFILING
 175
 176
 177 #define INTERRUPT(i) { \
 178         .level = XCHAL_INT ## i ## _LEVEL, \
 179         .inttype = XCHAL_INT ## i ## _TYPE, \
 180     }
 181
 182 #define INTERRUPTS { \
 183         [0] = INTERRUPT(0), \
 184         [1] = INTERRUPT(1), \
 185         [2] = INTERRUPT(2), \
 186         [3] = INTERRUPT(3), \
 187         [4] = INTERRUPT(4), \
 188         [5] = INTERRUPT(5), \
 189         [6] = INTERRUPT(6), \
 190         [7] = INTERRUPT(7), \
 191         [8] = INTERRUPT(8), \
 192         [9] = INTERRUPT(9), \
 193         [10] = INTERRUPT(10), \
 194         [11] = INTERRUPT(11), \
 195         [12] = INTERRUPT(12), \
 196         [13] = INTERRUPT(13), \
 197         [14] = INTERRUPT(14), \
 198         [15] = INTERRUPT(15), \
 199         [16] = INTERRUPT(16), \
 200         [17] = INTERRUPT(17), \
 201         [18] = INTERRUPT(18), \
 202         [19] = INTERRUPT(19), \
 203         [20] = INTERRUPT(20), \
 204         [21] = INTERRUPT(21), \
 205         [22] = INTERRUPT(22), \
 206         [23] = INTERRUPT(23), \
 207         [24] = INTERRUPT(24), \
 208         [25] = INTERRUPT(25), \
 209         [26] = INTERRUPT(26), \
 210         [27] = INTERRUPT(27), \
 211         [28] = INTERRUPT(28), \
 212         [29] = INTERRUPT(29), \
 213         [30] = INTERRUPT(30), \
 214         [31] = INTERRUPT(31), \
 215     }
 216
 217 #define TIMERINTS { \
 218         [0] = XCHAL_TIMER0_INTERRUPT, \
 219         [1] = XCHAL_TIMER1_INTERRUPT, \
 220         [2] = XCHAL_TIMER2_INTERRUPT, \
 221     }
 222
 223 #define EXTINTS { \
 224         [0] = XCHAL_EXTINT0_NUM, \
 225         [1] = XCHAL_EXTINT1_NUM, \
 226         [2] = XCHAL_EXTINT2_NUM, \
 227         [3] = XCHAL_EXTINT3_NUM, \
 228         [4] = XCHAL_EXTINT4_NUM, \
 229         [5] = XCHAL_EXTINT5_NUM, \
 230         [6] = XCHAL_EXTINT6_NUM, \
 231         [7] = XCHAL_EXTINT7_NUM, \
 232         [8] = XCHAL_EXTINT8_NUM, \
 233         [9] = XCHAL_EXTINT9_NUM, \
 234         [10] = XCHAL_EXTINT10_NUM, \
 235         [11] = XCHAL_EXTINT11_NUM, \
 236         [12] = XCHAL_EXTINT12_NUM, \
 237         [13] = XCHAL_EXTINT13_NUM, \
 238         [14] = XCHAL_EXTINT14_NUM, \
 239         [15] = XCHAL_EXTINT15_NUM, \
 240         [16] = XCHAL_EXTINT16_NUM, \
 241         [17] = XCHAL_EXTINT17_NUM, \
 242         [18] = XCHAL_EXTINT18_NUM, \
 243         [19] = XCHAL_EXTINT19_NUM, \
 244         [20] = XCHAL_EXTINT20_NUM, \
 245         [21] = XCHAL_EXTINT21_NUM, \
 246         [22] = XCHAL_EXTINT22_NUM, \
 247         [23] = XCHAL_EXTINT23_NUM, \
 248         [24] = XCHAL_EXTINT24_NUM, \
 249         [25] = XCHAL_EXTINT25_NUM, \
 250         [26] = XCHAL_EXTINT26_NUM, \
 251         [27] = XCHAL_EXTINT27_NUM, \
 252         [28] = XCHAL_EXTINT28_NUM, \
 253         [29] = XCHAL_EXTINT29_NUM, \
 254         [30] = XCHAL_EXTINT30_NUM, \
 255         [31] = XCHAL_EXTINT31_NUM, \
 256     }
 257
 258 #define EXCEPTIONS_SECTION \
 259     .excm_level = XCHAL_EXCM_LEVEL, \
 260     .vecbase = XCHAL_VECBASE_RESET_VADDR, \
 261     .exception_vector = EXCEPTION_VECTORS
 262
 263 #define INTERRUPTS_SECTION \
 264     .ninterrupt = XCHAL_NUM_INTERRUPTS, \
 265     .nlevel = XCHAL_NUM_INTLEVELS, \
 266     .interrupt_vector = INTERRUPT_VECTORS, \
 267     .level_mask = LEVEL_MASKS, \
 268     .inttype_mask = INTTYPE_MASKS, \
 269     .interrupt = INTERRUPTS, \
 270     .nccompare = XCHAL_NUM_TIMERS, \
 271     .timerint = TIMERINTS, \
 272     .nextint = XCHAL_NUM_EXTINTERRUPTS, \
 273     .extint = EXTINTS
 274
 275 #if XCHAL_HAVE_PTP_MMU
 276
 277 #define TLB_TEMPLATE(ways, refill_way_size, way56) { \
 278         .nways = ways, \
 279         .way_size = { \
 280             (refill_way_size), (refill_way_size), \
 281             (refill_way_size), (refill_way_size), \
 282             4, (way56) ? 4 : 2, (way56) ? 8 : 2, 1, 1, 1, \
 283         }, \
 284         .varway56 = (way56), \
 285         .nrefillentries = (refill_way_size) * 4, \
 286     }
 287
 288 #define ITLB(varway56) \
 289     TLB_TEMPLATE(7, 1 << XCHAL_ITLB_ARF_ENTRIES_LOG2, varway56)
 290
 291 #define DTLB(varway56) \
 292     TLB_TEMPLATE(10, 1 << XCHAL_DTLB_ARF_ENTRIES_LOG2, varway56)
 293
 294 #define TLB_SECTION \
 295     .itlb = ITLB(XCHAL_HAVE_SPANNING_WAY), \
 296     .dtlb = DTLB(XCHAL_HAVE_SPANNING_WAY)
 297
 298 #elif XCHAL_HAVE_XLT_CACHEATTR || XCHAL_HAVE_MIMIC_CACHEATTR
 299
 300 #define TLB_TEMPLATE { \
 301         .nways = 1, \
 302         .way_size = { \
 303             8, \
 304         } \
 305     }
 306
 307 #define TLB_SECTION \
 308     .itlb = TLB_TEMPLATE, \
 309     .dtlb = TLB_TEMPLATE
 310
 311 #endif
 312
 313 #if (defined(TARGET_WORDS_BIGENDIAN) != 0) == (XCHAL_HAVE_BE != 0)
 314 #define REGISTER_CORE(core) \
 315     static void __attribute__((constructor)) register_core(void) \
 316     { \
 317         static XtensaConfigList node = { \
 318             .config = &core, \
 319         }; \
 320         xtensa_finalize_config(&core); \
 321         xtensa_register_core(&node); \
 322     }
 323 #else
 324 #define REGISTER_CORE(core)
 325 #endif
 326
 327 #define DEBUG_SECTION \
 328     .debug_level = XCHAL_DEBUGLEVEL, \
 329     .nibreak = XCHAL_NUM_IBREAK, \
 330     .ndbreak = XCHAL_NUM_DBREAK
 331
 332 #define CONFIG_SECTION \
 333     .configid = { \
 334         XCHAL_HW_CONFIGID0, \
 335         XCHAL_HW_CONFIGID1, \
 336     }
 337
 338 #define DEFAULT_SECTIONS \
 339     .options = XTENSA_OPTIONS, \
 340     .nareg = XCHAL_NUM_AREGS, \
 341     .ndepc = (XCHAL_XEA_VERSION >= 2), \
 342     EXCEPTIONS_SECTION, \
 343     INTERRUPTS_SECTION, \
 344     TLB_SECTION, \
 345     DEBUG_SECTION, \
 346     CONFIG_SECTION
 347
 348
 349 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 2
 350 #define XCHAL_INTLEVEL2_VECTOR_VADDR 0
 351 #endif
 352 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 3
 353 #define XCHAL_INTLEVEL3_VECTOR_VADDR 0
 354 #endif
 355 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 4
 356 #define XCHAL_INTLEVEL4_VECTOR_VADDR 0
 357 #endif
 358 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 5
 359 #define XCHAL_INTLEVEL5_VECTOR_VADDR 0
 360 #endif
 361 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 6
 362 #define XCHAL_INTLEVEL6_VECTOR_VADDR 0
 363 #endif
 364 #if XCHAL_NUM_INTLEVELS + XCHAL_HAVE_NMI + 1 <= 7
 365 #define XCHAL_INTLEVEL7_VECTOR_VADDR 0
 366 #endif
 367
 368
 369 #if XCHAL_NUM_INTERRUPTS <= 0
 370 #define XCHAL_INT0_LEVEL 0
 371 #define XCHAL_INT0_TYPE 0
 372 #endif
 373 #if XCHAL_NUM_INTERRUPTS <= 1
 374 #define XCHAL_INT1_LEVEL 0
 375 #define XCHAL_INT1_TYPE 0
 376 #endif
 377 #if XCHAL_NUM_INTERRUPTS <= 2
 378 #define XCHAL_INT2_LEVEL 0
 379 #define XCHAL_INT2_TYPE 0
 380 #endif
 381 #if XCHAL_NUM_INTERRUPTS <= 3
 382 #define XCHAL_INT3_LEVEL 0
 383 #define XCHAL_INT3_TYPE 0
 384 #endif
 385 #if XCHAL_NUM_INTERRUPTS <= 4
 386 #define XCHAL_INT4_LEVEL 0
 387 #define XCHAL_INT4_TYPE 0
 388 #endif
 389 #if XCHAL_NUM_INTERRUPTS <= 5
 390 #define XCHAL_INT5_LEVEL 0
 391 #define XCHAL_INT5_TYPE 0
 392 #endif
 393 #if XCHAL_NUM_INTERRUPTS <= 6
 394 #define XCHAL_INT6_LEVEL 0
 395 #define XCHAL_INT6_TYPE 0
 396 #endif
 397 #if XCHAL_NUM_INTERRUPTS <= 7
 398 #define XCHAL_INT7_LEVEL 0
 399 #define XCHAL_INT7_TYPE 0
 400 #endif
 401 #if XCHAL_NUM_INTERRUPTS <= 8
 402 #define XCHAL_INT8_LEVEL 0
 403 #define XCHAL_INT8_TYPE 0
 404 #endif
 405 #if XCHAL_NUM_INTERRUPTS <= 9
 406 #define XCHAL_INT9_LEVEL 0
 407 #define XCHAL_INT9_TYPE 0
 408 #endif
 409 #if XCHAL_NUM_INTERRUPTS <= 10
 410 #define XCHAL_INT10_LEVEL 0
 411 #define XCHAL_INT10_TYPE 0
 412 #endif
 413 #if XCHAL_NUM_INTERRUPTS <= 11
 414 #define XCHAL_INT11_LEVEL 0
 415 #define XCHAL_INT11_TYPE 0
 416 #endif
 417 #if XCHAL_NUM_INTERRUPTS <= 12
 418 #define XCHAL_INT12_LEVEL 0
 419 #define XCHAL_INT12_TYPE 0
 420 #endif
 421 #if XCHAL_NUM_INTERRUPTS <= 13
 422 #define XCHAL_INT13_LEVEL 0
 423 #define XCHAL_INT13_TYPE 0
 424 #endif
 425 #if XCHAL_NUM_INTERRUPTS <= 14
 426 #define XCHAL_INT14_LEVEL 0
 427 #define XCHAL_INT14_TYPE 0
 428 #endif
 429 #if XCHAL_NUM_INTERRUPTS <= 15
 430 #define XCHAL_INT15_LEVEL 0
 431 #define XCHAL_INT15_TYPE 0
 432 #endif
 433 #if XCHAL_NUM_INTERRUPTS <= 16
 434 #define XCHAL_INT16_LEVEL 0
 435 #define XCHAL_INT16_TYPE 0
 436 #endif
 437 #if XCHAL_NUM_INTERRUPTS <= 17
 438 #define XCHAL_INT17_LEVEL 0
 439 #define XCHAL_INT17_TYPE 0
 440 #endif
 441 #if XCHAL_NUM_INTERRUPTS <= 18
 442 #define XCHAL_INT18_LEVEL 0
 443 #define XCHAL_INT18_TYPE 0
 444 #endif
 445 #if XCHAL_NUM_INTERRUPTS <= 19
 446 #define XCHAL_INT19_LEVEL 0
 447 #define XCHAL_INT19_TYPE 0
 448 #endif
 449 #if XCHAL_NUM_INTERRUPTS <= 20
 450 #define XCHAL_INT20_LEVEL 0
 451 #define XCHAL_INT20_TYPE 0
 452 #endif
 453 #if XCHAL_NUM_INTERRUPTS <= 21
 454 #define XCHAL_INT21_LEVEL 0
 455 #define XCHAL_INT21_TYPE 0
 456 #endif
 457 #if XCHAL_NUM_INTERRUPTS <= 22
 458 #define XCHAL_INT22_LEVEL 0
 459 #define XCHAL_INT22_TYPE 0
 460 #endif
 461 #if XCHAL_NUM_INTERRUPTS <= 23
 462 #define XCHAL_INT23_LEVEL 0
 463 #define XCHAL_INT23_TYPE 0
 464 #endif
 465 #if XCHAL_NUM_INTERRUPTS <= 24
 466 #define XCHAL_INT24_LEVEL 0
 467 #define XCHAL_INT24_TYPE 0
 468 #endif
 469 #if XCHAL_NUM_INTERRUPTS <= 25
 470 #define XCHAL_INT25_LEVEL 0
 471 #define XCHAL_INT25_TYPE 0
 472 #endif
 473 #if XCHAL_NUM_INTERRUPTS <= 26
 474 #define XCHAL_INT26_LEVEL 0
 475 #define XCHAL_INT26_TYPE 0
 476 #endif
 477 #if XCHAL_NUM_INTERRUPTS <= 27
 478 #define XCHAL_INT27_LEVEL 0
 479 #define XCHAL_INT27_TYPE 0
 480 #endif
 481 #if XCHAL_NUM_INTERRUPTS <= 28
 482 #define XCHAL_INT28_LEVEL 0
 483 #define XCHAL_INT28_TYPE 0
 484 #endif
 485 #if XCHAL_NUM_INTERRUPTS <= 29
 486 #define XCHAL_INT29_LEVEL 0
 487 #define XCHAL_INT29_TYPE 0
 488 #endif
 489 #if XCHAL_NUM_INTERRUPTS <= 30
 490 #define XCHAL_INT30_LEVEL 0
 491 #define XCHAL_INT30_TYPE 0
 492 #endif
 493 #if XCHAL_NUM_INTERRUPTS <= 31
 494 #define XCHAL_INT31_LEVEL 0
 495 #define XCHAL_INT31_TYPE 0
 496 #endif
 497
 498
 499 #if XCHAL_NUM_EXTINTERRUPTS <= 0
 500 #define XCHAL_EXTINT0_NUM 0
 501 #endif
 502 #if XCHAL_NUM_EXTINTERRUPTS <= 1
 503 #define XCHAL_EXTINT1_NUM 0
 504 #endif
 505 #if XCHAL_NUM_EXTINTERRUPTS <= 2
 506 #define XCHAL_EXTINT2_NUM 0
 507 #endif
 508 #if XCHAL_NUM_EXTINTERRUPTS <= 3
 509 #define XCHAL_EXTINT3_NUM 0
 510 #endif
 511 #if XCHAL_NUM_EXTINTERRUPTS <= 4
 512 #define XCHAL_EXTINT4_NUM 0
 513 #endif
 514 #if XCHAL_NUM_EXTINTERRUPTS <= 5
 515 #define XCHAL_EXTINT5_NUM 0
 516 #endif
 517 #if XCHAL_NUM_EXTINTERRUPTS <= 6
 518 #define XCHAL_EXTINT6_NUM 0
 519 #endif
 520 #if XCHAL_NUM_EXTINTERRUPTS <= 7
 521 #define XCHAL_EXTINT7_NUM 0
 522 #endif
 523 #if XCHAL_NUM_EXTINTERRUPTS <= 8
 524 #define XCHAL_EXTINT8_NUM 0
 525 #endif
 526 #if XCHAL_NUM_EXTINTERRUPTS <= 9
 527 #define XCHAL_EXTINT9_NUM 0
 528 #endif
 529 #if XCHAL_NUM_EXTINTERRUPTS <= 10
 530 #define XCHAL_EXTINT10_NUM 0
 531 #endif
 532 #if XCHAL_NUM_EXTINTERRUPTS <= 11
 533 #define XCHAL_EXTINT11_NUM 0
 534 #endif
 535 #if XCHAL_NUM_EXTINTERRUPTS <= 12
 536 #define XCHAL_EXTINT12_NUM 0
 537 #endif
 538 #if XCHAL_NUM_EXTINTERRUPTS <= 13
 539 #define XCHAL_EXTINT13_NUM 0
 540 #endif
 541 #if XCHAL_NUM_EXTINTERRUPTS <= 14
 542 #define XCHAL_EXTINT14_NUM 0
 543 #endif
 544 #if XCHAL_NUM_EXTINTERRUPTS <= 15
 545 #define XCHAL_EXTINT15_NUM 0
 546 #endif
 547 #if XCHAL_NUM_EXTINTERRUPTS <= 16
 548 #define XCHAL_EXTINT16_NUM 0
 549 #endif
 550 #if XCHAL_NUM_EXTINTERRUPTS <= 17
 551 #define XCHAL_EXTINT17_NUM 0
 552 #endif
 553 #if XCHAL_NUM_EXTINTERRUPTS <= 18
 554 #define XCHAL_EXTINT18_NUM 0
 555 #endif
 556 #if XCHAL_NUM_EXTINTERRUPTS <= 19
 557 #define XCHAL_EXTINT19_NUM 0
 558 #endif
 559 #if XCHAL_NUM_EXTINTERRUPTS <= 20
 560 #define XCHAL_EXTINT20_NUM 0
 561 #endif
 562 #if XCHAL_NUM_EXTINTERRUPTS <= 21
 563 #define XCHAL_EXTINT21_NUM 0
 564 #endif
 565 #if XCHAL_NUM_EXTINTERRUPTS <= 22
 566 #define XCHAL_EXTINT22_NUM 0
 567 #endif
 568 #if XCHAL_NUM_EXTINTERRUPTS <= 23
 569 #define XCHAL_EXTINT23_NUM 0
 570 #endif
 571 #if XCHAL_NUM_EXTINTERRUPTS <= 24
 572 #define XCHAL_EXTINT24_NUM 0
 573 #endif
 574 #if XCHAL_NUM_EXTINTERRUPTS <= 25
 575 #define XCHAL_EXTINT25_NUM 0
 576 #endif
 577 #if XCHAL_NUM_EXTINTERRUPTS <= 26
 578 #define XCHAL_EXTINT26_NUM 0
 579 #endif
 580 #if XCHAL_NUM_EXTINTERRUPTS <= 27
 581 #define XCHAL_EXTINT27_NUM 0
 582 #endif
 583 #if XCHAL_NUM_EXTINTERRUPTS <= 28
 584 #define XCHAL_EXTINT28_NUM 0
 585 #endif
 586 #if XCHAL_NUM_EXTINTERRUPTS <= 29
 587 #define XCHAL_EXTINT29_NUM 0
 588 #endif
 589 #if XCHAL_NUM_EXTINTERRUPTS <= 30
 590 #define XCHAL_EXTINT30_NUM 0
 591 #endif
 592 #if XCHAL_NUM_EXTINTERRUPTS <= 31
 593 #define XCHAL_EXTINT31_NUM 0
 594 #endif
 595
 596
 597 #define XTHAL_TIMER_UNCONFIGURED 0