2 * PowerPC emulation cpu definitions for qemu.
4 * Copyright (c) 2003-2007 Jocelyn Mayer
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
19 #if !defined (__CPU_PPC_H__)
22 #include "qemu-common.h"
24 //#define PPC_EMULATE_32BITS_HYPV
26 #if defined (TARGET_PPC64)
27 /* PowerPC 64 definitions */
28 #define TARGET_LONG_BITS 64
29 #define TARGET_PAGE_BITS 12
31 #define TARGET_IS_BIENDIAN 1
33 /* Note that the official physical address space bits is 62-M where M
34 is implementation dependent. I've not looked up M for the set of
35 cpus we emulate at the system level. */
36 #define TARGET_PHYS_ADDR_SPACE_BITS 62
38 /* Note that the PPC environment architecture talks about 80 bit virtual
39 addresses, with segmentation. Obviously that's not all visible to a
40 single process, which is all we're concerned with here. */
42 # define TARGET_VIRT_ADDR_SPACE_BITS 32
44 # define TARGET_VIRT_ADDR_SPACE_BITS 64
47 #define TARGET_PAGE_BITS_64K 16
48 #define TARGET_PAGE_BITS_16M 24
50 #else /* defined (TARGET_PPC64) */
51 /* PowerPC 32 definitions */
52 #define TARGET_LONG_BITS 32
54 #if defined(TARGET_PPCEMB)
55 /* Specific definitions for PowerPC embedded */
56 /* BookE have 36 bits physical address space */
57 #if defined(CONFIG_USER_ONLY)
58 /* It looks like a lot of Linux programs assume page size
59 * is 4kB long. This is evil, but we have to deal with it...
61 #define TARGET_PAGE_BITS 12
62 #else /* defined(CONFIG_USER_ONLY) */
63 /* Pages can be 1 kB small */
64 #define TARGET_PAGE_BITS 10
65 #endif /* defined(CONFIG_USER_ONLY) */
66 #else /* defined(TARGET_PPCEMB) */
67 /* "standard" PowerPC 32 definitions */
68 #define TARGET_PAGE_BITS 12
69 #endif /* defined(TARGET_PPCEMB) */
71 #define TARGET_PHYS_ADDR_SPACE_BITS 36
72 #define TARGET_VIRT_ADDR_SPACE_BITS 32
74 #endif /* defined (TARGET_PPC64) */
76 #define CPUArchState struct CPUPPCState
78 #include "exec/cpu-defs.h"
80 #include "fpu/softfloat.h"
82 #if defined (TARGET_PPC64)
83 #define PPC_ELF_MACHINE EM_PPC64
85 #define PPC_ELF_MACHINE EM_PPC
88 /*****************************************************************************/
90 typedef enum powerpc_mmu_t powerpc_mmu_t;
92 POWERPC_MMU_UNKNOWN = 0x00000000,
93 /* Standard 32 bits PowerPC MMU */
94 POWERPC_MMU_32B = 0x00000001,
95 /* PowerPC 6xx MMU with software TLB */
96 POWERPC_MMU_SOFT_6xx = 0x00000002,
97 /* PowerPC 74xx MMU with software TLB */
98 POWERPC_MMU_SOFT_74xx = 0x00000003,
99 /* PowerPC 4xx MMU with software TLB */
100 POWERPC_MMU_SOFT_4xx = 0x00000004,
101 /* PowerPC 4xx MMU with software TLB and zones protections */
102 POWERPC_MMU_SOFT_4xx_Z = 0x00000005,
103 /* PowerPC MMU in real mode only */
104 POWERPC_MMU_REAL = 0x00000006,
105 /* Freescale MPC8xx MMU model */
106 POWERPC_MMU_MPC8xx = 0x00000007,
107 /* BookE MMU model */
108 POWERPC_MMU_BOOKE = 0x00000008,
109 /* BookE 2.06 MMU model */
110 POWERPC_MMU_BOOKE206 = 0x00000009,
111 /* PowerPC 601 MMU model (specific BATs format) */
112 POWERPC_MMU_601 = 0x0000000A,
113 #if defined(TARGET_PPC64)
114 #define POWERPC_MMU_64 0x00010000
115 #define POWERPC_MMU_1TSEG 0x00020000
116 #define POWERPC_MMU_AMR 0x00040000
117 /* 64 bits PowerPC MMU */
118 POWERPC_MMU_64B = POWERPC_MMU_64 | 0x00000001,
119 /* Architecture 2.03 and later (has LPCR) */
120 POWERPC_MMU_2_03 = POWERPC_MMU_64 | 0x00000002,
121 /* Architecture 2.06 variant */
122 POWERPC_MMU_2_06 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
123 | POWERPC_MMU_AMR | 0x00000003,
124 /* Architecture 2.06 "degraded" (no 1T segments) */
125 POWERPC_MMU_2_06a = POWERPC_MMU_64 | POWERPC_MMU_AMR
127 /* Architecture 2.07 variant */
128 POWERPC_MMU_2_07 = POWERPC_MMU_64 | POWERPC_MMU_1TSEG
129 | POWERPC_MMU_AMR | 0x00000004,
130 /* Architecture 2.07 "degraded" (no 1T segments) */
131 POWERPC_MMU_2_07a = POWERPC_MMU_64 | POWERPC_MMU_AMR
133 #endif /* defined(TARGET_PPC64) */
136 /*****************************************************************************/
137 /* Exception model */
138 typedef enum powerpc_excp_t powerpc_excp_t;
139 enum powerpc_excp_t {
140 POWERPC_EXCP_UNKNOWN = 0,
141 /* Standard PowerPC exception model */
143 /* PowerPC 40x exception model */
145 /* PowerPC 601 exception model */
147 /* PowerPC 602 exception model */
149 /* PowerPC 603 exception model */
151 /* PowerPC 603e exception model */
153 /* PowerPC G2 exception model */
155 /* PowerPC 604 exception model */
157 /* PowerPC 7x0 exception model */
159 /* PowerPC 7x5 exception model */
161 /* PowerPC 74xx exception model */
163 /* BookE exception model */
165 #if defined(TARGET_PPC64)
166 /* PowerPC 970 exception model */
168 /* POWER7 exception model */
170 /* POWER8 exception model */
172 #endif /* defined(TARGET_PPC64) */
175 /*****************************************************************************/
176 /* Exception vectors definitions */
178 POWERPC_EXCP_NONE = -1,
179 /* The 64 first entries are used by the PowerPC embedded specification */
180 POWERPC_EXCP_CRITICAL = 0, /* Critical input */
181 POWERPC_EXCP_MCHECK = 1, /* Machine check exception */
182 POWERPC_EXCP_DSI = 2, /* Data storage exception */
183 POWERPC_EXCP_ISI = 3, /* Instruction storage exception */
184 POWERPC_EXCP_EXTERNAL = 4, /* External input */
185 POWERPC_EXCP_ALIGN = 5, /* Alignment exception */
186 POWERPC_EXCP_PROGRAM = 6, /* Program exception */
187 POWERPC_EXCP_FPU = 7, /* Floating-point unavailable exception */
188 POWERPC_EXCP_SYSCALL = 8, /* System call exception */
189 POWERPC_EXCP_APU = 9, /* Auxiliary processor unavailable */
190 POWERPC_EXCP_DECR = 10, /* Decrementer exception */
191 POWERPC_EXCP_FIT = 11, /* Fixed-interval timer interrupt */
192 POWERPC_EXCP_WDT = 12, /* Watchdog timer interrupt */
193 POWERPC_EXCP_DTLB = 13, /* Data TLB miss */
194 POWERPC_EXCP_ITLB = 14, /* Instruction TLB miss */
195 POWERPC_EXCP_DEBUG = 15, /* Debug interrupt */
196 /* Vectors 16 to 31 are reserved */
197 POWERPC_EXCP_SPEU = 32, /* SPE/embedded floating-point unavailable */
198 POWERPC_EXCP_EFPDI = 33, /* Embedded floating-point data interrupt */
199 POWERPC_EXCP_EFPRI = 34, /* Embedded floating-point round interrupt */
200 POWERPC_EXCP_EPERFM = 35, /* Embedded performance monitor interrupt */
201 POWERPC_EXCP_DOORI = 36, /* Embedded doorbell interrupt */
202 POWERPC_EXCP_DOORCI = 37, /* Embedded doorbell critical interrupt */
203 POWERPC_EXCP_GDOORI = 38, /* Embedded guest doorbell interrupt */
204 POWERPC_EXCP_GDOORCI = 39, /* Embedded guest doorbell critical interrupt*/
205 POWERPC_EXCP_HYPPRIV = 41, /* Embedded hypervisor priv instruction */
206 /* Vectors 42 to 63 are reserved */
207 /* Exceptions defined in the PowerPC server specification */
208 POWERPC_EXCP_RESET = 64, /* System reset exception */
209 POWERPC_EXCP_DSEG = 65, /* Data segment exception */
210 POWERPC_EXCP_ISEG = 66, /* Instruction segment exception */
211 POWERPC_EXCP_HDECR = 67, /* Hypervisor decrementer exception */
212 POWERPC_EXCP_TRACE = 68, /* Trace exception */
213 POWERPC_EXCP_HDSI = 69, /* Hypervisor data storage exception */
214 POWERPC_EXCP_HISI = 70, /* Hypervisor instruction storage exception */
215 POWERPC_EXCP_HDSEG = 71, /* Hypervisor data segment exception */
216 POWERPC_EXCP_HISEG = 72, /* Hypervisor instruction segment exception */
217 POWERPC_EXCP_VPU = 73, /* Vector unavailable exception */
218 /* 40x specific exceptions */
219 POWERPC_EXCP_PIT = 74, /* Programmable interval timer interrupt */
220 /* 601 specific exceptions */
221 POWERPC_EXCP_IO = 75, /* IO error exception */
222 POWERPC_EXCP_RUNM = 76, /* Run mode exception */
223 /* 602 specific exceptions */
224 POWERPC_EXCP_EMUL = 77, /* Emulation trap exception */
225 /* 602/603 specific exceptions */
226 POWERPC_EXCP_IFTLB = 78, /* Instruction fetch TLB miss */
227 POWERPC_EXCP_DLTLB = 79, /* Data load TLB miss */
228 POWERPC_EXCP_DSTLB = 80, /* Data store TLB miss */
229 /* Exceptions available on most PowerPC */
230 POWERPC_EXCP_FPA = 81, /* Floating-point assist exception */
231 POWERPC_EXCP_DABR = 82, /* Data address breakpoint */
232 POWERPC_EXCP_IABR = 83, /* Instruction address breakpoint */
233 POWERPC_EXCP_SMI = 84, /* System management interrupt */
234 POWERPC_EXCP_PERFM = 85, /* Embedded performance monitor interrupt */
235 /* 7xx/74xx specific exceptions */
236 POWERPC_EXCP_THERM = 86, /* Thermal interrupt */
237 /* 74xx specific exceptions */
238 POWERPC_EXCP_VPUA = 87, /* Vector assist exception */
239 /* 970FX specific exceptions */
240 POWERPC_EXCP_SOFTP = 88, /* Soft patch exception */
241 POWERPC_EXCP_MAINT = 89, /* Maintenance exception */
242 /* Freescale embedded cores specific exceptions */
243 POWERPC_EXCP_MEXTBR = 90, /* Maskable external breakpoint */
244 POWERPC_EXCP_NMEXTBR = 91, /* Non maskable external breakpoint */
245 POWERPC_EXCP_ITLBE = 92, /* Instruction TLB error */
246 POWERPC_EXCP_DTLBE = 93, /* Data TLB error */
247 /* VSX Unavailable (Power ISA 2.06 and later) */
248 POWERPC_EXCP_VSXU = 94, /* VSX Unavailable */
249 POWERPC_EXCP_FU = 95, /* Facility Unavailable */
251 POWERPC_EXCP_NB = 96,
252 /* QEMU exceptions: used internally during code translation */
253 POWERPC_EXCP_STOP = 0x200, /* stop translation */
254 POWERPC_EXCP_BRANCH = 0x201, /* branch instruction */
255 /* QEMU exceptions: special cases we want to stop translation */
256 POWERPC_EXCP_SYNC = 0x202, /* context synchronizing instruction */
257 POWERPC_EXCP_SYSCALL_USER = 0x203, /* System call in user mode only */
258 POWERPC_EXCP_STCX = 0x204 /* Conditional stores in user mode */
261 /* Exceptions error codes */
263 /* Exception subtypes for POWERPC_EXCP_ALIGN */
264 POWERPC_EXCP_ALIGN_FP = 0x01, /* FP alignment exception */
265 POWERPC_EXCP_ALIGN_LST = 0x02, /* Unaligned mult/extern load/store */
266 POWERPC_EXCP_ALIGN_LE = 0x03, /* Multiple little-endian access */
267 POWERPC_EXCP_ALIGN_PROT = 0x04, /* Access cross protection boundary */
268 POWERPC_EXCP_ALIGN_BAT = 0x05, /* Access cross a BAT/seg boundary */
269 POWERPC_EXCP_ALIGN_CACHE = 0x06, /* Impossible dcbz access */
270 /* Exception subtypes for POWERPC_EXCP_PROGRAM */
272 POWERPC_EXCP_FP = 0x10,
273 POWERPC_EXCP_FP_OX = 0x01, /* FP overflow */
274 POWERPC_EXCP_FP_UX = 0x02, /* FP underflow */
275 POWERPC_EXCP_FP_ZX = 0x03, /* FP divide by zero */
276 POWERPC_EXCP_FP_XX = 0x04, /* FP inexact */
277 POWERPC_EXCP_FP_VXSNAN = 0x05, /* FP invalid SNaN op */
278 POWERPC_EXCP_FP_VXISI = 0x06, /* FP invalid infinite subtraction */
279 POWERPC_EXCP_FP_VXIDI = 0x07, /* FP invalid infinite divide */
280 POWERPC_EXCP_FP_VXZDZ = 0x08, /* FP invalid zero divide */
281 POWERPC_EXCP_FP_VXIMZ = 0x09, /* FP invalid infinite * zero */
282 POWERPC_EXCP_FP_VXVC = 0x0A, /* FP invalid compare */
283 POWERPC_EXCP_FP_VXSOFT = 0x0B, /* FP invalid operation */
284 POWERPC_EXCP_FP_VXSQRT = 0x0C, /* FP invalid square root */
285 POWERPC_EXCP_FP_VXCVI = 0x0D, /* FP invalid integer conversion */
286 /* Invalid instruction */
287 POWERPC_EXCP_INVAL = 0x20,
288 POWERPC_EXCP_INVAL_INVAL = 0x01, /* Invalid instruction */
289 POWERPC_EXCP_INVAL_LSWX = 0x02, /* Invalid lswx instruction */
290 POWERPC_EXCP_INVAL_SPR = 0x03, /* Invalid SPR access */
291 POWERPC_EXCP_INVAL_FP = 0x04, /* Unimplemented mandatory fp instr */
292 /* Privileged instruction */
293 POWERPC_EXCP_PRIV = 0x30,
294 POWERPC_EXCP_PRIV_OPC = 0x01, /* Privileged operation exception */
295 POWERPC_EXCP_PRIV_REG = 0x02, /* Privileged register exception */
297 POWERPC_EXCP_TRAP = 0x40,
300 /*****************************************************************************/
301 /* Input pins model */
302 typedef enum powerpc_input_t powerpc_input_t;
303 enum powerpc_input_t {
304 PPC_FLAGS_INPUT_UNKNOWN = 0,
305 /* PowerPC 6xx bus */
308 PPC_FLAGS_INPUT_BookE,
309 /* PowerPC 405 bus */
311 /* PowerPC 970 bus */
313 /* PowerPC POWER7 bus */
314 PPC_FLAGS_INPUT_POWER7,
315 /* PowerPC 401 bus */
317 /* Freescale RCPU bus */
318 PPC_FLAGS_INPUT_RCPU,
321 #define PPC_INPUT(env) (env->bus_model)
323 /*****************************************************************************/
324 typedef struct opc_handler_t opc_handler_t;
326 /*****************************************************************************/
327 /* Types used to describe some PowerPC registers */
328 typedef struct CPUPPCState CPUPPCState;
329 typedef struct DisasContext DisasContext;
330 typedef struct ppc_tb_t ppc_tb_t;
331 typedef struct ppc_spr_t ppc_spr_t;
332 typedef struct ppc_dcr_t ppc_dcr_t;
333 typedef union ppc_avr_t ppc_avr_t;
334 typedef union ppc_tlb_t ppc_tlb_t;
336 /* SPR access micro-ops generations callbacks */
338 void (*uea_read)(DisasContext *ctx, int gpr_num, int spr_num);
339 void (*uea_write)(DisasContext *ctx, int spr_num, int gpr_num);
340 #if !defined(CONFIG_USER_ONLY)
341 void (*oea_read)(DisasContext *ctx, int gpr_num, int spr_num);
342 void (*oea_write)(DisasContext *ctx, int spr_num, int gpr_num);
343 void (*hea_read)(DisasContext *ctx, int gpr_num, int spr_num);
344 void (*hea_write)(DisasContext *ctx, int spr_num, int gpr_num);
347 target_ulong default_value;
349 /* We (ab)use the fact that all the SPRs will have ids for the
350 * ONE_REG interface will have KVM_REG_PPC to use 0 as meaning,
356 /* Altivec registers (128 bits) */
372 #if !defined(CONFIG_USER_ONLY)
373 /* Software TLB cache */
374 typedef struct ppc6xx_tlb_t ppc6xx_tlb_t;
375 struct ppc6xx_tlb_t {
381 typedef struct ppcemb_tlb_t ppcemb_tlb_t;
382 struct ppcemb_tlb_t {
388 uint32_t attr; /* Storage attributes */
391 typedef struct ppcmas_tlb_t {
404 /* possible TLB variants */
411 #define SDR_32_HTABORG 0xFFFF0000UL
412 #define SDR_32_HTABMASK 0x000001FFUL
414 #if defined(TARGET_PPC64)
415 #define SDR_64_HTABORG 0xFFFFFFFFFFFC0000ULL
416 #define SDR_64_HTABSIZE 0x000000000000001FULL
417 #endif /* defined(TARGET_PPC64 */
419 typedef struct ppc_slb_t ppc_slb_t;
423 const struct ppc_one_seg_page_size *sps;
426 #define MAX_SLB_ENTRIES 64
427 #define SEGMENT_SHIFT_256M 28
428 #define SEGMENT_MASK_256M (~((1ULL << SEGMENT_SHIFT_256M) - 1))
430 #define SEGMENT_SHIFT_1T 40
431 #define SEGMENT_MASK_1T (~((1ULL << SEGMENT_SHIFT_1T) - 1))
434 /*****************************************************************************/
435 /* Machine state register bits definition */
436 #define MSR_SF 63 /* Sixty-four-bit mode hflags */
437 #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
438 #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
439 #define MSR_SHV 60 /* hypervisor state hflags */
440 #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
442 #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
443 #define MSR_CM 31 /* Computation mode for BookE hflags */
444 #define MSR_ICM 30 /* Interrupt computation mode for BookE */
445 #define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
446 #define MSR_GS 28 /* guest state for BookE */
447 #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
448 #define MSR_VR 25 /* altivec available x hflags */
449 #define MSR_SPE 25 /* SPE enable for BookE x hflags */
450 #define MSR_AP 23 /* Access privilege state on 602 hflags */
451 #define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
452 #define MSR_SA 22 /* Supervisor access mode on 602 hflags */
453 #define MSR_KEY 19 /* key bit on 603e */
454 #define MSR_POW 18 /* Power management */
455 #define MSR_TGPR 17 /* TGPR usage on 602/603 x */
456 #define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
457 #define MSR_ILE 16 /* Interrupt little-endian mode */
458 #define MSR_EE 15 /* External interrupt enable */
459 #define MSR_PR 14 /* Problem state hflags */
460 #define MSR_FP 13 /* Floating point available hflags */
461 #define MSR_ME 12 /* Machine check interrupt enable */
462 #define MSR_FE0 11 /* Floating point exception mode 0 hflags */
463 #define MSR_SE 10 /* Single-step trace enable x hflags */
464 #define MSR_DWE 10 /* Debug wait enable on 405 x */
465 #define MSR_UBLE 10 /* User BTB lock enable on e500 x */
466 #define MSR_BE 9 /* Branch trace enable x hflags */
467 #define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
468 #define MSR_FE1 8 /* Floating point exception mode 1 hflags */
469 #define MSR_AL 7 /* AL bit on POWER */
470 #define MSR_EP 6 /* Exception prefix on 601 */
471 #define MSR_IR 5 /* Instruction relocate */
472 #define MSR_DR 4 /* Data relocate */
473 #define MSR_PE 3 /* Protection enable on 403 */
474 #define MSR_PX 2 /* Protection exclusive on 403 x */
475 #define MSR_PMM 2 /* Performance monitor mark on POWER x */
476 #define MSR_RI 1 /* Recoverable interrupt 1 */
477 #define MSR_LE 0 /* Little-endian mode 1 hflags */
480 #define LPCR_VPM0 (1ull << (63 - 0))
481 #define LPCR_VPM1 (1ull << (63 - 1))
482 #define LPCR_ISL (1ull << (63 - 2))
483 #define LPCR_KBV (1ull << (63 - 3))
484 #define LPCR_ILE (1ull << (63 - 38))
485 #define LPCR_MER (1ull << (63 - 52))
486 #define LPCR_LPES0 (1ull << (63 - 60))
487 #define LPCR_LPES1 (1ull << (63 - 61))
488 #define LPCR_AIL_SHIFT (63 - 40) /* Alternate interrupt location */
489 #define LPCR_AIL (3ull << LPCR_AIL_SHIFT)
491 #define msr_sf ((env->msr >> MSR_SF) & 1)
492 #define msr_isf ((env->msr >> MSR_ISF) & 1)
493 #define msr_shv ((env->msr >> MSR_SHV) & 1)
494 #define msr_cm ((env->msr >> MSR_CM) & 1)
495 #define msr_icm ((env->msr >> MSR_ICM) & 1)
496 #define msr_thv ((env->msr >> MSR_THV) & 1)
497 #define msr_gs ((env->msr >> MSR_GS) & 1)
498 #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
499 #define msr_vr ((env->msr >> MSR_VR) & 1)
500 #define msr_spe ((env->msr >> MSR_SPE) & 1)
501 #define msr_ap ((env->msr >> MSR_AP) & 1)
502 #define msr_vsx ((env->msr >> MSR_VSX) & 1)
503 #define msr_sa ((env->msr >> MSR_SA) & 1)
504 #define msr_key ((env->msr >> MSR_KEY) & 1)
505 #define msr_pow ((env->msr >> MSR_POW) & 1)
506 #define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
507 #define msr_ce ((env->msr >> MSR_CE) & 1)
508 #define msr_ile ((env->msr >> MSR_ILE) & 1)
509 #define msr_ee ((env->msr >> MSR_EE) & 1)
510 #define msr_pr ((env->msr >> MSR_PR) & 1)
511 #define msr_fp ((env->msr >> MSR_FP) & 1)
512 #define msr_me ((env->msr >> MSR_ME) & 1)
513 #define msr_fe0 ((env->msr >> MSR_FE0) & 1)
514 #define msr_se ((env->msr >> MSR_SE) & 1)
515 #define msr_dwe ((env->msr >> MSR_DWE) & 1)
516 #define msr_uble ((env->msr >> MSR_UBLE) & 1)
517 #define msr_be ((env->msr >> MSR_BE) & 1)
518 #define msr_de ((env->msr >> MSR_DE) & 1)
519 #define msr_fe1 ((env->msr >> MSR_FE1) & 1)
520 #define msr_al ((env->msr >> MSR_AL) & 1)
521 #define msr_ep ((env->msr >> MSR_EP) & 1)
522 #define msr_ir ((env->msr >> MSR_IR) & 1)
523 #define msr_dr ((env->msr >> MSR_DR) & 1)
524 #define msr_pe ((env->msr >> MSR_PE) & 1)
525 #define msr_px ((env->msr >> MSR_PX) & 1)
526 #define msr_pmm ((env->msr >> MSR_PMM) & 1)
527 #define msr_ri ((env->msr >> MSR_RI) & 1)
528 #define msr_le ((env->msr >> MSR_LE) & 1)
529 #define msr_ts ((env->msr >> MSR_TS1) & 3)
530 #define msr_tm ((env->msr >> MSR_TM) & 1)
532 /* Hypervisor bit is more specific */
533 #if defined(TARGET_PPC64)
534 #define MSR_HVB (1ULL << MSR_SHV)
535 #define msr_hv msr_shv
537 #if defined(PPC_EMULATE_32BITS_HYPV)
538 #define MSR_HVB (1ULL << MSR_THV)
539 #define msr_hv msr_thv
541 #define MSR_HVB (0ULL)
546 /* Facility Status and Control (FSCR) bits */
547 #define FSCR_EBB (63 - 56) /* Event-Based Branch Facility */
548 #define FSCR_TAR (63 - 55) /* Target Address Register */
549 /* Interrupt cause mask and position in FSCR. HFSCR has the same format */
550 #define FSCR_IC_MASK (0xFFULL)
551 #define FSCR_IC_POS (63 - 7)
552 #define FSCR_IC_DSCR_SPR3 2
553 #define FSCR_IC_PMU 3
554 #define FSCR_IC_BHRB 4
556 #define FSCR_IC_EBB 7
557 #define FSCR_IC_TAR 8
559 /* Exception state register bits definition */
560 #define ESR_PIL (1 << (63 - 36)) /* Illegal Instruction */
561 #define ESR_PPR (1 << (63 - 37)) /* Privileged Instruction */
562 #define ESR_PTR (1 << (63 - 38)) /* Trap */
563 #define ESR_FP (1 << (63 - 39)) /* Floating-Point Operation */
564 #define ESR_ST (1 << (63 - 40)) /* Store Operation */
565 #define ESR_AP (1 << (63 - 44)) /* Auxiliary Processor Operation */
566 #define ESR_PUO (1 << (63 - 45)) /* Unimplemented Operation */
567 #define ESR_BO (1 << (63 - 46)) /* Byte Ordering */
568 #define ESR_PIE (1 << (63 - 47)) /* Imprecise exception */
569 #define ESR_DATA (1 << (63 - 53)) /* Data Access (Embedded page table) */
570 #define ESR_TLBI (1 << (63 - 54)) /* TLB Ineligible (Embedded page table) */
571 #define ESR_PT (1 << (63 - 55)) /* Page Table (Embedded page table) */
572 #define ESR_SPV (1 << (63 - 56)) /* SPE/VMX operation */
573 #define ESR_EPID (1 << (63 - 57)) /* External Process ID operation */
574 #define ESR_VLEMI (1 << (63 - 58)) /* VLE operation */
575 #define ESR_MIF (1 << (63 - 62)) /* Misaligned instruction (VLE) */
577 /* Transaction EXception And Summary Register bits */
578 #define TEXASR_FAILURE_PERSISTENT (63 - 7)
579 #define TEXASR_DISALLOWED (63 - 8)
580 #define TEXASR_NESTING_OVERFLOW (63 - 9)
581 #define TEXASR_FOOTPRINT_OVERFLOW (63 - 10)
582 #define TEXASR_SELF_INDUCED_CONFLICT (63 - 11)
583 #define TEXASR_NON_TRANSACTIONAL_CONFLICT (63 - 12)
584 #define TEXASR_TRANSACTION_CONFLICT (63 - 13)
585 #define TEXASR_TRANSLATION_INVALIDATION_CONFLICT (63 - 14)
586 #define TEXASR_IMPLEMENTATION_SPECIFIC (63 - 15)
587 #define TEXASR_INSTRUCTION_FETCH_CONFLICT (63 - 16)
588 #define TEXASR_ABORT (63 - 31)
589 #define TEXASR_SUSPENDED (63 - 32)
590 #define TEXASR_PRIVILEGE_HV (63 - 34)
591 #define TEXASR_PRIVILEGE_PR (63 - 35)
592 #define TEXASR_FAILURE_SUMMARY (63 - 36)
593 #define TEXASR_TFIAR_EXACT (63 - 37)
594 #define TEXASR_ROT (63 - 38)
595 #define TEXASR_TRANSACTION_LEVEL (63 - 52) /* 12 bits */
598 POWERPC_FLAG_NONE = 0x00000000,
599 /* Flag for MSR bit 25 signification (VRE/SPE) */
600 POWERPC_FLAG_SPE = 0x00000001,
601 POWERPC_FLAG_VRE = 0x00000002,
602 /* Flag for MSR bit 17 signification (TGPR/CE) */
603 POWERPC_FLAG_TGPR = 0x00000004,
604 POWERPC_FLAG_CE = 0x00000008,
605 /* Flag for MSR bit 10 signification (SE/DWE/UBLE) */
606 POWERPC_FLAG_SE = 0x00000010,
607 POWERPC_FLAG_DWE = 0x00000020,
608 POWERPC_FLAG_UBLE = 0x00000040,
609 /* Flag for MSR bit 9 signification (BE/DE) */
610 POWERPC_FLAG_BE = 0x00000080,
611 POWERPC_FLAG_DE = 0x00000100,
612 /* Flag for MSR bit 2 signification (PX/PMM) */
613 POWERPC_FLAG_PX = 0x00000200,
614 POWERPC_FLAG_PMM = 0x00000400,
615 /* Flag for special features */
616 /* Decrementer clock: RTC clock (POWER, 601) or bus clock */
617 POWERPC_FLAG_RTC_CLK = 0x00010000,
618 POWERPC_FLAG_BUS_CLK = 0x00020000,
620 POWERPC_FLAG_CFAR = 0x00040000,
622 POWERPC_FLAG_VSX = 0x00080000,
623 /* Has Transaction Memory (ISA 2.07) */
624 POWERPC_FLAG_TM = 0x00100000,
627 /*****************************************************************************/
628 /* Floating point status and control register */
629 #define FPSCR_FX 31 /* Floating-point exception summary */
630 #define FPSCR_FEX 30 /* Floating-point enabled exception summary */
631 #define FPSCR_VX 29 /* Floating-point invalid operation exception summ. */
632 #define FPSCR_OX 28 /* Floating-point overflow exception */
633 #define FPSCR_UX 27 /* Floating-point underflow exception */
634 #define FPSCR_ZX 26 /* Floating-point zero divide exception */
635 #define FPSCR_XX 25 /* Floating-point inexact exception */
636 #define FPSCR_VXSNAN 24 /* Floating-point invalid operation exception (sNan) */
637 #define FPSCR_VXISI 23 /* Floating-point invalid operation exception (inf) */
638 #define FPSCR_VXIDI 22 /* Floating-point invalid operation exception (inf) */
639 #define FPSCR_VXZDZ 21 /* Floating-point invalid operation exception (zero) */
640 #define FPSCR_VXIMZ 20 /* Floating-point invalid operation exception (inf) */
641 #define FPSCR_VXVC 19 /* Floating-point invalid operation exception (comp) */
642 #define FPSCR_FR 18 /* Floating-point fraction rounded */
643 #define FPSCR_FI 17 /* Floating-point fraction inexact */
644 #define FPSCR_C 16 /* Floating-point result class descriptor */
645 #define FPSCR_FL 15 /* Floating-point less than or negative */
646 #define FPSCR_FG 14 /* Floating-point greater than or negative */
647 #define FPSCR_FE 13 /* Floating-point equal or zero */
648 #define FPSCR_FU 12 /* Floating-point unordered or NaN */
649 #define FPSCR_FPCC 12 /* Floating-point condition code */
650 #define FPSCR_FPRF 12 /* Floating-point result flags */
651 #define FPSCR_VXSOFT 10 /* Floating-point invalid operation exception (soft) */
652 #define FPSCR_VXSQRT 9 /* Floating-point invalid operation exception (sqrt) */
653 #define FPSCR_VXCVI 8 /* Floating-point invalid operation exception (int) */
654 #define FPSCR_VE 7 /* Floating-point invalid operation exception enable */
655 #define FPSCR_OE 6 /* Floating-point overflow exception enable */
656 #define FPSCR_UE 5 /* Floating-point undeflow exception enable */
657 #define FPSCR_ZE 4 /* Floating-point zero divide exception enable */
658 #define FPSCR_XE 3 /* Floating-point inexact exception enable */
659 #define FPSCR_NI 2 /* Floating-point non-IEEE mode */
661 #define FPSCR_RN 0 /* Floating-point rounding control */
662 #define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
663 #define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
664 #define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
665 #define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
666 #define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
667 #define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
668 #define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
669 #define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
670 #define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
671 #define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
672 #define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
673 #define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
674 #define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
675 #define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
676 #define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
677 #define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
678 #define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
679 #define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
680 #define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
681 #define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
682 #define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
683 #define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
684 #define fpscr_rn (((env->fpscr) >> FPSCR_RN) & 0x3)
685 /* Invalid operation exception summary */
686 #define fpscr_ix ((env->fpscr) & ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
687 (1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
688 (1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
689 (1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
691 /* exception summary */
692 #define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
693 /* enabled exception summary */
694 #define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
697 #define FP_FX (1ull << FPSCR_FX)
698 #define FP_FEX (1ull << FPSCR_FEX)
699 #define FP_VX (1ull << FPSCR_VX)
700 #define FP_OX (1ull << FPSCR_OX)
701 #define FP_UX (1ull << FPSCR_UX)
702 #define FP_ZX (1ull << FPSCR_ZX)
703 #define FP_XX (1ull << FPSCR_XX)
704 #define FP_VXSNAN (1ull << FPSCR_VXSNAN)
705 #define FP_VXISI (1ull << FPSCR_VXISI)
706 #define FP_VXIDI (1ull << FPSCR_VXIDI)
707 #define FP_VXZDZ (1ull << FPSCR_VXZDZ)
708 #define FP_VXIMZ (1ull << FPSCR_VXIMZ)
709 #define FP_VXVC (1ull << FPSCR_VXVC)
710 #define FP_FR (1ull << FSPCR_FR)
711 #define FP_FI (1ull << FPSCR_FI)
712 #define FP_C (1ull << FPSCR_C)
713 #define FP_FL (1ull << FPSCR_FL)
714 #define FP_FG (1ull << FPSCR_FG)
715 #define FP_FE (1ull << FPSCR_FE)
716 #define FP_FU (1ull << FPSCR_FU)
717 #define FP_FPCC (FP_FL | FP_FG | FP_FE | FP_FU)
718 #define FP_FPRF (FP_C | FP_FL | FP_FG | FP_FE | FP_FU)
719 #define FP_VXSOFT (1ull << FPSCR_VXSOFT)
720 #define FP_VXSQRT (1ull << FPSCR_VXSQRT)
721 #define FP_VXCVI (1ull << FPSCR_VXCVI)
722 #define FP_VE (1ull << FPSCR_VE)
723 #define FP_OE (1ull << FPSCR_OE)
724 #define FP_UE (1ull << FPSCR_UE)
725 #define FP_ZE (1ull << FPSCR_ZE)
726 #define FP_XE (1ull << FPSCR_XE)
727 #define FP_NI (1ull << FPSCR_NI)
728 #define FP_RN1 (1ull << FPSCR_RN1)
729 #define FP_RN (1ull << FPSCR_RN)
731 /* the exception bits which can be cleared by mcrfs - includes FX */
732 #define FP_EX_CLEAR_BITS (FP_FX | FP_OX | FP_UX | FP_ZX | \
733 FP_XX | FP_VXSNAN | FP_VXISI | FP_VXIDI | \
734 FP_VXZDZ | FP_VXIMZ | FP_VXVC | FP_VXSOFT | \
735 FP_VXSQRT | FP_VXCVI)
737 /*****************************************************************************/
738 /* Vector status and control register */
739 #define VSCR_NJ 16 /* Vector non-java */
740 #define VSCR_SAT 0 /* Vector saturation */
741 #define vscr_nj (((env->vscr) >> VSCR_NJ) & 0x1)
742 #define vscr_sat (((env->vscr) >> VSCR_SAT) & 0x1)
744 /*****************************************************************************/
745 /* BookE e500 MMU registers */
747 #define MAS0_NV_SHIFT 0
748 #define MAS0_NV_MASK (0xfff << MAS0_NV_SHIFT)
750 #define MAS0_WQ_SHIFT 12
751 #define MAS0_WQ_MASK (3 << MAS0_WQ_SHIFT)
752 /* Write TLB entry regardless of reservation */
753 #define MAS0_WQ_ALWAYS (0 << MAS0_WQ_SHIFT)
754 /* Write TLB entry only already in use */
755 #define MAS0_WQ_COND (1 << MAS0_WQ_SHIFT)
756 /* Clear TLB entry */
757 #define MAS0_WQ_CLR_RSRV (2 << MAS0_WQ_SHIFT)
759 #define MAS0_HES_SHIFT 14
760 #define MAS0_HES (1 << MAS0_HES_SHIFT)
762 #define MAS0_ESEL_SHIFT 16
763 #define MAS0_ESEL_MASK (0xfff << MAS0_ESEL_SHIFT)
765 #define MAS0_TLBSEL_SHIFT 28
766 #define MAS0_TLBSEL_MASK (3 << MAS0_TLBSEL_SHIFT)
767 #define MAS0_TLBSEL_TLB0 (0 << MAS0_TLBSEL_SHIFT)
768 #define MAS0_TLBSEL_TLB1 (1 << MAS0_TLBSEL_SHIFT)
769 #define MAS0_TLBSEL_TLB2 (2 << MAS0_TLBSEL_SHIFT)
770 #define MAS0_TLBSEL_TLB3 (3 << MAS0_TLBSEL_SHIFT)
772 #define MAS0_ATSEL_SHIFT 31
773 #define MAS0_ATSEL (1 << MAS0_ATSEL_SHIFT)
774 #define MAS0_ATSEL_TLB 0
775 #define MAS0_ATSEL_LRAT MAS0_ATSEL
777 #define MAS1_TSIZE_SHIFT 7
778 #define MAS1_TSIZE_MASK (0x1f << MAS1_TSIZE_SHIFT)
780 #define MAS1_TS_SHIFT 12
781 #define MAS1_TS (1 << MAS1_TS_SHIFT)
783 #define MAS1_IND_SHIFT 13
784 #define MAS1_IND (1 << MAS1_IND_SHIFT)
786 #define MAS1_TID_SHIFT 16
787 #define MAS1_TID_MASK (0x3fff << MAS1_TID_SHIFT)
789 #define MAS1_IPROT_SHIFT 30
790 #define MAS1_IPROT (1 << MAS1_IPROT_SHIFT)
792 #define MAS1_VALID_SHIFT 31
793 #define MAS1_VALID 0x80000000
795 #define MAS2_EPN_SHIFT 12
796 #define MAS2_EPN_MASK (~0ULL << MAS2_EPN_SHIFT)
798 #define MAS2_ACM_SHIFT 6
799 #define MAS2_ACM (1 << MAS2_ACM_SHIFT)
801 #define MAS2_VLE_SHIFT 5
802 #define MAS2_VLE (1 << MAS2_VLE_SHIFT)
804 #define MAS2_W_SHIFT 4
805 #define MAS2_W (1 << MAS2_W_SHIFT)
807 #define MAS2_I_SHIFT 3
808 #define MAS2_I (1 << MAS2_I_SHIFT)
810 #define MAS2_M_SHIFT 2
811 #define MAS2_M (1 << MAS2_M_SHIFT)
813 #define MAS2_G_SHIFT 1
814 #define MAS2_G (1 << MAS2_G_SHIFT)
816 #define MAS2_E_SHIFT 0
817 #define MAS2_E (1 << MAS2_E_SHIFT)
819 #define MAS3_RPN_SHIFT 12
820 #define MAS3_RPN_MASK (0xfffff << MAS3_RPN_SHIFT)
822 #define MAS3_U0 0x00000200
823 #define MAS3_U1 0x00000100
824 #define MAS3_U2 0x00000080
825 #define MAS3_U3 0x00000040
826 #define MAS3_UX 0x00000020
827 #define MAS3_SX 0x00000010
828 #define MAS3_UW 0x00000008
829 #define MAS3_SW 0x00000004
830 #define MAS3_UR 0x00000002
831 #define MAS3_SR 0x00000001
832 #define MAS3_SPSIZE_SHIFT 1
833 #define MAS3_SPSIZE_MASK (0x3e << MAS3_SPSIZE_SHIFT)
835 #define MAS4_TLBSELD_SHIFT MAS0_TLBSEL_SHIFT
836 #define MAS4_TLBSELD_MASK MAS0_TLBSEL_MASK
837 #define MAS4_TIDSELD_MASK 0x00030000
838 #define MAS4_TIDSELD_PID0 0x00000000
839 #define MAS4_TIDSELD_PID1 0x00010000
840 #define MAS4_TIDSELD_PID2 0x00020000
841 #define MAS4_TIDSELD_PIDZ 0x00030000
842 #define MAS4_INDD 0x00008000 /* Default IND */
843 #define MAS4_TSIZED_SHIFT MAS1_TSIZE_SHIFT
844 #define MAS4_TSIZED_MASK MAS1_TSIZE_MASK
845 #define MAS4_ACMD 0x00000040
846 #define MAS4_VLED 0x00000020
847 #define MAS4_WD 0x00000010
848 #define MAS4_ID 0x00000008
849 #define MAS4_MD 0x00000004
850 #define MAS4_GD 0x00000002
851 #define MAS4_ED 0x00000001
852 #define MAS4_WIMGED_MASK 0x0000001f /* Default WIMGE */
853 #define MAS4_WIMGED_SHIFT 0
855 #define MAS5_SGS 0x80000000
856 #define MAS5_SLPID_MASK 0x00000fff
858 #define MAS6_SPID0 0x3fff0000
859 #define MAS6_SPID1 0x00007ffe
860 #define MAS6_ISIZE(x) MAS1_TSIZE(x)
861 #define MAS6_SAS 0x00000001
862 #define MAS6_SPID MAS6_SPID0
863 #define MAS6_SIND 0x00000002 /* Indirect page */
864 #define MAS6_SIND_SHIFT 1
865 #define MAS6_SPID_MASK 0x3fff0000
866 #define MAS6_SPID_SHIFT 16
867 #define MAS6_ISIZE_MASK 0x00000f80
868 #define MAS6_ISIZE_SHIFT 7
870 #define MAS7_RPN 0xffffffff
872 #define MAS8_TGS 0x80000000
873 #define MAS8_VF 0x40000000
874 #define MAS8_TLBPID 0x00000fff
876 /* Bit definitions for MMUCFG */
877 #define MMUCFG_MAVN 0x00000003 /* MMU Architecture Version Number */
878 #define MMUCFG_MAVN_V1 0x00000000 /* v1.0 */
879 #define MMUCFG_MAVN_V2 0x00000001 /* v2.0 */
880 #define MMUCFG_NTLBS 0x0000000c /* Number of TLBs */
881 #define MMUCFG_PIDSIZE 0x000007c0 /* PID Reg Size */
882 #define MMUCFG_TWC 0x00008000 /* TLB Write Conditional (v2.0) */
883 #define MMUCFG_LRAT 0x00010000 /* LRAT Supported (v2.0) */
884 #define MMUCFG_RASIZE 0x00fe0000 /* Real Addr Size */
885 #define MMUCFG_LPIDSIZE 0x0f000000 /* LPID Reg Size */
887 /* Bit definitions for MMUCSR0 */
888 #define MMUCSR0_TLB1FI 0x00000002 /* TLB1 Flash invalidate */
889 #define MMUCSR0_TLB0FI 0x00000004 /* TLB0 Flash invalidate */
890 #define MMUCSR0_TLB2FI 0x00000040 /* TLB2 Flash invalidate */
891 #define MMUCSR0_TLB3FI 0x00000020 /* TLB3 Flash invalidate */
892 #define MMUCSR0_TLBFI (MMUCSR0_TLB0FI | MMUCSR0_TLB1FI | \
893 MMUCSR0_TLB2FI | MMUCSR0_TLB3FI)
894 #define MMUCSR0_TLB0PS 0x00000780 /* TLB0 Page Size */
895 #define MMUCSR0_TLB1PS 0x00007800 /* TLB1 Page Size */
896 #define MMUCSR0_TLB2PS 0x00078000 /* TLB2 Page Size */
897 #define MMUCSR0_TLB3PS 0x00780000 /* TLB3 Page Size */
899 /* TLBnCFG encoding */
900 #define TLBnCFG_N_ENTRY 0x00000fff /* number of entries */
901 #define TLBnCFG_HES 0x00002000 /* HW select supported */
902 #define TLBnCFG_AVAIL 0x00004000 /* variable page size */
903 #define TLBnCFG_IPROT 0x00008000 /* IPROT supported */
904 #define TLBnCFG_GTWE 0x00010000 /* Guest can write */
905 #define TLBnCFG_IND 0x00020000 /* IND entries supported */
906 #define TLBnCFG_PT 0x00040000 /* Can load from page table */
907 #define TLBnCFG_MINSIZE 0x00f00000 /* Minimum Page Size (v1.0) */
908 #define TLBnCFG_MINSIZE_SHIFT 20
909 #define TLBnCFG_MAXSIZE 0x000f0000 /* Maximum Page Size (v1.0) */
910 #define TLBnCFG_MAXSIZE_SHIFT 16
911 #define TLBnCFG_ASSOC 0xff000000 /* Associativity */
912 #define TLBnCFG_ASSOC_SHIFT 24
914 /* TLBnPS encoding */
915 #define TLBnPS_4K 0x00000004
916 #define TLBnPS_8K 0x00000008
917 #define TLBnPS_16K 0x00000010
918 #define TLBnPS_32K 0x00000020
919 #define TLBnPS_64K 0x00000040
920 #define TLBnPS_128K 0x00000080
921 #define TLBnPS_256K 0x00000100
922 #define TLBnPS_512K 0x00000200
923 #define TLBnPS_1M 0x00000400
924 #define TLBnPS_2M 0x00000800
925 #define TLBnPS_4M 0x00001000
926 #define TLBnPS_8M 0x00002000
927 #define TLBnPS_16M 0x00004000
928 #define TLBnPS_32M 0x00008000
929 #define TLBnPS_64M 0x00010000
930 #define TLBnPS_128M 0x00020000
931 #define TLBnPS_256M 0x00040000
932 #define TLBnPS_512M 0x00080000
933 #define TLBnPS_1G 0x00100000
934 #define TLBnPS_2G 0x00200000
935 #define TLBnPS_4G 0x00400000
936 #define TLBnPS_8G 0x00800000
937 #define TLBnPS_16G 0x01000000
938 #define TLBnPS_32G 0x02000000
939 #define TLBnPS_64G 0x04000000
940 #define TLBnPS_128G 0x08000000
941 #define TLBnPS_256G 0x10000000
943 /* tlbilx action encoding */
944 #define TLBILX_T_ALL 0
945 #define TLBILX_T_TID 1
946 #define TLBILX_T_FULLMATCH 3
947 #define TLBILX_T_CLASS0 4
948 #define TLBILX_T_CLASS1 5
949 #define TLBILX_T_CLASS2 6
950 #define TLBILX_T_CLASS3 7
952 /* BookE 2.06 helper defines */
954 #define BOOKE206_FLUSH_TLB0 (1 << 0)
955 #define BOOKE206_FLUSH_TLB1 (1 << 1)
956 #define BOOKE206_FLUSH_TLB2 (1 << 2)
957 #define BOOKE206_FLUSH_TLB3 (1 << 3)
959 /* number of possible TLBs */
960 #define BOOKE206_MAX_TLBN 4
962 /*****************************************************************************/
963 /* Embedded.Processor Control */
965 #define DBELL_TYPE_SHIFT 27
966 #define DBELL_TYPE_MASK (0x1f << DBELL_TYPE_SHIFT)
967 #define DBELL_TYPE_DBELL (0x00 << DBELL_TYPE_SHIFT)
968 #define DBELL_TYPE_DBELL_CRIT (0x01 << DBELL_TYPE_SHIFT)
969 #define DBELL_TYPE_G_DBELL (0x02 << DBELL_TYPE_SHIFT)
970 #define DBELL_TYPE_G_DBELL_CRIT (0x03 << DBELL_TYPE_SHIFT)
971 #define DBELL_TYPE_G_DBELL_MC (0x04 << DBELL_TYPE_SHIFT)
973 #define DBELL_BRDCAST (1 << 26)
974 #define DBELL_LPIDTAG_SHIFT 14
975 #define DBELL_LPIDTAG_MASK (0xfff << DBELL_LPIDTAG_SHIFT)
976 #define DBELL_PIRTAG_MASK 0x3fff
978 /*****************************************************************************/
979 /* Segment page size information, used by recent hash MMUs
980 * The format of this structure mirrors kvm_ppc_smmu_info
983 #define PPC_PAGE_SIZES_MAX_SZ 8
985 struct ppc_one_page_size {
986 uint32_t page_shift; /* Page shift (or 0) */
987 uint32_t pte_enc; /* Encoding in the HPTE (>>12) */
990 struct ppc_one_seg_page_size {
991 uint32_t page_shift; /* Base page shift of segment (or 0) */
992 uint32_t slb_enc; /* SLB encoding for BookS */
993 struct ppc_one_page_size enc[PPC_PAGE_SIZES_MAX_SZ];
996 struct ppc_segment_page_sizes {
997 struct ppc_one_seg_page_size sps[PPC_PAGE_SIZES_MAX_SZ];
1001 /*****************************************************************************/
1002 /* The whole PowerPC CPU context */
1003 #define NB_MMU_MODES 3
1005 #define PPC_CPU_OPCODES_LEN 0x40
1006 #define PPC_CPU_INDIRECT_OPCODES_LEN 0x20
1008 struct CPUPPCState {
1009 /* First are the most commonly used resources
1010 * during translated code execution
1012 /* general purpose registers */
1013 target_ulong gpr[32];
1014 /* Storage for GPR MSB, used by the SPE extension */
1015 target_ulong gprh[32];
1020 /* condition register */
1022 #if defined(TARGET_PPC64)
1026 /* XER (with SO, OV, CA split out) */
1031 /* Reservation address */
1032 target_ulong reserve_addr;
1033 /* Reservation value */
1034 target_ulong reserve_val;
1035 target_ulong reserve_val2;
1036 /* Reservation store address */
1037 target_ulong reserve_ea;
1038 /* Reserved store source register and size */
1039 target_ulong reserve_info;
1041 /* Those ones are used in supervisor mode only */
1042 /* machine state register */
1044 /* temporary general purpose registers */
1045 target_ulong tgpr[4]; /* Used to speed-up TLB assist handlers */
1047 /* Floating point execution context */
1048 float_status fp_status;
1049 /* floating point registers */
1051 /* floating point status and control register */
1054 /* Next instruction pointer */
1057 int access_type; /* when a memory exception occurs, the access
1058 type is stored here */
1062 /* MMU context - only relevant for full system emulation */
1063 #if !defined(CONFIG_USER_ONLY)
1064 #if defined(TARGET_PPC64)
1065 /* PowerPC 64 SLB area */
1066 ppc_slb_t slb[MAX_SLB_ENTRIES];
1069 /* segment registers */
1071 /* mask used to normalize hash value to PTEG index */
1073 target_ulong sr[32];
1074 /* externally stored hash table */
1075 uint8_t *external_htab;
1078 target_ulong DBAT[2][8];
1079 target_ulong IBAT[2][8];
1080 /* PowerPC TLB registers (for 4xx, e500 and 60x software driven TLBs) */
1081 int32_t nb_tlb; /* Total number of TLB */
1082 int tlb_per_way; /* Speed-up helper: used to avoid divisions at run time */
1083 int nb_ways; /* Number of ways in the TLB set */
1084 int last_way; /* Last used way used to allocate TLB in a LRU way */
1085 int id_tlbs; /* If 1, MMU has separated TLBs for instructions & data */
1086 int nb_pids; /* Number of available PID registers */
1087 int tlb_type; /* Type of TLB we're dealing with */
1088 ppc_tlb_t tlb; /* TLB is optional. Allocate them only if needed */
1089 /* 403 dedicated access protection registers */
1091 bool tlb_dirty; /* Set to non-zero when modifying TLB */
1092 bool kvm_sw_tlb; /* non-zero if KVM SW TLB API is active */
1095 /* Other registers */
1096 /* Special purpose registers */
1097 target_ulong spr[1024];
1098 ppc_spr_t spr_cb[1024];
1099 /* Altivec registers */
1107 /* SPE and Altivec can share a status since they will never be used
1109 float_status vec_status;
1111 /* Internal devices resources */
1112 /* Time base and decrementer */
1114 /* Device control registers */
1117 int dcache_line_size;
1118 int icache_line_size;
1120 /* Those resources are used during exception processing */
1121 /* CPU model definition */
1122 target_ulong msr_mask;
1123 powerpc_mmu_t mmu_model;
1124 powerpc_excp_t excp_model;
1125 powerpc_input_t bus_model;
1128 uint64_t insns_flags;
1129 uint64_t insns_flags2;
1130 #if defined(TARGET_PPC64)
1131 struct ppc_segment_page_sizes sps;
1132 bool ci_large_pages;
1135 #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY)
1137 uint64_t slb_shadow_addr, slb_shadow_size;
1138 uint64_t dtl_addr, dtl_size;
1139 #endif /* TARGET_PPC64 */
1142 uint32_t pending_interrupts;
1143 #if !defined(CONFIG_USER_ONLY)
1144 /* This is the IRQ controller, which is implementation dependent
1145 * and only relevant when emulating a complete machine.
1147 uint32_t irq_input_state;
1149 /* Exception vectors */
1150 target_ulong excp_vectors[POWERPC_EXCP_NB];
1151 target_ulong excp_prefix;
1152 target_ulong ivor_mask;
1153 target_ulong ivpr_mask;
1154 target_ulong hreset_vector;
1156 /* true when the external proxy facility mode is enabled */
1160 /* Those resources are used only during code translation */
1161 /* opcode handlers */
1162 opc_handler_t *opcodes[PPC_CPU_OPCODES_LEN];
1164 /* Those resources are used only in QEMU core */
1165 target_ulong hflags; /* hflags is a MSR & HFLAGS_MASK */
1166 target_ulong hflags_nmsr; /* specific hflags, not coming from MSR */
1167 int mmu_idx; /* precomputed MMU index to speed up mem accesses */
1169 /* Power management */
1170 int (*check_pow)(CPUPPCState *env);
1172 #if !defined(CONFIG_USER_ONLY)
1173 void *load_info; /* Holds boot loading state. */
1178 /* Specifies bit locations of the Time Base used to signal a fixed timer
1179 * exception on a transition from 0 to 1. (watchdog or fixed-interval timer)
1181 * 0 selects the least significant bit.
1182 * 63 selects the most significant bit.
1184 uint8_t fit_period[4];
1185 uint8_t wdt_period[4];
1187 /* Transactional memory state */
1188 target_ulong tm_gpr[32];
1189 ppc_avr_t tm_vsr[64];
1202 #define SET_FIT_PERIOD(a_, b_, c_, d_) \
1204 env->fit_period[0] = (a_); \
1205 env->fit_period[1] = (b_); \
1206 env->fit_period[2] = (c_); \
1207 env->fit_period[3] = (d_); \
1210 #define SET_WDT_PERIOD(a_, b_, c_, d_) \
1212 env->wdt_period[0] = (a_); \
1213 env->wdt_period[1] = (b_); \
1214 env->wdt_period[2] = (c_); \
1215 env->wdt_period[3] = (d_); \
1218 #include "cpu-qom.h"
1220 /*****************************************************************************/
1221 PowerPCCPU *cpu_ppc_init(const char *cpu_model);
1222 void ppc_translate_init(void);
1223 void gen_update_current_nip(void *opaque);
1224 int cpu_ppc_exec (CPUState *s);
1225 /* you can call this signal handler from your SIGBUS and SIGSEGV
1226 signal handlers to inform the virtual CPU of exceptions. non zero
1227 is returned if the signal was handled by the virtual CPU. */
1228 int cpu_ppc_signal_handler (int host_signum, void *pinfo,
1230 #if defined(CONFIG_USER_ONLY)
1231 int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw,
1235 #if !defined(CONFIG_USER_ONLY)
1236 void ppc_store_sdr1 (CPUPPCState *env, target_ulong value);
1237 #endif /* !defined(CONFIG_USER_ONLY) */
1238 void ppc_store_msr (CPUPPCState *env, target_ulong value);
1240 void ppc_cpu_list (FILE *f, fprintf_function cpu_fprintf);
1241 int ppc_get_compat_smt_threads(PowerPCCPU *cpu);
1242 void ppc_set_compat(PowerPCCPU *cpu, uint32_t cpu_version, Error **errp);
1244 /* Time-base and decrementer management */
1245 #ifndef NO_CPU_IO_DEFS
1246 uint64_t cpu_ppc_load_tbl (CPUPPCState *env);
1247 uint32_t cpu_ppc_load_tbu (CPUPPCState *env);
1248 void cpu_ppc_store_tbu (CPUPPCState *env, uint32_t value);
1249 void cpu_ppc_store_tbl (CPUPPCState *env, uint32_t value);
1250 uint64_t cpu_ppc_load_atbl (CPUPPCState *env);
1251 uint32_t cpu_ppc_load_atbu (CPUPPCState *env);
1252 void cpu_ppc_store_atbl (CPUPPCState *env, uint32_t value);
1253 void cpu_ppc_store_atbu (CPUPPCState *env, uint32_t value);
1254 bool ppc_decr_clear_on_delivery(CPUPPCState *env);
1255 uint32_t cpu_ppc_load_decr (CPUPPCState *env);
1256 void cpu_ppc_store_decr (CPUPPCState *env, uint32_t value);
1257 uint32_t cpu_ppc_load_hdecr (CPUPPCState *env);
1258 void cpu_ppc_store_hdecr (CPUPPCState *env, uint32_t value);
1259 uint64_t cpu_ppc_load_purr (CPUPPCState *env);
1260 uint32_t cpu_ppc601_load_rtcl (CPUPPCState *env);
1261 uint32_t cpu_ppc601_load_rtcu (CPUPPCState *env);
1262 #if !defined(CONFIG_USER_ONLY)
1263 void cpu_ppc601_store_rtcl (CPUPPCState *env, uint32_t value);
1264 void cpu_ppc601_store_rtcu (CPUPPCState *env, uint32_t value);
1265 target_ulong load_40x_pit (CPUPPCState *env);
1266 void store_40x_pit (CPUPPCState *env, target_ulong val);
1267 void store_40x_dbcr0 (CPUPPCState *env, uint32_t val);
1268 void store_40x_sler (CPUPPCState *env, uint32_t val);
1269 void store_booke_tcr (CPUPPCState *env, target_ulong val);
1270 void store_booke_tsr (CPUPPCState *env, target_ulong val);
1271 void ppc_tlb_invalidate_all (CPUPPCState *env);
1272 void ppc_tlb_invalidate_one (CPUPPCState *env, target_ulong addr);
1273 void cpu_ppc_set_papr(PowerPCCPU *cpu);
1277 void store_fpscr(CPUPPCState *env, uint64_t arg, uint32_t mask);
1279 static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn)
1283 gprv = env->gpr[gprn];
1284 if (env->flags & POWERPC_FLAG_SPE) {
1285 /* If the CPU implements the SPE extension, we have to get the
1286 * high bits of the GPR from the gprh storage area
1288 gprv &= 0xFFFFFFFFULL;
1289 gprv |= (uint64_t)env->gprh[gprn] << 32;
1295 /* Device control registers */
1296 int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp);
1297 int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val);
1299 #define cpu_init(cpu_model) CPU(cpu_ppc_init(cpu_model))
1301 #define cpu_exec cpu_ppc_exec
1302 #define cpu_signal_handler cpu_ppc_signal_handler
1303 #define cpu_list ppc_cpu_list
1305 /* MMU modes definitions */
1306 #define MMU_MODE0_SUFFIX _user
1307 #define MMU_MODE1_SUFFIX _kernel
1308 #define MMU_MODE2_SUFFIX _hypv
1309 #define MMU_USER_IDX 0
1310 static inline int cpu_mmu_index (CPUPPCState *env, bool ifetch)
1312 return env->mmu_idx;
1315 #include "exec/cpu-all.h"
1317 /*****************************************************************************/
1318 /* CRF definitions */
1323 #define CRF_CH (1 << CRF_LT)
1324 #define CRF_CL (1 << CRF_GT)
1325 #define CRF_CH_OR_CL (1 << CRF_EQ)
1326 #define CRF_CH_AND_CL (1 << CRF_SO)
1328 /* XER definitions */
1334 #define xer_so (env->so)
1335 #define xer_ov (env->ov)
1336 #define xer_ca (env->ca)
1337 #define xer_cmp ((env->xer >> XER_CMP) & 0xFF)
1338 #define xer_bc ((env->xer >> XER_BC) & 0x7F)
1340 /* SPR definitions */
1341 #define SPR_MQ (0x000)
1342 #define SPR_XER (0x001)
1343 #define SPR_601_VRTCU (0x004)
1344 #define SPR_601_VRTCL (0x005)
1345 #define SPR_601_UDECR (0x006)
1346 #define SPR_LR (0x008)
1347 #define SPR_CTR (0x009)
1348 #define SPR_UAMR (0x00C)
1349 #define SPR_DSCR (0x011)
1350 #define SPR_DSISR (0x012)
1351 #define SPR_DAR (0x013) /* DAE for PowerPC 601 */
1352 #define SPR_601_RTCU (0x014)
1353 #define SPR_601_RTCL (0x015)
1354 #define SPR_DECR (0x016)
1355 #define SPR_SDR1 (0x019)
1356 #define SPR_SRR0 (0x01A)
1357 #define SPR_SRR1 (0x01B)
1358 #define SPR_CFAR (0x01C)
1359 #define SPR_AMR (0x01D)
1360 #define SPR_ACOP (0x01F)
1361 #define SPR_BOOKE_PID (0x030)
1362 #define SPR_BOOKS_PID (0x030)
1363 #define SPR_BOOKE_DECAR (0x036)
1364 #define SPR_BOOKE_CSRR0 (0x03A)
1365 #define SPR_BOOKE_CSRR1 (0x03B)
1366 #define SPR_BOOKE_DEAR (0x03D)
1367 #define SPR_IAMR (0x03D)
1368 #define SPR_BOOKE_ESR (0x03E)
1369 #define SPR_BOOKE_IVPR (0x03F)
1370 #define SPR_MPC_EIE (0x050)
1371 #define SPR_MPC_EID (0x051)
1372 #define SPR_MPC_NRI (0x052)
1373 #define SPR_TFHAR (0x080)
1374 #define SPR_TFIAR (0x081)
1375 #define SPR_TEXASR (0x082)
1376 #define SPR_TEXASRU (0x083)
1377 #define SPR_UCTRL (0x088)
1378 #define SPR_MPC_CMPA (0x090)
1379 #define SPR_MPC_CMPB (0x091)
1380 #define SPR_MPC_CMPC (0x092)
1381 #define SPR_MPC_CMPD (0x093)
1382 #define SPR_MPC_ECR (0x094)
1383 #define SPR_MPC_DER (0x095)
1384 #define SPR_MPC_COUNTA (0x096)
1385 #define SPR_MPC_COUNTB (0x097)
1386 #define SPR_CTRL (0x098)
1387 #define SPR_MPC_CMPE (0x098)
1388 #define SPR_MPC_CMPF (0x099)
1389 #define SPR_FSCR (0x099)
1390 #define SPR_MPC_CMPG (0x09A)
1391 #define SPR_MPC_CMPH (0x09B)
1392 #define SPR_MPC_LCTRL1 (0x09C)
1393 #define SPR_MPC_LCTRL2 (0x09D)
1394 #define SPR_UAMOR (0x09D)
1395 #define SPR_MPC_ICTRL (0x09E)
1396 #define SPR_MPC_BAR (0x09F)
1397 #define SPR_PSPB (0x09F)
1398 #define SPR_DAWR (0x0B4)
1399 #define SPR_RPR (0x0BA)
1400 #define SPR_CIABR (0x0BB)
1401 #define SPR_DAWRX (0x0BC)
1402 #define SPR_HFSCR (0x0BE)
1403 #define SPR_VRSAVE (0x100)
1404 #define SPR_USPRG0 (0x100)
1405 #define SPR_USPRG1 (0x101)
1406 #define SPR_USPRG2 (0x102)
1407 #define SPR_USPRG3 (0x103)
1408 #define SPR_USPRG4 (0x104)
1409 #define SPR_USPRG5 (0x105)
1410 #define SPR_USPRG6 (0x106)
1411 #define SPR_USPRG7 (0x107)
1412 #define SPR_VTBL (0x10C)
1413 #define SPR_VTBU (0x10D)
1414 #define SPR_SPRG0 (0x110)
1415 #define SPR_SPRG1 (0x111)
1416 #define SPR_SPRG2 (0x112)
1417 #define SPR_SPRG3 (0x113)
1418 #define SPR_SPRG4 (0x114)
1419 #define SPR_SCOMC (0x114)
1420 #define SPR_SPRG5 (0x115)
1421 #define SPR_SCOMD (0x115)
1422 #define SPR_SPRG6 (0x116)
1423 #define SPR_SPRG7 (0x117)
1424 #define SPR_ASR (0x118)
1425 #define SPR_EAR (0x11A)
1426 #define SPR_TBL (0x11C)
1427 #define SPR_TBU (0x11D)
1428 #define SPR_TBU40 (0x11E)
1429 #define SPR_SVR (0x11E)
1430 #define SPR_BOOKE_PIR (0x11E)
1431 #define SPR_PVR (0x11F)
1432 #define SPR_HSPRG0 (0x130)
1433 #define SPR_BOOKE_DBSR (0x130)
1434 #define SPR_HSPRG1 (0x131)
1435 #define SPR_HDSISR (0x132)
1436 #define SPR_HDAR (0x133)
1437 #define SPR_BOOKE_EPCR (0x133)
1438 #define SPR_SPURR (0x134)
1439 #define SPR_BOOKE_DBCR0 (0x134)
1440 #define SPR_IBCR (0x135)
1441 #define SPR_PURR (0x135)
1442 #define SPR_BOOKE_DBCR1 (0x135)
1443 #define SPR_DBCR (0x136)
1444 #define SPR_HDEC (0x136)
1445 #define SPR_BOOKE_DBCR2 (0x136)
1446 #define SPR_HIOR (0x137)
1447 #define SPR_MBAR (0x137)
1448 #define SPR_RMOR (0x138)
1449 #define SPR_BOOKE_IAC1 (0x138)
1450 #define SPR_HRMOR (0x139)
1451 #define SPR_BOOKE_IAC2 (0x139)
1452 #define SPR_HSRR0 (0x13A)
1453 #define SPR_BOOKE_IAC3 (0x13A)
1454 #define SPR_HSRR1 (0x13B)
1455 #define SPR_BOOKE_IAC4 (0x13B)
1456 #define SPR_BOOKE_DAC1 (0x13C)
1457 #define SPR_MMCRH (0x13C)
1458 #define SPR_DABR2 (0x13D)
1459 #define SPR_BOOKE_DAC2 (0x13D)
1460 #define SPR_TFMR (0x13D)
1461 #define SPR_BOOKE_DVC1 (0x13E)
1462 #define SPR_LPCR (0x13E)
1463 #define SPR_BOOKE_DVC2 (0x13F)
1464 #define SPR_LPIDR (0x13F)
1465 #define SPR_BOOKE_TSR (0x150)
1466 #define SPR_HMER (0x150)
1467 #define SPR_HMEER (0x151)
1468 #define SPR_PCR (0x152)
1469 #define SPR_BOOKE_LPIDR (0x152)
1470 #define SPR_BOOKE_TCR (0x154)
1471 #define SPR_BOOKE_TLB0PS (0x158)
1472 #define SPR_BOOKE_TLB1PS (0x159)
1473 #define SPR_BOOKE_TLB2PS (0x15A)
1474 #define SPR_BOOKE_TLB3PS (0x15B)
1475 #define SPR_AMOR (0x15D)
1476 #define SPR_BOOKE_MAS7_MAS3 (0x174)
1477 #define SPR_BOOKE_IVOR0 (0x190)
1478 #define SPR_BOOKE_IVOR1 (0x191)
1479 #define SPR_BOOKE_IVOR2 (0x192)
1480 #define SPR_BOOKE_IVOR3 (0x193)
1481 #define SPR_BOOKE_IVOR4 (0x194)
1482 #define SPR_BOOKE_IVOR5 (0x195)
1483 #define SPR_BOOKE_IVOR6 (0x196)
1484 #define SPR_BOOKE_IVOR7 (0x197)
1485 #define SPR_BOOKE_IVOR8 (0x198)
1486 #define SPR_BOOKE_IVOR9 (0x199)
1487 #define SPR_BOOKE_IVOR10 (0x19A)
1488 #define SPR_BOOKE_IVOR11 (0x19B)
1489 #define SPR_BOOKE_IVOR12 (0x19C)
1490 #define SPR_BOOKE_IVOR13 (0x19D)
1491 #define SPR_BOOKE_IVOR14 (0x19E)
1492 #define SPR_BOOKE_IVOR15 (0x19F)
1493 #define SPR_BOOKE_IVOR38 (0x1B0)
1494 #define SPR_BOOKE_IVOR39 (0x1B1)
1495 #define SPR_BOOKE_IVOR40 (0x1B2)
1496 #define SPR_BOOKE_IVOR41 (0x1B3)
1497 #define SPR_BOOKE_IVOR42 (0x1B4)
1498 #define SPR_BOOKE_GIVOR2 (0x1B8)
1499 #define SPR_BOOKE_GIVOR3 (0x1B9)
1500 #define SPR_BOOKE_GIVOR4 (0x1BA)
1501 #define SPR_BOOKE_GIVOR8 (0x1BB)
1502 #define SPR_BOOKE_GIVOR13 (0x1BC)
1503 #define SPR_BOOKE_GIVOR14 (0x1BD)
1504 #define SPR_TIR (0x1BE)
1505 #define SPR_BOOKE_SPEFSCR (0x200)
1506 #define SPR_Exxx_BBEAR (0x201)
1507 #define SPR_Exxx_BBTAR (0x202)
1508 #define SPR_Exxx_L1CFG0 (0x203)
1509 #define SPR_Exxx_L1CFG1 (0x204)
1510 #define SPR_Exxx_NPIDR (0x205)
1511 #define SPR_ATBL (0x20E)
1512 #define SPR_ATBU (0x20F)
1513 #define SPR_IBAT0U (0x210)
1514 #define SPR_BOOKE_IVOR32 (0x210)
1515 #define SPR_RCPU_MI_GRA (0x210)
1516 #define SPR_IBAT0L (0x211)
1517 #define SPR_BOOKE_IVOR33 (0x211)
1518 #define SPR_IBAT1U (0x212)
1519 #define SPR_BOOKE_IVOR34 (0x212)
1520 #define SPR_IBAT1L (0x213)
1521 #define SPR_BOOKE_IVOR35 (0x213)
1522 #define SPR_IBAT2U (0x214)
1523 #define SPR_BOOKE_IVOR36 (0x214)
1524 #define SPR_IBAT2L (0x215)
1525 #define SPR_BOOKE_IVOR37 (0x215)
1526 #define SPR_IBAT3U (0x216)
1527 #define SPR_IBAT3L (0x217)
1528 #define SPR_DBAT0U (0x218)
1529 #define SPR_RCPU_L2U_GRA (0x218)
1530 #define SPR_DBAT0L (0x219)
1531 #define SPR_DBAT1U (0x21A)
1532 #define SPR_DBAT1L (0x21B)
1533 #define SPR_DBAT2U (0x21C)
1534 #define SPR_DBAT2L (0x21D)
1535 #define SPR_DBAT3U (0x21E)
1536 #define SPR_DBAT3L (0x21F)
1537 #define SPR_IBAT4U (0x230)
1538 #define SPR_RPCU_BBCMCR (0x230)
1539 #define SPR_MPC_IC_CST (0x230)
1540 #define SPR_Exxx_CTXCR (0x230)
1541 #define SPR_IBAT4L (0x231)
1542 #define SPR_MPC_IC_ADR (0x231)
1543 #define SPR_Exxx_DBCR3 (0x231)
1544 #define SPR_IBAT5U (0x232)
1545 #define SPR_MPC_IC_DAT (0x232)
1546 #define SPR_Exxx_DBCNT (0x232)
1547 #define SPR_IBAT5L (0x233)
1548 #define SPR_IBAT6U (0x234)
1549 #define SPR_IBAT6L (0x235)
1550 #define SPR_IBAT7U (0x236)
1551 #define SPR_IBAT7L (0x237)
1552 #define SPR_DBAT4U (0x238)
1553 #define SPR_RCPU_L2U_MCR (0x238)
1554 #define SPR_MPC_DC_CST (0x238)
1555 #define SPR_Exxx_ALTCTXCR (0x238)
1556 #define SPR_DBAT4L (0x239)
1557 #define SPR_MPC_DC_ADR (0x239)
1558 #define SPR_DBAT5U (0x23A)
1559 #define SPR_BOOKE_MCSRR0 (0x23A)
1560 #define SPR_MPC_DC_DAT (0x23A)
1561 #define SPR_DBAT5L (0x23B)
1562 #define SPR_BOOKE_MCSRR1 (0x23B)
1563 #define SPR_DBAT6U (0x23C)
1564 #define SPR_BOOKE_MCSR (0x23C)
1565 #define SPR_DBAT6L (0x23D)
1566 #define SPR_Exxx_MCAR (0x23D)
1567 #define SPR_DBAT7U (0x23E)
1568 #define SPR_BOOKE_DSRR0 (0x23E)
1569 #define SPR_DBAT7L (0x23F)
1570 #define SPR_BOOKE_DSRR1 (0x23F)
1571 #define SPR_BOOKE_SPRG8 (0x25C)
1572 #define SPR_BOOKE_SPRG9 (0x25D)
1573 #define SPR_BOOKE_MAS0 (0x270)
1574 #define SPR_BOOKE_MAS1 (0x271)
1575 #define SPR_BOOKE_MAS2 (0x272)
1576 #define SPR_BOOKE_MAS3 (0x273)
1577 #define SPR_BOOKE_MAS4 (0x274)
1578 #define SPR_BOOKE_MAS5 (0x275)
1579 #define SPR_BOOKE_MAS6 (0x276)
1580 #define SPR_BOOKE_PID1 (0x279)
1581 #define SPR_BOOKE_PID2 (0x27A)
1582 #define SPR_MPC_DPDR (0x280)
1583 #define SPR_MPC_IMMR (0x288)
1584 #define SPR_BOOKE_TLB0CFG (0x2B0)
1585 #define SPR_BOOKE_TLB1CFG (0x2B1)
1586 #define SPR_BOOKE_TLB2CFG (0x2B2)
1587 #define SPR_BOOKE_TLB3CFG (0x2B3)
1588 #define SPR_BOOKE_EPR (0x2BE)
1589 #define SPR_PERF0 (0x300)
1590 #define SPR_RCPU_MI_RBA0 (0x300)
1591 #define SPR_MPC_MI_CTR (0x300)
1592 #define SPR_POWER_USIER (0x300)
1593 #define SPR_PERF1 (0x301)
1594 #define SPR_RCPU_MI_RBA1 (0x301)
1595 #define SPR_POWER_UMMCR2 (0x301)
1596 #define SPR_PERF2 (0x302)
1597 #define SPR_RCPU_MI_RBA2 (0x302)
1598 #define SPR_MPC_MI_AP (0x302)
1599 #define SPR_POWER_UMMCRA (0x302)
1600 #define SPR_PERF3 (0x303)
1601 #define SPR_RCPU_MI_RBA3 (0x303)
1602 #define SPR_MPC_MI_EPN (0x303)
1603 #define SPR_POWER_UPMC1 (0x303)
1604 #define SPR_PERF4 (0x304)
1605 #define SPR_POWER_UPMC2 (0x304)
1606 #define SPR_PERF5 (0x305)
1607 #define SPR_MPC_MI_TWC (0x305)
1608 #define SPR_POWER_UPMC3 (0x305)
1609 #define SPR_PERF6 (0x306)
1610 #define SPR_MPC_MI_RPN (0x306)
1611 #define SPR_POWER_UPMC4 (0x306)
1612 #define SPR_PERF7 (0x307)
1613 #define SPR_POWER_UPMC5 (0x307)
1614 #define SPR_PERF8 (0x308)
1615 #define SPR_RCPU_L2U_RBA0 (0x308)
1616 #define SPR_MPC_MD_CTR (0x308)
1617 #define SPR_POWER_UPMC6 (0x308)
1618 #define SPR_PERF9 (0x309)
1619 #define SPR_RCPU_L2U_RBA1 (0x309)
1620 #define SPR_MPC_MD_CASID (0x309)
1621 #define SPR_970_UPMC7 (0X309)
1622 #define SPR_PERFA (0x30A)
1623 #define SPR_RCPU_L2U_RBA2 (0x30A)
1624 #define SPR_MPC_MD_AP (0x30A)
1625 #define SPR_970_UPMC8 (0X30A)
1626 #define SPR_PERFB (0x30B)
1627 #define SPR_RCPU_L2U_RBA3 (0x30B)
1628 #define SPR_MPC_MD_EPN (0x30B)
1629 #define SPR_POWER_UMMCR0 (0X30B)
1630 #define SPR_PERFC (0x30C)
1631 #define SPR_MPC_MD_TWB (0x30C)
1632 #define SPR_POWER_USIAR (0X30C)
1633 #define SPR_PERFD (0x30D)
1634 #define SPR_MPC_MD_TWC (0x30D)
1635 #define SPR_POWER_USDAR (0X30D)
1636 #define SPR_PERFE (0x30E)
1637 #define SPR_MPC_MD_RPN (0x30E)
1638 #define SPR_POWER_UMMCR1 (0X30E)
1639 #define SPR_PERFF (0x30F)
1640 #define SPR_MPC_MD_TW (0x30F)
1641 #define SPR_UPERF0 (0x310)
1642 #define SPR_POWER_SIER (0x310)
1643 #define SPR_UPERF1 (0x311)
1644 #define SPR_POWER_MMCR2 (0x311)
1645 #define SPR_UPERF2 (0x312)
1646 #define SPR_POWER_MMCRA (0X312)
1647 #define SPR_UPERF3 (0x313)
1648 #define SPR_POWER_PMC1 (0X313)
1649 #define SPR_UPERF4 (0x314)
1650 #define SPR_POWER_PMC2 (0X314)
1651 #define SPR_UPERF5 (0x315)
1652 #define SPR_POWER_PMC3 (0X315)
1653 #define SPR_UPERF6 (0x316)
1654 #define SPR_POWER_PMC4 (0X316)
1655 #define SPR_UPERF7 (0x317)
1656 #define SPR_POWER_PMC5 (0X317)
1657 #define SPR_UPERF8 (0x318)
1658 #define SPR_POWER_PMC6 (0X318)
1659 #define SPR_UPERF9 (0x319)
1660 #define SPR_970_PMC7 (0X319)
1661 #define SPR_UPERFA (0x31A)
1662 #define SPR_970_PMC8 (0X31A)
1663 #define SPR_UPERFB (0x31B)
1664 #define SPR_POWER_MMCR0 (0X31B)
1665 #define SPR_UPERFC (0x31C)
1666 #define SPR_POWER_SIAR (0X31C)
1667 #define SPR_UPERFD (0x31D)
1668 #define SPR_POWER_SDAR (0X31D)
1669 #define SPR_UPERFE (0x31E)
1670 #define SPR_POWER_MMCR1 (0X31E)
1671 #define SPR_UPERFF (0x31F)
1672 #define SPR_RCPU_MI_RA0 (0x320)
1673 #define SPR_MPC_MI_DBCAM (0x320)
1674 #define SPR_BESCRS (0x320)
1675 #define SPR_RCPU_MI_RA1 (0x321)
1676 #define SPR_MPC_MI_DBRAM0 (0x321)
1677 #define SPR_BESCRSU (0x321)
1678 #define SPR_RCPU_MI_RA2 (0x322)
1679 #define SPR_MPC_MI_DBRAM1 (0x322)
1680 #define SPR_BESCRR (0x322)
1681 #define SPR_RCPU_MI_RA3 (0x323)
1682 #define SPR_BESCRRU (0x323)
1683 #define SPR_EBBHR (0x324)
1684 #define SPR_EBBRR (0x325)
1685 #define SPR_BESCR (0x326)
1686 #define SPR_RCPU_L2U_RA0 (0x328)
1687 #define SPR_MPC_MD_DBCAM (0x328)
1688 #define SPR_RCPU_L2U_RA1 (0x329)
1689 #define SPR_MPC_MD_DBRAM0 (0x329)
1690 #define SPR_RCPU_L2U_RA2 (0x32A)
1691 #define SPR_MPC_MD_DBRAM1 (0x32A)
1692 #define SPR_RCPU_L2U_RA3 (0x32B)
1693 #define SPR_TAR (0x32F)
1694 #define SPR_IC (0x350)
1695 #define SPR_VTB (0x351)
1696 #define SPR_MMCRC (0x353)
1697 #define SPR_440_INV0 (0x370)
1698 #define SPR_440_INV1 (0x371)
1699 #define SPR_440_INV2 (0x372)
1700 #define SPR_440_INV3 (0x373)
1701 #define SPR_440_ITV0 (0x374)
1702 #define SPR_440_ITV1 (0x375)
1703 #define SPR_440_ITV2 (0x376)
1704 #define SPR_440_ITV3 (0x377)
1705 #define SPR_440_CCR1 (0x378)
1706 #define SPR_TACR (0x378)
1707 #define SPR_TCSCR (0x379)
1708 #define SPR_CSIGR (0x37a)
1709 #define SPR_DCRIPR (0x37B)
1710 #define SPR_POWER_SPMC1 (0x37C)
1711 #define SPR_POWER_SPMC2 (0x37D)
1712 #define SPR_POWER_MMCRS (0x37E)
1713 #define SPR_WORT (0x37F)
1714 #define SPR_PPR (0x380)
1715 #define SPR_750_GQR0 (0x390)
1716 #define SPR_440_DNV0 (0x390)
1717 #define SPR_750_GQR1 (0x391)
1718 #define SPR_440_DNV1 (0x391)
1719 #define SPR_750_GQR2 (0x392)
1720 #define SPR_440_DNV2 (0x392)
1721 #define SPR_750_GQR3 (0x393)
1722 #define SPR_440_DNV3 (0x393)
1723 #define SPR_750_GQR4 (0x394)
1724 #define SPR_440_DTV0 (0x394)
1725 #define SPR_750_GQR5 (0x395)
1726 #define SPR_440_DTV1 (0x395)
1727 #define SPR_750_GQR6 (0x396)
1728 #define SPR_440_DTV2 (0x396)
1729 #define SPR_750_GQR7 (0x397)
1730 #define SPR_440_DTV3 (0x397)
1731 #define SPR_750_THRM4 (0x398)
1732 #define SPR_750CL_HID2 (0x398)
1733 #define SPR_440_DVLIM (0x398)
1734 #define SPR_750_WPAR (0x399)
1735 #define SPR_440_IVLIM (0x399)
1736 #define SPR_TSCR (0x399)
1737 #define SPR_750_DMAU (0x39A)
1738 #define SPR_750_DMAL (0x39B)
1739 #define SPR_440_RSTCFG (0x39B)
1740 #define SPR_BOOKE_DCDBTRL (0x39C)
1741 #define SPR_BOOKE_DCDBTRH (0x39D)
1742 #define SPR_BOOKE_ICDBTRL (0x39E)
1743 #define SPR_BOOKE_ICDBTRH (0x39F)
1744 #define SPR_74XX_UMMCR2 (0x3A0)
1745 #define SPR_7XX_UPMC5 (0x3A1)
1746 #define SPR_7XX_UPMC6 (0x3A2)
1747 #define SPR_UBAMR (0x3A7)
1748 #define SPR_7XX_UMMCR0 (0x3A8)
1749 #define SPR_7XX_UPMC1 (0x3A9)
1750 #define SPR_7XX_UPMC2 (0x3AA)
1751 #define SPR_7XX_USIAR (0x3AB)
1752 #define SPR_7XX_UMMCR1 (0x3AC)
1753 #define SPR_7XX_UPMC3 (0x3AD)
1754 #define SPR_7XX_UPMC4 (0x3AE)
1755 #define SPR_USDA (0x3AF)
1756 #define SPR_40x_ZPR (0x3B0)
1757 #define SPR_BOOKE_MAS7 (0x3B0)
1758 #define SPR_74XX_MMCR2 (0x3B0)
1759 #define SPR_7XX_PMC5 (0x3B1)
1760 #define SPR_40x_PID (0x3B1)
1761 #define SPR_7XX_PMC6 (0x3B2)
1762 #define SPR_440_MMUCR (0x3B2)
1763 #define SPR_4xx_CCR0 (0x3B3)
1764 #define SPR_BOOKE_EPLC (0x3B3)
1765 #define SPR_405_IAC3 (0x3B4)
1766 #define SPR_BOOKE_EPSC (0x3B4)
1767 #define SPR_405_IAC4 (0x3B5)
1768 #define SPR_405_DVC1 (0x3B6)
1769 #define SPR_405_DVC2 (0x3B7)
1770 #define SPR_BAMR (0x3B7)
1771 #define SPR_7XX_MMCR0 (0x3B8)
1772 #define SPR_7XX_PMC1 (0x3B9)
1773 #define SPR_40x_SGR (0x3B9)
1774 #define SPR_7XX_PMC2 (0x3BA)
1775 #define SPR_40x_DCWR (0x3BA)
1776 #define SPR_7XX_SIAR (0x3BB)
1777 #define SPR_405_SLER (0x3BB)
1778 #define SPR_7XX_MMCR1 (0x3BC)
1779 #define SPR_405_SU0R (0x3BC)
1780 #define SPR_401_SKR (0x3BC)
1781 #define SPR_7XX_PMC3 (0x3BD)
1782 #define SPR_405_DBCR1 (0x3BD)
1783 #define SPR_7XX_PMC4 (0x3BE)
1784 #define SPR_SDA (0x3BF)
1785 #define SPR_403_VTBL (0x3CC)
1786 #define SPR_403_VTBU (0x3CD)
1787 #define SPR_DMISS (0x3D0)
1788 #define SPR_DCMP (0x3D1)
1789 #define SPR_HASH1 (0x3D2)
1790 #define SPR_HASH2 (0x3D3)
1791 #define SPR_BOOKE_ICDBDR (0x3D3)
1792 #define SPR_TLBMISS (0x3D4)
1793 #define SPR_IMISS (0x3D4)
1794 #define SPR_40x_ESR (0x3D4)
1795 #define SPR_PTEHI (0x3D5)
1796 #define SPR_ICMP (0x3D5)
1797 #define SPR_40x_DEAR (0x3D5)
1798 #define SPR_PTELO (0x3D6)
1799 #define SPR_RPA (0x3D6)
1800 #define SPR_40x_EVPR (0x3D6)
1801 #define SPR_L3PM (0x3D7)
1802 #define SPR_403_CDBCR (0x3D7)
1803 #define SPR_L3ITCR0 (0x3D8)
1804 #define SPR_TCR (0x3D8)
1805 #define SPR_40x_TSR (0x3D8)
1806 #define SPR_IBR (0x3DA)
1807 #define SPR_40x_TCR (0x3DA)
1808 #define SPR_ESASRR (0x3DB)
1809 #define SPR_40x_PIT (0x3DB)
1810 #define SPR_403_TBL (0x3DC)
1811 #define SPR_403_TBU (0x3DD)
1812 #define SPR_SEBR (0x3DE)
1813 #define SPR_40x_SRR2 (0x3DE)
1814 #define SPR_SER (0x3DF)
1815 #define SPR_40x_SRR3 (0x3DF)
1816 #define SPR_L3OHCR (0x3E8)
1817 #define SPR_L3ITCR1 (0x3E9)
1818 #define SPR_L3ITCR2 (0x3EA)
1819 #define SPR_L3ITCR3 (0x3EB)
1820 #define SPR_HID0 (0x3F0)
1821 #define SPR_40x_DBSR (0x3F0)
1822 #define SPR_HID1 (0x3F1)
1823 #define SPR_IABR (0x3F2)
1824 #define SPR_40x_DBCR0 (0x3F2)
1825 #define SPR_601_HID2 (0x3F2)
1826 #define SPR_Exxx_L1CSR0 (0x3F2)
1827 #define SPR_ICTRL (0x3F3)
1828 #define SPR_HID2 (0x3F3)
1829 #define SPR_750CL_HID4 (0x3F3)
1830 #define SPR_Exxx_L1CSR1 (0x3F3)
1831 #define SPR_440_DBDR (0x3F3)
1832 #define SPR_LDSTDB (0x3F4)
1833 #define SPR_750_TDCL (0x3F4)
1834 #define SPR_40x_IAC1 (0x3F4)
1835 #define SPR_MMUCSR0 (0x3F4)
1836 #define SPR_970_HID4 (0x3F4)
1837 #define SPR_DABR (0x3F5)
1838 #define DABR_MASK (~(target_ulong)0x7)
1839 #define SPR_Exxx_BUCSR (0x3F5)
1840 #define SPR_40x_IAC2 (0x3F5)
1841 #define SPR_601_HID5 (0x3F5)
1842 #define SPR_40x_DAC1 (0x3F6)
1843 #define SPR_MSSCR0 (0x3F6)
1844 #define SPR_970_HID5 (0x3F6)
1845 #define SPR_MSSSR0 (0x3F7)
1846 #define SPR_MSSCR1 (0x3F7)
1847 #define SPR_DABRX (0x3F7)
1848 #define SPR_40x_DAC2 (0x3F7)
1849 #define SPR_MMUCFG (0x3F7)
1850 #define SPR_LDSTCR (0x3F8)
1851 #define SPR_L2PMCR (0x3F8)
1852 #define SPR_750FX_HID2 (0x3F8)
1853 #define SPR_Exxx_L1FINV0 (0x3F8)
1854 #define SPR_L2CR (0x3F9)
1855 #define SPR_L3CR (0x3FA)
1856 #define SPR_750_TDCH (0x3FA)
1857 #define SPR_IABR2 (0x3FA)
1858 #define SPR_40x_DCCR (0x3FA)
1859 #define SPR_ICTC (0x3FB)
1860 #define SPR_40x_ICCR (0x3FB)
1861 #define SPR_THRM1 (0x3FC)
1862 #define SPR_403_PBL1 (0x3FC)
1863 #define SPR_SP (0x3FD)
1864 #define SPR_THRM2 (0x3FD)
1865 #define SPR_403_PBU1 (0x3FD)
1866 #define SPR_604_HID13 (0x3FD)
1867 #define SPR_LT (0x3FE)
1868 #define SPR_THRM3 (0x3FE)
1869 #define SPR_RCPU_FPECR (0x3FE)
1870 #define SPR_403_PBL2 (0x3FE)
1871 #define SPR_PIR (0x3FF)
1872 #define SPR_403_PBU2 (0x3FF)
1873 #define SPR_601_HID15 (0x3FF)
1874 #define SPR_604_HID15 (0x3FF)
1875 #define SPR_E500_SVR (0x3FF)
1877 /* Disable MAS Interrupt Updates for Hypervisor */
1878 #define EPCR_DMIUH (1 << 22)
1879 /* Disable Guest TLB Management Instructions */
1880 #define EPCR_DGTMI (1 << 23)
1881 /* Guest Interrupt Computation Mode */
1882 #define EPCR_GICM (1 << 24)
1883 /* Interrupt Computation Mode */
1884 #define EPCR_ICM (1 << 25)
1885 /* Disable Embedded Hypervisor Debug */
1886 #define EPCR_DUVD (1 << 26)
1887 /* Instruction Storage Interrupt Directed to Guest State */
1888 #define EPCR_ISIGS (1 << 27)
1889 /* Data Storage Interrupt Directed to Guest State */
1890 #define EPCR_DSIGS (1 << 28)
1891 /* Instruction TLB Error Interrupt Directed to Guest State */
1892 #define EPCR_ITLBGS (1 << 29)
1893 /* Data TLB Error Interrupt Directed to Guest State */
1894 #define EPCR_DTLBGS (1 << 30)
1895 /* External Input Interrupt Directed to Guest State */
1896 #define EPCR_EXTGS (1 << 31)
1898 #define L1CSR0_CPE 0x00010000 /* Data Cache Parity Enable */
1899 #define L1CSR0_CUL 0x00000400 /* (D-)Cache Unable to Lock */
1900 #define L1CSR0_DCLFR 0x00000100 /* D-Cache Lock Flash Reset */
1901 #define L1CSR0_DCFI 0x00000002 /* Data Cache Flash Invalidate */
1902 #define L1CSR0_DCE 0x00000001 /* Data Cache Enable */
1904 #define L1CSR1_CPE 0x00010000 /* Instruction Cache Parity Enable */
1905 #define L1CSR1_ICUL 0x00000400 /* I-Cache Unable to Lock */
1906 #define L1CSR1_ICLFR 0x00000100 /* I-Cache Lock Flash Reset */
1907 #define L1CSR1_ICFI 0x00000002 /* Instruction Cache Flash Invalidate */
1908 #define L1CSR1_ICE 0x00000001 /* Instruction Cache Enable */
1911 #define HID0_DEEPNAP (1 << 24) /* pre-2.06 */
1912 #define HID0_DOZE (1 << 23) /* pre-2.06 */
1913 #define HID0_NAP (1 << 22) /* pre-2.06 */
1914 #define HID0_HILE (1ull << (63 - 19)) /* POWER8 */
1916 /*****************************************************************************/
1917 /* PowerPC Instructions types definitions */
1919 PPC_NONE = 0x0000000000000000ULL,
1920 /* PowerPC base instructions set */
1921 PPC_INSNS_BASE = 0x0000000000000001ULL,
1922 /* integer operations instructions */
1923 #define PPC_INTEGER PPC_INSNS_BASE
1924 /* flow control instructions */
1925 #define PPC_FLOW PPC_INSNS_BASE
1926 /* virtual memory instructions */
1927 #define PPC_MEM PPC_INSNS_BASE
1928 /* ld/st with reservation instructions */
1929 #define PPC_RES PPC_INSNS_BASE
1930 /* spr/msr access instructions */
1931 #define PPC_MISC PPC_INSNS_BASE
1932 /* Deprecated instruction sets */
1933 /* Original POWER instruction set */
1934 PPC_POWER = 0x0000000000000002ULL,
1935 /* POWER2 instruction set extension */
1936 PPC_POWER2 = 0x0000000000000004ULL,
1937 /* Power RTC support */
1938 PPC_POWER_RTC = 0x0000000000000008ULL,
1939 /* Power-to-PowerPC bridge (601) */
1940 PPC_POWER_BR = 0x0000000000000010ULL,
1941 /* 64 bits PowerPC instruction set */
1942 PPC_64B = 0x0000000000000020ULL,
1943 /* New 64 bits extensions (PowerPC 2.0x) */
1944 PPC_64BX = 0x0000000000000040ULL,
1945 /* 64 bits hypervisor extensions */
1946 PPC_64H = 0x0000000000000080ULL,
1947 /* New wait instruction (PowerPC 2.0x) */
1948 PPC_WAIT = 0x0000000000000100ULL,
1949 /* Time base mftb instruction */
1950 PPC_MFTB = 0x0000000000000200ULL,
1952 /* Fixed-point unit extensions */
1953 /* PowerPC 602 specific */
1954 PPC_602_SPEC = 0x0000000000000400ULL,
1955 /* isel instruction */
1956 PPC_ISEL = 0x0000000000000800ULL,
1957 /* popcntb instruction */
1958 PPC_POPCNTB = 0x0000000000001000ULL,
1959 /* string load / store */
1960 PPC_STRING = 0x0000000000002000ULL,
1962 /* Floating-point unit extensions */
1963 /* Optional floating point instructions */
1964 PPC_FLOAT = 0x0000000000010000ULL,
1965 /* New floating-point extensions (PowerPC 2.0x) */
1966 PPC_FLOAT_EXT = 0x0000000000020000ULL,
1967 PPC_FLOAT_FSQRT = 0x0000000000040000ULL,
1968 PPC_FLOAT_FRES = 0x0000000000080000ULL,
1969 PPC_FLOAT_FRSQRTE = 0x0000000000100000ULL,
1970 PPC_FLOAT_FRSQRTES = 0x0000000000200000ULL,
1971 PPC_FLOAT_FSEL = 0x0000000000400000ULL,
1972 PPC_FLOAT_STFIWX = 0x0000000000800000ULL,
1974 /* Vector/SIMD extensions */
1975 /* Altivec support */
1976 PPC_ALTIVEC = 0x0000000001000000ULL,
1977 /* PowerPC 2.03 SPE extension */
1978 PPC_SPE = 0x0000000002000000ULL,
1979 /* PowerPC 2.03 SPE single-precision floating-point extension */
1980 PPC_SPE_SINGLE = 0x0000000004000000ULL,
1981 /* PowerPC 2.03 SPE double-precision floating-point extension */
1982 PPC_SPE_DOUBLE = 0x0000000008000000ULL,
1984 /* Optional memory control instructions */
1985 PPC_MEM_TLBIA = 0x0000000010000000ULL,
1986 PPC_MEM_TLBIE = 0x0000000020000000ULL,
1987 PPC_MEM_TLBSYNC = 0x0000000040000000ULL,
1988 /* sync instruction */
1989 PPC_MEM_SYNC = 0x0000000080000000ULL,
1990 /* eieio instruction */
1991 PPC_MEM_EIEIO = 0x0000000100000000ULL,
1993 /* Cache control instructions */
1994 PPC_CACHE = 0x0000000200000000ULL,
1995 /* icbi instruction */
1996 PPC_CACHE_ICBI = 0x0000000400000000ULL,
1997 /* dcbz instruction */
1998 PPC_CACHE_DCBZ = 0x0000000800000000ULL,
1999 /* dcba instruction */
2000 PPC_CACHE_DCBA = 0x0000002000000000ULL,
2001 /* Freescale cache locking instructions */
2002 PPC_CACHE_LOCK = 0x0000004000000000ULL,
2004 /* MMU related extensions */
2005 /* external control instructions */
2006 PPC_EXTERN = 0x0000010000000000ULL,
2007 /* segment register access instructions */
2008 PPC_SEGMENT = 0x0000020000000000ULL,
2009 /* PowerPC 6xx TLB management instructions */
2010 PPC_6xx_TLB = 0x0000040000000000ULL,
2011 /* PowerPC 74xx TLB management instructions */
2012 PPC_74xx_TLB = 0x0000080000000000ULL,
2013 /* PowerPC 40x TLB management instructions */
2014 PPC_40x_TLB = 0x0000100000000000ULL,
2015 /* segment register access instructions for PowerPC 64 "bridge" */
2016 PPC_SEGMENT_64B = 0x0000200000000000ULL,
2017 /* SLB management */
2018 PPC_SLBI = 0x0000400000000000ULL,
2020 /* Embedded PowerPC dedicated instructions */
2021 PPC_WRTEE = 0x0001000000000000ULL,
2022 /* PowerPC 40x exception model */
2023 PPC_40x_EXCP = 0x0002000000000000ULL,
2024 /* PowerPC 405 Mac instructions */
2025 PPC_405_MAC = 0x0004000000000000ULL,
2026 /* PowerPC 440 specific instructions */
2027 PPC_440_SPEC = 0x0008000000000000ULL,
2028 /* BookE (embedded) PowerPC specification */
2029 PPC_BOOKE = 0x0010000000000000ULL,
2030 /* mfapidi instruction */
2031 PPC_MFAPIDI = 0x0020000000000000ULL,
2032 /* tlbiva instruction */
2033 PPC_TLBIVA = 0x0040000000000000ULL,
2034 /* tlbivax instruction */
2035 PPC_TLBIVAX = 0x0080000000000000ULL,
2036 /* PowerPC 4xx dedicated instructions */
2037 PPC_4xx_COMMON = 0x0100000000000000ULL,
2038 /* PowerPC 40x ibct instructions */
2039 PPC_40x_ICBT = 0x0200000000000000ULL,
2040 /* rfmci is not implemented in all BookE PowerPC */
2041 PPC_RFMCI = 0x0400000000000000ULL,
2042 /* rfdi instruction */
2043 PPC_RFDI = 0x0800000000000000ULL,
2045 PPC_DCR = 0x1000000000000000ULL,
2046 /* DCR extended accesse */
2047 PPC_DCRX = 0x2000000000000000ULL,
2048 /* user-mode DCR access, implemented in PowerPC 460 */
2049 PPC_DCRUX = 0x4000000000000000ULL,
2050 /* popcntw and popcntd instructions */
2051 PPC_POPCNTWD = 0x8000000000000000ULL,
2053 #define PPC_TCG_INSNS (PPC_INSNS_BASE | PPC_POWER | PPC_POWER2 \
2054 | PPC_POWER_RTC | PPC_POWER_BR | PPC_64B \
2055 | PPC_64BX | PPC_64H | PPC_WAIT | PPC_MFTB \
2056 | PPC_602_SPEC | PPC_ISEL | PPC_POPCNTB \
2057 | PPC_STRING | PPC_FLOAT | PPC_FLOAT_EXT \
2058 | PPC_FLOAT_FSQRT | PPC_FLOAT_FRES \
2059 | PPC_FLOAT_FRSQRTE | PPC_FLOAT_FRSQRTES \
2060 | PPC_FLOAT_FSEL | PPC_FLOAT_STFIWX \
2061 | PPC_ALTIVEC | PPC_SPE | PPC_SPE_SINGLE \
2062 | PPC_SPE_DOUBLE | PPC_MEM_TLBIA \
2063 | PPC_MEM_TLBIE | PPC_MEM_TLBSYNC \
2064 | PPC_MEM_SYNC | PPC_MEM_EIEIO \
2065 | PPC_CACHE | PPC_CACHE_ICBI \
2067 | PPC_CACHE_DCBA | PPC_CACHE_LOCK \
2068 | PPC_EXTERN | PPC_SEGMENT | PPC_6xx_TLB \
2069 | PPC_74xx_TLB | PPC_40x_TLB | PPC_SEGMENT_64B \
2070 | PPC_SLBI | PPC_WRTEE | PPC_40x_EXCP \
2071 | PPC_405_MAC | PPC_440_SPEC | PPC_BOOKE \
2072 | PPC_MFAPIDI | PPC_TLBIVA | PPC_TLBIVAX \
2073 | PPC_4xx_COMMON | PPC_40x_ICBT | PPC_RFMCI \
2074 | PPC_RFDI | PPC_DCR | PPC_DCRX | PPC_DCRUX \
2077 /* extended type values */
2079 /* BookE 2.06 PowerPC specification */
2080 PPC2_BOOKE206 = 0x0000000000000001ULL,
2081 /* VSX (extensions to Altivec / VMX) */
2082 PPC2_VSX = 0x0000000000000002ULL,
2083 /* Decimal Floating Point (DFP) */
2084 PPC2_DFP = 0x0000000000000004ULL,
2085 /* Embedded.Processor Control */
2086 PPC2_PRCNTL = 0x0000000000000008ULL,
2087 /* Byte-reversed, indexed, double-word load and store */
2088 PPC2_DBRX = 0x0000000000000010ULL,
2089 /* Book I 2.05 PowerPC specification */
2090 PPC2_ISA205 = 0x0000000000000020ULL,
2091 /* VSX additions in ISA 2.07 */
2092 PPC2_VSX207 = 0x0000000000000040ULL,
2093 /* ISA 2.06B bpermd */
2094 PPC2_PERM_ISA206 = 0x0000000000000080ULL,
2095 /* ISA 2.06B divide extended variants */
2096 PPC2_DIVE_ISA206 = 0x0000000000000100ULL,
2097 /* ISA 2.06B larx/stcx. instructions */
2098 PPC2_ATOMIC_ISA206 = 0x0000000000000200ULL,
2099 /* ISA 2.06B floating point integer conversion */
2100 PPC2_FP_CVT_ISA206 = 0x0000000000000400ULL,
2101 /* ISA 2.06B floating point test instructions */
2102 PPC2_FP_TST_ISA206 = 0x0000000000000800ULL,
2103 /* ISA 2.07 bctar instruction */
2104 PPC2_BCTAR_ISA207 = 0x0000000000001000ULL,
2105 /* ISA 2.07 load/store quadword */
2106 PPC2_LSQ_ISA207 = 0x0000000000002000ULL,
2107 /* ISA 2.07 Altivec */
2108 PPC2_ALTIVEC_207 = 0x0000000000004000ULL,
2109 /* PowerISA 2.07 Book3s specification */
2110 PPC2_ISA207S = 0x0000000000008000ULL,
2111 /* Double precision floating point conversion for signed integer 64 */
2112 PPC2_FP_CVT_S64 = 0x0000000000010000ULL,
2113 /* Transactional Memory (ISA 2.07, Book II) */
2114 PPC2_TM = 0x0000000000020000ULL,
2116 #define PPC_TCG_INSNS2 (PPC2_BOOKE206 | PPC2_VSX | PPC2_PRCNTL | PPC2_DBRX | \
2117 PPC2_ISA205 | PPC2_VSX207 | PPC2_PERM_ISA206 | \
2118 PPC2_DIVE_ISA206 | PPC2_ATOMIC_ISA206 | \
2119 PPC2_FP_CVT_ISA206 | PPC2_FP_TST_ISA206 | \
2120 PPC2_BCTAR_ISA207 | PPC2_LSQ_ISA207 | \
2121 PPC2_ALTIVEC_207 | PPC2_ISA207S | PPC2_DFP | \
2122 PPC2_FP_CVT_S64 | PPC2_TM)
2125 /*****************************************************************************/
2126 /* Memory access type :
2127 * may be needed for precise access rights control and precise exceptions.
2130 /* 1 bit to define user level / supervisor access */
2132 ACCESS_SUPER = 0x01,
2133 /* Type of instruction that generated the access */
2134 ACCESS_CODE = 0x10, /* Code fetch access */
2135 ACCESS_INT = 0x20, /* Integer load/store access */
2136 ACCESS_FLOAT = 0x30, /* floating point load/store access */
2137 ACCESS_RES = 0x40, /* load/store with reservation */
2138 ACCESS_EXT = 0x50, /* external access */
2139 ACCESS_CACHE = 0x60, /* Cache manipulation */
2142 /* Hardware interruption sources:
2143 * all those exception can be raised simulteaneously
2145 /* Input pins definitions */
2147 /* 6xx bus input pins */
2148 PPC6xx_INPUT_HRESET = 0,
2149 PPC6xx_INPUT_SRESET = 1,
2150 PPC6xx_INPUT_CKSTP_IN = 2,
2151 PPC6xx_INPUT_MCP = 3,
2152 PPC6xx_INPUT_SMI = 4,
2153 PPC6xx_INPUT_INT = 5,
2154 PPC6xx_INPUT_TBEN = 6,
2155 PPC6xx_INPUT_WAKEUP = 7,
2160 /* Embedded PowerPC input pins */
2161 PPCBookE_INPUT_HRESET = 0,
2162 PPCBookE_INPUT_SRESET = 1,
2163 PPCBookE_INPUT_CKSTP_IN = 2,
2164 PPCBookE_INPUT_MCP = 3,
2165 PPCBookE_INPUT_SMI = 4,
2166 PPCBookE_INPUT_INT = 5,
2167 PPCBookE_INPUT_CINT = 6,
2172 /* PowerPC E500 input pins */
2173 PPCE500_INPUT_RESET_CORE = 0,
2174 PPCE500_INPUT_MCK = 1,
2175 PPCE500_INPUT_CINT = 3,
2176 PPCE500_INPUT_INT = 4,
2177 PPCE500_INPUT_DEBUG = 6,
2182 /* PowerPC 40x input pins */
2183 PPC40x_INPUT_RESET_CORE = 0,
2184 PPC40x_INPUT_RESET_CHIP = 1,
2185 PPC40x_INPUT_RESET_SYS = 2,
2186 PPC40x_INPUT_CINT = 3,
2187 PPC40x_INPUT_INT = 4,
2188 PPC40x_INPUT_HALT = 5,
2189 PPC40x_INPUT_DEBUG = 6,
2194 /* RCPU input pins */
2195 PPCRCPU_INPUT_PORESET = 0,
2196 PPCRCPU_INPUT_HRESET = 1,
2197 PPCRCPU_INPUT_SRESET = 2,
2198 PPCRCPU_INPUT_IRQ0 = 3,
2199 PPCRCPU_INPUT_IRQ1 = 4,
2200 PPCRCPU_INPUT_IRQ2 = 5,
2201 PPCRCPU_INPUT_IRQ3 = 6,
2202 PPCRCPU_INPUT_IRQ4 = 7,
2203 PPCRCPU_INPUT_IRQ5 = 8,
2204 PPCRCPU_INPUT_IRQ6 = 9,
2205 PPCRCPU_INPUT_IRQ7 = 10,
2209 #if defined(TARGET_PPC64)
2211 /* PowerPC 970 input pins */
2212 PPC970_INPUT_HRESET = 0,
2213 PPC970_INPUT_SRESET = 1,
2214 PPC970_INPUT_CKSTP = 2,
2215 PPC970_INPUT_TBEN = 3,
2216 PPC970_INPUT_MCP = 4,
2217 PPC970_INPUT_INT = 5,
2218 PPC970_INPUT_THINT = 6,
2223 /* POWER7 input pins */
2224 POWER7_INPUT_INT = 0,
2225 /* POWER7 probably has other inputs, but we don't care about them
2226 * for any existing machine. We can wire these up when we need
2232 /* Hardware exceptions definitions */
2234 /* External hardware exception sources */
2235 PPC_INTERRUPT_RESET = 0, /* Reset exception */
2236 PPC_INTERRUPT_WAKEUP, /* Wakeup exception */
2237 PPC_INTERRUPT_MCK, /* Machine check exception */
2238 PPC_INTERRUPT_EXT, /* External interrupt */
2239 PPC_INTERRUPT_SMI, /* System management interrupt */
2240 PPC_INTERRUPT_CEXT, /* Critical external interrupt */
2241 PPC_INTERRUPT_DEBUG, /* External debug exception */
2242 PPC_INTERRUPT_THERM, /* Thermal exception */
2243 /* Internal hardware exception sources */
2244 PPC_INTERRUPT_DECR, /* Decrementer exception */
2245 PPC_INTERRUPT_HDECR, /* Hypervisor decrementer exception */
2246 PPC_INTERRUPT_PIT, /* Programmable inteval timer interrupt */
2247 PPC_INTERRUPT_FIT, /* Fixed interval timer interrupt */
2248 PPC_INTERRUPT_WDT, /* Watchdog timer interrupt */
2249 PPC_INTERRUPT_CDOORBELL, /* Critical doorbell interrupt */
2250 PPC_INTERRUPT_DOORBELL, /* Doorbell interrupt */
2251 PPC_INTERRUPT_PERFM, /* Performance monitor interrupt */
2254 /* Processor Compatibility mask (PCR) */
2256 PCR_COMPAT_2_05 = 1ull << (63-62),
2257 PCR_COMPAT_2_06 = 1ull << (63-61),
2258 PCR_VEC_DIS = 1ull << (63-0), /* Vec. disable (bit NA since POWER8) */
2259 PCR_VSX_DIS = 1ull << (63-1), /* VSX disable (bit NA since POWER8) */
2260 PCR_TM_DIS = 1ull << (63-2), /* Trans. memory disable (POWER8) */
2265 HMER_MALFUNCTION_ALERT = 1ull << (63 - 0),
2266 HMER_PROC_RECV_DONE = 1ull << (63 - 2),
2267 HMER_PROC_RECV_ERROR_MASKED = 1ull << (63 - 3),
2268 HMER_TFAC_ERROR = 1ull << (63 - 4),
2269 HMER_TFMR_PARITY_ERROR = 1ull << (63 - 5),
2270 HMER_XSCOM_FAIL = 1ull << (63 - 8),
2271 HMER_XSCOM_DONE = 1ull << (63 - 9),
2272 HMER_PROC_RECV_AGAIN = 1ull << (63 - 11),
2273 HMER_WARN_RISE = 1ull << (63 - 14),
2274 HMER_WARN_FALL = 1ull << (63 - 15),
2275 HMER_SCOM_FIR_HMI = 1ull << (63 - 16),
2276 HMER_TRIG_FIR_HMI = 1ull << (63 - 17),
2277 HMER_HYP_RESOURCE_ERR = 1ull << (63 - 20),
2278 HMER_XSCOM_STATUS_MASK = 7ull << (63 - 23),
2279 HMER_XSCOM_STATUS_LSH = (63 - 23),
2282 /* Alternate Interrupt Location (AIL) */
2287 AIL_C000_0000_0000_4000 = 3,
2290 /*****************************************************************************/
2292 static inline target_ulong cpu_read_xer(CPUPPCState *env)
2294 return env->xer | (env->so << XER_SO) | (env->ov << XER_OV) | (env->ca << XER_CA);
2297 static inline void cpu_write_xer(CPUPPCState *env, target_ulong xer)
2299 env->so = (xer >> XER_SO) & 1;
2300 env->ov = (xer >> XER_OV) & 1;
2301 env->ca = (xer >> XER_CA) & 1;
2302 env->xer = xer & ~((1u << XER_SO) | (1u << XER_OV) | (1u << XER_CA));
2305 static inline void cpu_get_tb_cpu_state(CPUPPCState *env, target_ulong *pc,
2306 target_ulong *cs_base, int *flags)
2310 *flags = env->hflags;
2313 #if !defined(CONFIG_USER_ONLY)
2314 static inline int booke206_tlbm_id(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2316 uintptr_t tlbml = (uintptr_t)tlbm;
2317 uintptr_t tlbl = (uintptr_t)env->tlb.tlbm;
2319 return (tlbml - tlbl) / sizeof(env->tlb.tlbm[0]);
2322 static inline int booke206_tlb_size(CPUPPCState *env, int tlbn)
2324 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2325 int r = tlbncfg & TLBnCFG_N_ENTRY;
2329 static inline int booke206_tlb_ways(CPUPPCState *env, int tlbn)
2331 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2332 int r = tlbncfg >> TLBnCFG_ASSOC_SHIFT;
2336 static inline int booke206_tlbm_to_tlbn(CPUPPCState *env, ppcmas_tlb_t *tlbm)
2338 int id = booke206_tlbm_id(env, tlbm);
2342 for (i = 0; i < BOOKE206_MAX_TLBN; i++) {
2343 end += booke206_tlb_size(env, i);
2349 cpu_abort(CPU(ppc_env_get_cpu(env)), "Unknown TLBe: %d\n", id);
2353 static inline int booke206_tlbm_to_way(CPUPPCState *env, ppcmas_tlb_t *tlb)
2355 int tlbn = booke206_tlbm_to_tlbn(env, tlb);
2356 int tlbid = booke206_tlbm_id(env, tlb);
2357 return tlbid & (booke206_tlb_ways(env, tlbn) - 1);
2360 static inline ppcmas_tlb_t *booke206_get_tlbm(CPUPPCState *env, const int tlbn,
2361 target_ulong ea, int way)
2364 uint32_t ways = booke206_tlb_ways(env, tlbn);
2365 int ways_bits = ctz32(ways);
2366 int tlb_bits = ctz32(booke206_tlb_size(env, tlbn));
2370 ea >>= MAS2_EPN_SHIFT;
2371 ea &= (1 << (tlb_bits - ways_bits)) - 1;
2372 r = (ea << ways_bits) | way;
2374 if (r >= booke206_tlb_size(env, tlbn)) {
2378 /* bump up to tlbn index */
2379 for (i = 0; i < tlbn; i++) {
2380 r += booke206_tlb_size(env, i);
2383 return &env->tlb.tlbm[r];
2386 /* returns bitmap of supported page sizes for a given TLB */
2387 static inline uint32_t booke206_tlbnps(CPUPPCState *env, const int tlbn)
2393 ret = env->spr[SPR_BOOKE_TLB0PS + tlbn];
2395 uint32_t tlbncfg = env->spr[SPR_BOOKE_TLB0CFG + tlbn];
2396 uint32_t min = (tlbncfg & TLBnCFG_MINSIZE) >> TLBnCFG_MINSIZE_SHIFT;
2397 uint32_t max = (tlbncfg & TLBnCFG_MAXSIZE) >> TLBnCFG_MAXSIZE_SHIFT;
2399 for (i = min; i <= max; i++) {
2400 ret |= (1 << (i << 1));
2409 static inline bool msr_is_64bit(CPUPPCState *env, target_ulong msr)
2411 if (env->mmu_model == POWERPC_MMU_BOOKE206) {
2412 return msr & (1ULL << MSR_CM);
2415 return msr & (1ULL << MSR_SF);
2419 * Check whether register rx is in the range between start and
2420 * start + nregs (as needed by the LSWX and LSWI instructions)
2422 static inline bool lsw_reg_in_range(int start, int nregs, int rx)
2424 return (start + nregs <= 32 && rx >= start && rx < start + nregs) ||
2425 (start + nregs > 32 && (rx >= start || rx < start + nregs - 32));
2428 extern void (*cpu_ppc_hypercall)(PowerPCCPU *);
2430 #include "exec/exec-all.h"
2432 void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUPPCState *env);
2435 * ppc_get_vcpu_dt_id:
2436 * @cs: a PowerPCCPU struct.
2438 * Returns a device-tree ID for a CPU.
2440 int ppc_get_vcpu_dt_id(PowerPCCPU *cpu);
2443 * ppc_get_vcpu_by_dt_id:
2444 * @cpu_dt_id: a device tree id
2446 * Searches for a CPU by @cpu_dt_id.
2448 * Returns: a PowerPCCPU struct
2450 PowerPCCPU *ppc_get_vcpu_by_dt_id(int cpu_dt_id);
2452 void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len);
2453 #endif /* !defined (__CPU_PPC_H__) */
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