qemu/target-lm32/cpu.c

   1 /*
   2  * QEMU LatticeMico32 CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This library is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU Lesser General Public
   8  * License as published by the Free Software Foundation; either
   9  * version 2.1 of the License, or (at your option) any later version.
  10  *
  11  * This library is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14  * Lesser General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU Lesser General Public
  17  * License along with this library; if not, see
  18  * <http://www.gnu.org/licenses/lgpl-2.1.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "qemu-common.h"
  23
  24
  25 static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
  26 {
  27     LM32CPU *cpu = LM32_CPU(cs);
  28
  29     cpu->env.pc = value;
  30 }
  31
  32 /* Sort alphabetically by type name. */
  33 static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
  34 {
  35     ObjectClass *class_a = (ObjectClass *)a;
  36     ObjectClass *class_b = (ObjectClass *)b;
  37     const char *name_a, *name_b;
  38
  39     name_a = object_class_get_name(class_a);
  40     name_b = object_class_get_name(class_b);
  41     return strcmp(name_a, name_b);
  42 }
  43
  44 static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
  45 {
  46     ObjectClass *oc = data;
  47     CPUListState *s = user_data;
  48     const char *typename = object_class_get_name(oc);
  49     char *name;
  50
  51     name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
  52     (*s->cpu_fprintf)(s->file, "  %s\n", name);
  53     g_free(name);
  54 }
  55
  56
  57 void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
  58 {
  59     CPUListState s = {
  60         .file = f,
  61         .cpu_fprintf = cpu_fprintf,
  62     };
  63     GSList *list;
  64
  65     list = object_class_get_list(TYPE_LM32_CPU, false);
  66     list = g_slist_sort(list, lm32_cpu_list_compare);
  67     (*cpu_fprintf)(f, "Available CPUs:\n");
  68     g_slist_foreach(list, lm32_cpu_list_entry, &s);
  69     g_slist_free(list);
  70 }
  71
  72 static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
  73 {
  74     CPULM32State *env = &cpu->env;
  75     uint32_t cfg = 0;
  76
  77     if (cpu->features & LM32_FEATURE_MULTIPLY) {
  78         cfg |= CFG_M;
  79     }
  80
  81     if (cpu->features & LM32_FEATURE_DIVIDE) {
  82         cfg |= CFG_D;
  83     }
  84
  85     if (cpu->features & LM32_FEATURE_SHIFT) {
  86         cfg |= CFG_S;
  87     }
  88
  89     if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
  90         cfg |= CFG_X;
  91     }
  92
  93     if (cpu->features & LM32_FEATURE_I_CACHE) {
  94         cfg |= CFG_IC;
  95     }
  96
  97     if (cpu->features & LM32_FEATURE_D_CACHE) {
  98         cfg |= CFG_DC;
  99     }
 100
 101     if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
 102         cfg |= CFG_CC;
 103     }
 104
 105     cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
 106     cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
 107     cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
 108     cfg |= (cpu->revision << CFG_REV_SHIFT);
 109
 110     env->cfg = cfg;
 111 }
 112
 113 static bool lm32_cpu_has_work(CPUState *cs)
 114 {
 115     return cs->interrupt_request & CPU_INTERRUPT_HARD;
 116 }
 117
 118 /* CPUClass::reset() */
 119 static void lm32_cpu_reset(CPUState *s)
 120 {
 121     LM32CPU *cpu = LM32_CPU(s);
 122     LM32CPUClass *lcc = LM32_CPU_GET_CLASS(cpu);
 123     CPULM32State *env = &cpu->env;
 124
 125     lcc->parent_reset(s);
 126
 127     /* reset cpu state */
 128     memset(env, 0, offsetof(CPULM32State, eba));
 129
 130     lm32_cpu_init_cfg_reg(cpu);
 131     tlb_flush(s, 1);
 132 }
 133
 134 static void lm32_cpu_realizefn(DeviceState *dev, Error **errp)
 135 {
 136     CPUState *cs = CPU(dev);
 137     LM32CPUClass *lcc = LM32_CPU_GET_CLASS(dev);
 138
 139     cpu_reset(cs);
 140
 141     qemu_init_vcpu(cs);
 142
 143     lcc->parent_realize(dev, errp);
 144 }
 145
 146 static void lm32_cpu_initfn(Object *obj)
 147 {
 148     CPUState *cs = CPU(obj);
 149     LM32CPU *cpu = LM32_CPU(obj);
 150     CPULM32State *env = &cpu->env;
 151     static bool tcg_initialized;
 152
 153     cs->env_ptr = env;
 154     cpu_exec_init(cs, &error_abort);
 155
 156     env->flags = 0;
 157
 158     if (tcg_enabled() && !tcg_initialized) {
 159         tcg_initialized = true;
 160         lm32_translate_init();
 161     }
 162 }
 163
 164 static void lm32_basic_cpu_initfn(Object *obj)
 165 {
 166     LM32CPU *cpu = LM32_CPU(obj);
 167
 168     cpu->revision = 3;
 169     cpu->num_interrupts = 32;
 170     cpu->num_breakpoints = 4;
 171     cpu->num_watchpoints = 4;
 172     cpu->features = LM32_FEATURE_SHIFT
 173                   | LM32_FEATURE_SIGN_EXTEND
 174                   | LM32_FEATURE_CYCLE_COUNT;
 175 }
 176
 177 static void lm32_standard_cpu_initfn(Object *obj)
 178 {
 179     LM32CPU *cpu = LM32_CPU(obj);
 180
 181     cpu->revision = 3;
 182     cpu->num_interrupts = 32;
 183     cpu->num_breakpoints = 4;
 184     cpu->num_watchpoints = 4;
 185     cpu->features = LM32_FEATURE_MULTIPLY
 186                   | LM32_FEATURE_DIVIDE
 187                   | LM32_FEATURE_SHIFT
 188                   | LM32_FEATURE_SIGN_EXTEND
 189                   | LM32_FEATURE_I_CACHE
 190                   | LM32_FEATURE_CYCLE_COUNT;
 191 }
 192
 193 static void lm32_full_cpu_initfn(Object *obj)
 194 {
 195     LM32CPU *cpu = LM32_CPU(obj);
 196
 197     cpu->revision = 3;
 198     cpu->num_interrupts = 32;
 199     cpu->num_breakpoints = 4;
 200     cpu->num_watchpoints = 4;
 201     cpu->features = LM32_FEATURE_MULTIPLY
 202                   | LM32_FEATURE_DIVIDE
 203                   | LM32_FEATURE_SHIFT
 204                   | LM32_FEATURE_SIGN_EXTEND
 205                   | LM32_FEATURE_I_CACHE
 206                   | LM32_FEATURE_D_CACHE
 207                   | LM32_FEATURE_CYCLE_COUNT;
 208 }
 209
 210 typedef struct LM32CPUInfo {
 211     const char *name;
 212     void (*initfn)(Object *obj);
 213 } LM32CPUInfo;
 214
 215 static const LM32CPUInfo lm32_cpus[] = {
 216     {
 217         .name = "lm32-basic",
 218         .initfn = lm32_basic_cpu_initfn,
 219     },
 220     {
 221         .name = "lm32-standard",
 222         .initfn = lm32_standard_cpu_initfn,
 223     },
 224     {
 225         .name = "lm32-full",
 226         .initfn = lm32_full_cpu_initfn,
 227     },
 228 };
 229
 230 static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
 231 {
 232     ObjectClass *oc;
 233     char *typename;
 234
 235     if (cpu_model == NULL) {
 236         return NULL;
 237     }
 238
 239     typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
 240     oc = object_class_by_name(typename);
 241     g_free(typename);
 242     if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
 243                        object_class_is_abstract(oc))) {
 244         oc = NULL;
 245     }
 246     return oc;
 247 }
 248
 249 static void lm32_cpu_class_init(ObjectClass *oc, void *data)
 250 {
 251     LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
 252     CPUClass *cc = CPU_CLASS(oc);
 253     DeviceClass *dc = DEVICE_CLASS(oc);
 254
 255     lcc->parent_realize = dc->realize;
 256     dc->realize = lm32_cpu_realizefn;
 257
 258     lcc->parent_reset = cc->reset;
 259     cc->reset = lm32_cpu_reset;
 260
 261     cc->class_by_name = lm32_cpu_class_by_name;
 262     cc->has_work = lm32_cpu_has_work;
 263     cc->do_interrupt = lm32_cpu_do_interrupt;
 264     cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt;
 265     cc->dump_state = lm32_cpu_dump_state;
 266     cc->set_pc = lm32_cpu_set_pc;
 267     cc->gdb_read_register = lm32_cpu_gdb_read_register;
 268     cc->gdb_write_register = lm32_cpu_gdb_write_register;
 269 #ifdef CONFIG_USER_ONLY
 270     cc->handle_mmu_fault = lm32_cpu_handle_mmu_fault;
 271 #else
 272     cc->get_phys_page_debug = lm32_cpu_get_phys_page_debug;
 273     cc->vmsd = &vmstate_lm32_cpu;
 274 #endif
 275     cc->gdb_num_core_regs = 32 + 7;
 276     cc->gdb_stop_before_watchpoint = true;
 277     cc->debug_excp_handler = lm32_debug_excp_handler;
 278 }
 279
 280 static void lm32_register_cpu_type(const LM32CPUInfo *info)
 281 {
 282     TypeInfo type_info = {
 283         .parent = TYPE_LM32_CPU,
 284         .instance_init = info->initfn,
 285     };
 286
 287     type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
 288     type_register(&type_info);
 289     g_free((void *)type_info.name);
 290 }
 291
 292 static const TypeInfo lm32_cpu_type_info = {
 293     .name = TYPE_LM32_CPU,
 294     .parent = TYPE_CPU,
 295     .instance_size = sizeof(LM32CPU),
 296     .instance_init = lm32_cpu_initfn,
 297     .abstract = true,
 298     .class_size = sizeof(LM32CPUClass),
 299     .class_init = lm32_cpu_class_init,
 300 };
 301
 302 static void lm32_cpu_register_types(void)
 303 {
 304     int i;
 305
 306     type_register_static(&lm32_cpu_type_info);
 307     for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
 308         lm32_register_cpu_type(&lm32_cpus[i]);
 309     }
 310 }
 311
 312 type_init(lm32_cpu_register_types)