2 * x86 FPU, MMX/3DNow!/SSE/SSE2/SSE3/SSSE3/SSE4/PNI helpers
4 * Copyright (c) 2003 Fabrice Bellard
6 * This library is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU Lesser General Public
8 * License as published by the Free Software Foundation; either
9 * version 2 of the License, or (at your option) any later version.
11 * This library is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * Lesser General Public License for more details.
16 * You should have received a copy of the GNU Lesser General Public
17 * License along with this library; if not, see <http://www.gnu.org/licenses/>.
22 #include "exec/helper-proto.h"
23 #include "qemu/host-utils.h"
24 #include "exec/cpu_ldst.h"
26 #define FPU_RC_MASK 0xc00
27 #define FPU_RC_NEAR 0x000
28 #define FPU_RC_DOWN 0x400
29 #define FPU_RC_UP 0x800
30 #define FPU_RC_CHOP 0xc00
32 #define MAXTAN 9223372036854775808.0
34 /* the following deal with x86 long double-precision numbers */
35 #define MAXEXPD 0x7fff
37 #define EXPD(fp) (fp.l.upper & 0x7fff)
38 #define SIGND(fp) ((fp.l.upper) & 0x8000)
39 #define MANTD(fp) (fp.l.lower)
40 #define BIASEXPONENT(fp) fp.l.upper = (fp.l.upper & ~(0x7fff)) | EXPBIAS
42 #define FPUS_IE (1 << 0)
43 #define FPUS_DE (1 << 1)
44 #define FPUS_ZE (1 << 2)
45 #define FPUS_OE (1 << 3)
46 #define FPUS_UE (1 << 4)
47 #define FPUS_PE (1 << 5)
48 #define FPUS_SF (1 << 6)
49 #define FPUS_SE (1 << 7)
50 #define FPUS_B (1 << 15)
54 #define floatx80_lg2 make_floatx80(0x3ffd, 0x9a209a84fbcff799LL)
55 #define floatx80_l2e make_floatx80(0x3fff, 0xb8aa3b295c17f0bcLL)
56 #define floatx80_l2t make_floatx80(0x4000, 0xd49a784bcd1b8afeLL)
58 static inline void fpush(CPUX86State *env)
60 env->fpstt = (env->fpstt - 1) & 7;
61 env->fptags[env->fpstt] = 0; /* validate stack entry */
64 static inline void fpop(CPUX86State *env)
66 env->fptags[env->fpstt] = 1; /* invalidate stack entry */
67 env->fpstt = (env->fpstt + 1) & 7;
70 static inline floatx80 helper_fldt(CPUX86State *env, target_ulong ptr)
74 temp.l.lower = cpu_ldq_data(env, ptr);
75 temp.l.upper = cpu_lduw_data(env, ptr + 8);
79 static inline void helper_fstt(CPUX86State *env, floatx80 f, target_ulong ptr)
84 cpu_stq_data(env, ptr, temp.l.lower);
85 cpu_stw_data(env, ptr + 8, temp.l.upper);
90 static inline double floatx80_to_double(CPUX86State *env, floatx80 a)
97 u.f64 = floatx80_to_float64(a, &env->fp_status);
101 static inline floatx80 double_to_floatx80(CPUX86State *env, double a)
109 return float64_to_floatx80(u.f64, &env->fp_status);
112 static void fpu_set_exception(CPUX86State *env, int mask)
115 if (env->fpus & (~env->fpuc & FPUC_EM)) {
116 env->fpus |= FPUS_SE | FPUS_B;
120 static inline floatx80 helper_fdiv(CPUX86State *env, floatx80 a, floatx80 b)
122 if (floatx80_is_zero(b)) {
123 fpu_set_exception(env, FPUS_ZE);
125 return floatx80_div(a, b, &env->fp_status);
128 static void fpu_raise_exception(CPUX86State *env)
130 if (env->cr[0] & CR0_NE_MASK) {
131 raise_exception(env, EXCP10_COPR);
133 #if !defined(CONFIG_USER_ONLY)
140 void helper_flds_FT0(CPUX86State *env, uint32_t val)
148 FT0 = float32_to_floatx80(u.f, &env->fp_status);
151 void helper_fldl_FT0(CPUX86State *env, uint64_t val)
159 FT0 = float64_to_floatx80(u.f, &env->fp_status);
162 void helper_fildl_FT0(CPUX86State *env, int32_t val)
164 FT0 = int32_to_floatx80(val, &env->fp_status);
167 void helper_flds_ST0(CPUX86State *env, uint32_t val)
175 new_fpstt = (env->fpstt - 1) & 7;
177 env->fpregs[new_fpstt].d = float32_to_floatx80(u.f, &env->fp_status);
178 env->fpstt = new_fpstt;
179 env->fptags[new_fpstt] = 0; /* validate stack entry */
182 void helper_fldl_ST0(CPUX86State *env, uint64_t val)
190 new_fpstt = (env->fpstt - 1) & 7;
192 env->fpregs[new_fpstt].d = float64_to_floatx80(u.f, &env->fp_status);
193 env->fpstt = new_fpstt;
194 env->fptags[new_fpstt] = 0; /* validate stack entry */
197 void helper_fildl_ST0(CPUX86State *env, int32_t val)
201 new_fpstt = (env->fpstt - 1) & 7;
202 env->fpregs[new_fpstt].d = int32_to_floatx80(val, &env->fp_status);
203 env->fpstt = new_fpstt;
204 env->fptags[new_fpstt] = 0; /* validate stack entry */
207 void helper_fildll_ST0(CPUX86State *env, int64_t val)
211 new_fpstt = (env->fpstt - 1) & 7;
212 env->fpregs[new_fpstt].d = int64_to_floatx80(val, &env->fp_status);
213 env->fpstt = new_fpstt;
214 env->fptags[new_fpstt] = 0; /* validate stack entry */
217 uint32_t helper_fsts_ST0(CPUX86State *env)
224 u.f = floatx80_to_float32(ST0, &env->fp_status);
228 uint64_t helper_fstl_ST0(CPUX86State *env)
235 u.f = floatx80_to_float64(ST0, &env->fp_status);
239 int32_t helper_fist_ST0(CPUX86State *env)
243 val = floatx80_to_int32(ST0, &env->fp_status);
244 if (val != (int16_t)val) {
250 int32_t helper_fistl_ST0(CPUX86State *env)
253 signed char old_exp_flags;
255 old_exp_flags = get_float_exception_flags(&env->fp_status);
256 set_float_exception_flags(0, &env->fp_status);
258 val = floatx80_to_int32(ST0, &env->fp_status);
259 if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
262 set_float_exception_flags(get_float_exception_flags(&env->fp_status)
263 | old_exp_flags, &env->fp_status);
267 int64_t helper_fistll_ST0(CPUX86State *env)
270 signed char old_exp_flags;
272 old_exp_flags = get_float_exception_flags(&env->fp_status);
273 set_float_exception_flags(0, &env->fp_status);
275 val = floatx80_to_int64(ST0, &env->fp_status);
276 if (get_float_exception_flags(&env->fp_status) & float_flag_invalid) {
277 val = 0x8000000000000000ULL;
279 set_float_exception_flags(get_float_exception_flags(&env->fp_status)
280 | old_exp_flags, &env->fp_status);
284 int32_t helper_fistt_ST0(CPUX86State *env)
288 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
289 if (val != (int16_t)val) {
295 int32_t helper_fisttl_ST0(CPUX86State *env)
299 val = floatx80_to_int32_round_to_zero(ST0, &env->fp_status);
303 int64_t helper_fisttll_ST0(CPUX86State *env)
307 val = floatx80_to_int64_round_to_zero(ST0, &env->fp_status);
311 void helper_fldt_ST0(CPUX86State *env, target_ulong ptr)
315 new_fpstt = (env->fpstt - 1) & 7;
316 env->fpregs[new_fpstt].d = helper_fldt(env, ptr);
317 env->fpstt = new_fpstt;
318 env->fptags[new_fpstt] = 0; /* validate stack entry */
321 void helper_fstt_ST0(CPUX86State *env, target_ulong ptr)
323 helper_fstt(env, ST0, ptr);
326 void helper_fpush(CPUX86State *env)
331 void helper_fpop(CPUX86State *env)
336 void helper_fdecstp(CPUX86State *env)
338 env->fpstt = (env->fpstt - 1) & 7;
339 env->fpus &= ~0x4700;
342 void helper_fincstp(CPUX86State *env)
344 env->fpstt = (env->fpstt + 1) & 7;
345 env->fpus &= ~0x4700;
350 void helper_ffree_STN(CPUX86State *env, int st_index)
352 env->fptags[(env->fpstt + st_index) & 7] = 1;
355 void helper_fmov_ST0_FT0(CPUX86State *env)
360 void helper_fmov_FT0_STN(CPUX86State *env, int st_index)
365 void helper_fmov_ST0_STN(CPUX86State *env, int st_index)
370 void helper_fmov_STN_ST0(CPUX86State *env, int st_index)
375 void helper_fxchg_ST0_STN(CPUX86State *env, int st_index)
386 static const int fcom_ccval[4] = {0x0100, 0x4000, 0x0000, 0x4500};
388 void helper_fcom_ST0_FT0(CPUX86State *env)
392 ret = floatx80_compare(ST0, FT0, &env->fp_status);
393 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
396 void helper_fucom_ST0_FT0(CPUX86State *env)
400 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
401 env->fpus = (env->fpus & ~0x4500) | fcom_ccval[ret + 1];
404 static const int fcomi_ccval[4] = {CC_C, CC_Z, 0, CC_Z | CC_P | CC_C};
406 void helper_fcomi_ST0_FT0(CPUX86State *env)
411 ret = floatx80_compare(ST0, FT0, &env->fp_status);
412 eflags = cpu_cc_compute_all(env, CC_OP);
413 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
417 void helper_fucomi_ST0_FT0(CPUX86State *env)
422 ret = floatx80_compare_quiet(ST0, FT0, &env->fp_status);
423 eflags = cpu_cc_compute_all(env, CC_OP);
424 eflags = (eflags & ~(CC_Z | CC_P | CC_C)) | fcomi_ccval[ret + 1];
428 void helper_fadd_ST0_FT0(CPUX86State *env)
430 ST0 = floatx80_add(ST0, FT0, &env->fp_status);
433 void helper_fmul_ST0_FT0(CPUX86State *env)
435 ST0 = floatx80_mul(ST0, FT0, &env->fp_status);
438 void helper_fsub_ST0_FT0(CPUX86State *env)
440 ST0 = floatx80_sub(ST0, FT0, &env->fp_status);
443 void helper_fsubr_ST0_FT0(CPUX86State *env)
445 ST0 = floatx80_sub(FT0, ST0, &env->fp_status);
448 void helper_fdiv_ST0_FT0(CPUX86State *env)
450 ST0 = helper_fdiv(env, ST0, FT0);
453 void helper_fdivr_ST0_FT0(CPUX86State *env)
455 ST0 = helper_fdiv(env, FT0, ST0);
458 /* fp operations between STN and ST0 */
460 void helper_fadd_STN_ST0(CPUX86State *env, int st_index)
462 ST(st_index) = floatx80_add(ST(st_index), ST0, &env->fp_status);
465 void helper_fmul_STN_ST0(CPUX86State *env, int st_index)
467 ST(st_index) = floatx80_mul(ST(st_index), ST0, &env->fp_status);
470 void helper_fsub_STN_ST0(CPUX86State *env, int st_index)
472 ST(st_index) = floatx80_sub(ST(st_index), ST0, &env->fp_status);
475 void helper_fsubr_STN_ST0(CPUX86State *env, int st_index)
477 ST(st_index) = floatx80_sub(ST0, ST(st_index), &env->fp_status);
480 void helper_fdiv_STN_ST0(CPUX86State *env, int st_index)
485 *p = helper_fdiv(env, *p, ST0);
488 void helper_fdivr_STN_ST0(CPUX86State *env, int st_index)
493 *p = helper_fdiv(env, ST0, *p);
496 /* misc FPU operations */
497 void helper_fchs_ST0(CPUX86State *env)
499 ST0 = floatx80_chs(ST0);
502 void helper_fabs_ST0(CPUX86State *env)
504 ST0 = floatx80_abs(ST0);
507 void helper_fld1_ST0(CPUX86State *env)
512 void helper_fldl2t_ST0(CPUX86State *env)
517 void helper_fldl2e_ST0(CPUX86State *env)
522 void helper_fldpi_ST0(CPUX86State *env)
527 void helper_fldlg2_ST0(CPUX86State *env)
532 void helper_fldln2_ST0(CPUX86State *env)
537 void helper_fldz_ST0(CPUX86State *env)
542 void helper_fldz_FT0(CPUX86State *env)
547 uint32_t helper_fnstsw(CPUX86State *env)
549 return (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
552 uint32_t helper_fnstcw(CPUX86State *env)
557 void update_fp_status(CPUX86State *env)
561 /* set rounding mode */
562 switch (env->fpuc & FPU_RC_MASK) {
565 rnd_type = float_round_nearest_even;
568 rnd_type = float_round_down;
571 rnd_type = float_round_up;
574 rnd_type = float_round_to_zero;
577 set_float_rounding_mode(rnd_type, &env->fp_status);
578 switch ((env->fpuc >> 8) & 3) {
590 set_floatx80_rounding_precision(rnd_type, &env->fp_status);
593 void helper_fldcw(CPUX86State *env, uint32_t val)
595 cpu_set_fpuc(env, val);
598 void helper_fclex(CPUX86State *env)
603 void helper_fwait(CPUX86State *env)
605 if (env->fpus & FPUS_SE) {
606 fpu_raise_exception(env);
610 void helper_fninit(CPUX86State *env)
614 cpu_set_fpuc(env, 0x37f);
627 void helper_fbld_ST0(CPUX86State *env, target_ulong ptr)
635 for (i = 8; i >= 0; i--) {
636 v = cpu_ldub_data(env, ptr + i);
637 val = (val * 100) + ((v >> 4) * 10) + (v & 0xf);
639 tmp = int64_to_floatx80(val, &env->fp_status);
640 if (cpu_ldub_data(env, ptr + 9) & 0x80) {
641 tmp = floatx80_chs(tmp);
647 void helper_fbst_ST0(CPUX86State *env, target_ulong ptr)
650 target_ulong mem_ref, mem_end;
653 val = floatx80_to_int64(ST0, &env->fp_status);
655 mem_end = mem_ref + 9;
657 cpu_stb_data(env, mem_end, 0x80);
660 cpu_stb_data(env, mem_end, 0x00);
662 while (mem_ref < mem_end) {
668 v = ((v / 10) << 4) | (v % 10);
669 cpu_stb_data(env, mem_ref++, v);
671 while (mem_ref < mem_end) {
672 cpu_stb_data(env, mem_ref++, 0);
676 void helper_f2xm1(CPUX86State *env)
678 double val = floatx80_to_double(env, ST0);
680 val = pow(2.0, val) - 1.0;
681 ST0 = double_to_floatx80(env, val);
684 void helper_fyl2x(CPUX86State *env)
686 double fptemp = floatx80_to_double(env, ST0);
689 fptemp = log(fptemp) / log(2.0); /* log2(ST) */
690 fptemp *= floatx80_to_double(env, ST1);
691 ST1 = double_to_floatx80(env, fptemp);
694 env->fpus &= ~0x4700;
699 void helper_fptan(CPUX86State *env)
701 double fptemp = floatx80_to_double(env, ST0);
703 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
706 fptemp = tan(fptemp);
707 ST0 = double_to_floatx80(env, fptemp);
710 env->fpus &= ~0x400; /* C2 <-- 0 */
711 /* the above code is for |arg| < 2**52 only */
715 void helper_fpatan(CPUX86State *env)
717 double fptemp, fpsrcop;
719 fpsrcop = floatx80_to_double(env, ST1);
720 fptemp = floatx80_to_double(env, ST0);
721 ST1 = double_to_floatx80(env, atan2(fpsrcop, fptemp));
725 void helper_fxtract(CPUX86State *env)
731 if (floatx80_is_zero(ST0)) {
732 /* Easy way to generate -inf and raising division by 0 exception */
733 ST0 = floatx80_div(floatx80_chs(floatx80_one), floatx80_zero,
740 expdif = EXPD(temp) - EXPBIAS;
741 /* DP exponent bias */
742 ST0 = int32_to_floatx80(expdif, &env->fp_status);
749 void helper_fprem1(CPUX86State *env)
751 double st0, st1, dblq, fpsrcop, fptemp;
752 CPU_LDoubleU fpsrcop1, fptemp1;
754 signed long long int q;
756 st0 = floatx80_to_double(env, ST0);
757 st1 = floatx80_to_double(env, ST1);
759 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
760 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
761 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
769 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
772 /* optimisation? taken from the AMD docs */
773 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
774 /* ST0 is unchanged */
779 dblq = fpsrcop / fptemp;
780 /* round dblq towards nearest integer */
782 st0 = fpsrcop - fptemp * dblq;
784 /* convert dblq to q by truncating towards zero */
786 q = (signed long long int)(-dblq);
788 q = (signed long long int)dblq;
791 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
792 /* (C0,C3,C1) <-- (q2,q1,q0) */
793 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
794 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
795 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
797 env->fpus |= 0x400; /* C2 <-- 1 */
798 fptemp = pow(2.0, expdif - 50);
799 fpsrcop = (st0 / st1) / fptemp;
800 /* fpsrcop = integer obtained by chopping */
801 fpsrcop = (fpsrcop < 0.0) ?
802 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
803 st0 -= (st1 * fpsrcop * fptemp);
805 ST0 = double_to_floatx80(env, st0);
808 void helper_fprem(CPUX86State *env)
810 double st0, st1, dblq, fpsrcop, fptemp;
811 CPU_LDoubleU fpsrcop1, fptemp1;
813 signed long long int q;
815 st0 = floatx80_to_double(env, ST0);
816 st1 = floatx80_to_double(env, ST1);
818 if (isinf(st0) || isnan(st0) || isnan(st1) || (st1 == 0.0)) {
819 ST0 = double_to_floatx80(env, 0.0 / 0.0); /* NaN */
820 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
828 expdif = EXPD(fpsrcop1) - EXPD(fptemp1);
831 /* optimisation? taken from the AMD docs */
832 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
833 /* ST0 is unchanged */
838 dblq = fpsrcop / fptemp; /* ST0 / ST1 */
839 /* round dblq towards zero */
840 dblq = (dblq < 0.0) ? ceil(dblq) : floor(dblq);
841 st0 = fpsrcop - fptemp * dblq; /* fpsrcop is ST0 */
843 /* convert dblq to q by truncating towards zero */
845 q = (signed long long int)(-dblq);
847 q = (signed long long int)dblq;
850 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
851 /* (C0,C3,C1) <-- (q2,q1,q0) */
852 env->fpus |= (q & 0x4) << (8 - 2); /* (C0) <-- q2 */
853 env->fpus |= (q & 0x2) << (14 - 1); /* (C3) <-- q1 */
854 env->fpus |= (q & 0x1) << (9 - 0); /* (C1) <-- q0 */
856 int N = 32 + (expdif % 32); /* as per AMD docs */
858 env->fpus |= 0x400; /* C2 <-- 1 */
859 fptemp = pow(2.0, (double)(expdif - N));
860 fpsrcop = (st0 / st1) / fptemp;
861 /* fpsrcop = integer obtained by chopping */
862 fpsrcop = (fpsrcop < 0.0) ?
863 -(floor(fabs(fpsrcop))) : floor(fpsrcop);
864 st0 -= (st1 * fpsrcop * fptemp);
866 ST0 = double_to_floatx80(env, st0);
869 void helper_fyl2xp1(CPUX86State *env)
871 double fptemp = floatx80_to_double(env, ST0);
873 if ((fptemp + 1.0) > 0.0) {
874 fptemp = log(fptemp + 1.0) / log(2.0); /* log2(ST + 1.0) */
875 fptemp *= floatx80_to_double(env, ST1);
876 ST1 = double_to_floatx80(env, fptemp);
879 env->fpus &= ~0x4700;
884 void helper_fsqrt(CPUX86State *env)
886 if (floatx80_is_neg(ST0)) {
887 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
890 ST0 = floatx80_sqrt(ST0, &env->fp_status);
893 void helper_fsincos(CPUX86State *env)
895 double fptemp = floatx80_to_double(env, ST0);
897 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
900 ST0 = double_to_floatx80(env, sin(fptemp));
902 ST0 = double_to_floatx80(env, cos(fptemp));
903 env->fpus &= ~0x400; /* C2 <-- 0 */
904 /* the above code is for |arg| < 2**63 only */
908 void helper_frndint(CPUX86State *env)
910 ST0 = floatx80_round_to_int(ST0, &env->fp_status);
913 void helper_fscale(CPUX86State *env)
915 if (floatx80_is_any_nan(ST1)) {
918 int n = floatx80_to_int32_round_to_zero(ST1, &env->fp_status);
919 ST0 = floatx80_scalbn(ST0, n, &env->fp_status);
923 void helper_fsin(CPUX86State *env)
925 double fptemp = floatx80_to_double(env, ST0);
927 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
930 ST0 = double_to_floatx80(env, sin(fptemp));
931 env->fpus &= ~0x400; /* C2 <-- 0 */
932 /* the above code is for |arg| < 2**53 only */
936 void helper_fcos(CPUX86State *env)
938 double fptemp = floatx80_to_double(env, ST0);
940 if ((fptemp > MAXTAN) || (fptemp < -MAXTAN)) {
943 ST0 = double_to_floatx80(env, cos(fptemp));
944 env->fpus &= ~0x400; /* C2 <-- 0 */
945 /* the above code is for |arg| < 2**63 only */
949 void helper_fxam_ST0(CPUX86State *env)
956 env->fpus &= ~0x4700; /* (C3,C2,C1,C0) <-- 0000 */
958 env->fpus |= 0x200; /* C1 <-- 1 */
961 /* XXX: test fptags too */
963 if (expdif == MAXEXPD) {
964 if (MANTD(temp) == 0x8000000000000000ULL) {
965 env->fpus |= 0x500; /* Infinity */
967 env->fpus |= 0x100; /* NaN */
969 } else if (expdif == 0) {
970 if (MANTD(temp) == 0) {
971 env->fpus |= 0x4000; /* Zero */
973 env->fpus |= 0x4400; /* Denormal */
980 void helper_fstenv(CPUX86State *env, target_ulong ptr, int data32)
982 int fpus, fptag, exp, i;
986 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
988 for (i = 7; i >= 0; i--) {
990 if (env->fptags[i]) {
993 tmp.d = env->fpregs[i].d;
996 if (exp == 0 && mant == 0) {
999 } else if (exp == 0 || exp == MAXEXPD
1000 || (mant & (1LL << 63)) == 0) {
1001 /* NaNs, infinity, denormal */
1008 cpu_stl_data(env, ptr, env->fpuc);
1009 cpu_stl_data(env, ptr + 4, fpus);
1010 cpu_stl_data(env, ptr + 8, fptag);
1011 cpu_stl_data(env, ptr + 12, 0); /* fpip */
1012 cpu_stl_data(env, ptr + 16, 0); /* fpcs */
1013 cpu_stl_data(env, ptr + 20, 0); /* fpoo */
1014 cpu_stl_data(env, ptr + 24, 0); /* fpos */
1017 cpu_stw_data(env, ptr, env->fpuc);
1018 cpu_stw_data(env, ptr + 2, fpus);
1019 cpu_stw_data(env, ptr + 4, fptag);
1020 cpu_stw_data(env, ptr + 6, 0);
1021 cpu_stw_data(env, ptr + 8, 0);
1022 cpu_stw_data(env, ptr + 10, 0);
1023 cpu_stw_data(env, ptr + 12, 0);
1027 void helper_fldenv(CPUX86State *env, target_ulong ptr, int data32)
1032 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1033 fpus = cpu_lduw_data(env, ptr + 4);
1034 fptag = cpu_lduw_data(env, ptr + 8);
1036 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1037 fpus = cpu_lduw_data(env, ptr + 2);
1038 fptag = cpu_lduw_data(env, ptr + 4);
1040 env->fpstt = (fpus >> 11) & 7;
1041 env->fpus = fpus & ~0x3800;
1042 for (i = 0; i < 8; i++) {
1043 env->fptags[i] = ((fptag & 3) == 3);
1048 void helper_fsave(CPUX86State *env, target_ulong ptr, int data32)
1053 helper_fstenv(env, ptr, data32);
1055 ptr += (14 << data32);
1056 for (i = 0; i < 8; i++) {
1058 helper_fstt(env, tmp, ptr);
1065 cpu_set_fpuc(env, 0x37f);
1076 void helper_frstor(CPUX86State *env, target_ulong ptr, int data32)
1081 helper_fldenv(env, ptr, data32);
1082 ptr += (14 << data32);
1084 for (i = 0; i < 8; i++) {
1085 tmp = helper_fldt(env, ptr);
1091 #if defined(CONFIG_USER_ONLY)
1092 void cpu_x86_fsave(CPUX86State *env, target_ulong ptr, int data32)
1094 helper_fsave(env, ptr, data32);
1097 void cpu_x86_frstor(CPUX86State *env, target_ulong ptr, int data32)
1099 helper_frstor(env, ptr, data32);
1103 void helper_fxsave(CPUX86State *env, target_ulong ptr, int data64)
1105 int fpus, fptag, i, nb_xmm_regs;
1109 /* The operand must be 16 byte aligned */
1111 raise_exception(env, EXCP0D_GPF);
1114 fpus = (env->fpus & ~0x3800) | (env->fpstt & 0x7) << 11;
1116 for (i = 0; i < 8; i++) {
1117 fptag |= (env->fptags[i] << i);
1119 cpu_stw_data(env, ptr, env->fpuc);
1120 cpu_stw_data(env, ptr + 2, fpus);
1121 cpu_stw_data(env, ptr + 4, fptag ^ 0xff);
1122 #ifdef TARGET_X86_64
1124 cpu_stq_data(env, ptr + 0x08, 0); /* rip */
1125 cpu_stq_data(env, ptr + 0x10, 0); /* rdp */
1129 cpu_stl_data(env, ptr + 0x08, 0); /* eip */
1130 cpu_stl_data(env, ptr + 0x0c, 0); /* sel */
1131 cpu_stl_data(env, ptr + 0x10, 0); /* dp */
1132 cpu_stl_data(env, ptr + 0x14, 0); /* sel */
1136 for (i = 0; i < 8; i++) {
1138 helper_fstt(env, tmp, addr);
1142 if (env->cr[4] & CR4_OSFXSR_MASK) {
1143 /* XXX: finish it */
1144 cpu_stl_data(env, ptr + 0x18, env->mxcsr); /* mxcsr */
1145 cpu_stl_data(env, ptr + 0x1c, 0x0000ffff); /* mxcsr_mask */
1146 if (env->hflags & HF_CS64_MASK) {
1152 /* Fast FXSAVE leaves out the XMM registers */
1153 if (!(env->efer & MSR_EFER_FFXSR)
1154 || (env->hflags & HF_CPL_MASK)
1155 || !(env->hflags & HF_LMA_MASK)) {
1156 for (i = 0; i < nb_xmm_regs; i++) {
1157 cpu_stq_data(env, addr, env->xmm_regs[i].XMM_Q(0));
1158 cpu_stq_data(env, addr + 8, env->xmm_regs[i].XMM_Q(1));
1165 void helper_fxrstor(CPUX86State *env, target_ulong ptr, int data64)
1167 int i, fpus, fptag, nb_xmm_regs;
1171 /* The operand must be 16 byte aligned */
1173 raise_exception(env, EXCP0D_GPF);
1176 cpu_set_fpuc(env, cpu_lduw_data(env, ptr));
1177 fpus = cpu_lduw_data(env, ptr + 2);
1178 fptag = cpu_lduw_data(env, ptr + 4);
1179 env->fpstt = (fpus >> 11) & 7;
1180 env->fpus = fpus & ~0x3800;
1182 for (i = 0; i < 8; i++) {
1183 env->fptags[i] = ((fptag >> i) & 1);
1187 for (i = 0; i < 8; i++) {
1188 tmp = helper_fldt(env, addr);
1193 if (env->cr[4] & CR4_OSFXSR_MASK) {
1194 /* XXX: finish it */
1195 cpu_set_mxcsr(env, cpu_ldl_data(env, ptr + 0x18));
1196 /* cpu_ldl_data(env, ptr + 0x1c); */
1197 if (env->hflags & HF_CS64_MASK) {
1203 /* Fast FXRESTORE leaves out the XMM registers */
1204 if (!(env->efer & MSR_EFER_FFXSR)
1205 || (env->hflags & HF_CPL_MASK)
1206 || !(env->hflags & HF_LMA_MASK)) {
1207 for (i = 0; i < nb_xmm_regs; i++) {
1208 env->xmm_regs[i].XMM_Q(0) = cpu_ldq_data(env, addr);
1209 env->xmm_regs[i].XMM_Q(1) = cpu_ldq_data(env, addr + 8);
1216 void cpu_get_fp80(uint64_t *pmant, uint16_t *pexp, floatx80 f)
1221 *pmant = temp.l.lower;
1222 *pexp = temp.l.upper;
1225 floatx80 cpu_set_fp80(uint64_t mant, uint16_t upper)
1229 temp.l.upper = upper;
1230 temp.l.lower = mant;
1235 /* XXX: optimize by storing fptt and fptags in the static cpu state */
1237 #define SSE_DAZ 0x0040
1238 #define SSE_RC_MASK 0x6000
1239 #define SSE_RC_NEAR 0x0000
1240 #define SSE_RC_DOWN 0x2000
1241 #define SSE_RC_UP 0x4000
1242 #define SSE_RC_CHOP 0x6000
1243 #define SSE_FZ 0x8000
1245 void cpu_set_mxcsr(CPUX86State *env, uint32_t mxcsr)
1251 /* set rounding mode */
1252 switch (mxcsr & SSE_RC_MASK) {
1255 rnd_type = float_round_nearest_even;
1258 rnd_type = float_round_down;
1261 rnd_type = float_round_up;
1264 rnd_type = float_round_to_zero;
1267 set_float_rounding_mode(rnd_type, &env->sse_status);
1269 /* set denormals are zero */
1270 set_flush_inputs_to_zero((mxcsr & SSE_DAZ) ? 1 : 0, &env->sse_status);
1272 /* set flush to zero */
1273 set_flush_to_zero((mxcsr & SSE_FZ) ? 1 : 0, &env->fp_status);
1276 void cpu_set_fpuc(CPUX86State *env, uint16_t val)
1279 update_fp_status(env);
1282 void helper_ldmxcsr(CPUX86State *env, uint32_t val)
1284 cpu_set_mxcsr(env, val);
1287 void helper_enter_mmx(CPUX86State *env)
1290 *(uint32_t *)(env->fptags) = 0;
1291 *(uint32_t *)(env->fptags + 4) = 0;
1294 void helper_emms(CPUX86State *env)
1296 /* set to empty state */
1297 *(uint32_t *)(env->fptags) = 0x01010101;
1298 *(uint32_t *)(env->fptags + 4) = 0x01010101;
1302 void helper_movq(CPUX86State *env, void *d, void *s)
1304 *(uint64_t *)d = *(uint64_t *)s;
1308 #include "ops_sse.h"
1311 #include "ops_sse.h"