qemu/target-arm/cpu.c

   1 /*
   2  * QEMU ARM CPU
   3  *
   4  * Copyright (c) 2012 SUSE LINUX Products GmbH
   5  *
   6  * This program is free software; you can redistribute it and/or
   7  * modify it under the terms of the GNU General Public License
   8  * as published by the Free Software Foundation; either version 2
   9  * of the License, or (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, see
  18  * <http://www.gnu.org/licenses/gpl-2.0.html>
  19  */
  20
  21 #include "cpu.h"
  22 #include "internals.h"
  23 #include "qemu-common.h"
  24 #include "hw/qdev-properties.h"
  25 #if !defined(CONFIG_USER_ONLY)
  26 #include "hw/loader.h"
  27 #endif
  28 #include "hw/arm/arm.h"
  29 #include "sysemu/sysemu.h"
  30 #include "sysemu/kvm.h"
  31 #include "kvm_arm.h"
  32
  33 static void arm_cpu_set_pc(CPUState *cs, vaddr value)
  34 {
  35     ARMCPU *cpu = ARM_CPU(cs);
  36
  37     cpu->env.regs[15] = value;
  38 }
  39
  40 static bool arm_cpu_has_work(CPUState *cs)
  41 {
  42     ARMCPU *cpu = ARM_CPU(cs);
  43
  44     return !cpu->powered_off
  45         && cs->interrupt_request &
  46         (CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD
  47          | CPU_INTERRUPT_VFIQ | CPU_INTERRUPT_VIRQ
  48          | CPU_INTERRUPT_EXITTB);
  49 }
  50
  51 static void cp_reg_reset(gpointer key, gpointer value, gpointer opaque)
  52 {
  53     /* Reset a single ARMCPRegInfo register */
  54     ARMCPRegInfo *ri = value;
  55     ARMCPU *cpu = opaque;
  56
  57     if (ri->type & (ARM_CP_SPECIAL | ARM_CP_ALIAS)) {
  58         return;
  59     }
  60
  61     if (ri->resetfn) {
  62         ri->resetfn(&cpu->env, ri);
  63         return;
  64     }
  65
  66     /* A zero offset is never possible as it would be regs[0]
  67      * so we use it to indicate that reset is being handled elsewhere.
  68      * This is basically only used for fields in non-core coprocessors
  69      * (like the pxa2xx ones).
  70      */
  71     if (!ri->fieldoffset) {
  72         return;
  73     }
  74
  75     if (cpreg_field_is_64bit(ri)) {
  76         CPREG_FIELD64(&cpu->env, ri) = ri->resetvalue;
  77     } else {
  78         CPREG_FIELD32(&cpu->env, ri) = ri->resetvalue;
  79     }
  80 }
  81
  82 /* CPUClass::reset() */
  83 static void arm_cpu_reset(CPUState *s)
  84 {
  85     ARMCPU *cpu = ARM_CPU(s);
  86     ARMCPUClass *acc = ARM_CPU_GET_CLASS(cpu);
  87     CPUARMState *env = &cpu->env;
  88
  89     acc->parent_reset(s);
  90
  91     memset(env, 0, offsetof(CPUARMState, features));
  92     g_hash_table_foreach(cpu->cp_regs, cp_reg_reset, cpu);
  93     env->vfp.xregs[ARM_VFP_FPSID] = cpu->reset_fpsid;
  94     env->vfp.xregs[ARM_VFP_MVFR0] = cpu->mvfr0;
  95     env->vfp.xregs[ARM_VFP_MVFR1] = cpu->mvfr1;
  96     env->vfp.xregs[ARM_VFP_MVFR2] = cpu->mvfr2;
  97
  98     cpu->powered_off = cpu->start_powered_off;
  99     s->halted = cpu->start_powered_off;
 100
 101     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 102         env->iwmmxt.cregs[ARM_IWMMXT_wCID] = 0x69051000 | 'Q';
 103     }
 104
 105     if (arm_feature(env, ARM_FEATURE_AARCH64)) {
 106         /* 64 bit CPUs always start in 64 bit mode */
 107         env->aarch64 = 1;
 108 #if defined(CONFIG_USER_ONLY)
 109         env->pstate = PSTATE_MODE_EL0t;
 110         /* Userspace expects access to DC ZVA, CTL_EL0 and the cache ops */
 111         env->cp15.sctlr_el[1] |= SCTLR_UCT | SCTLR_UCI | SCTLR_DZE;
 112         /* and to the FP/Neon instructions */
 113         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 2, 3);
 114 #else
 115         /* Reset into the highest available EL */
 116         if (arm_feature(env, ARM_FEATURE_EL3)) {
 117             env->pstate = PSTATE_MODE_EL3h;
 118         } else if (arm_feature(env, ARM_FEATURE_EL2)) {
 119             env->pstate = PSTATE_MODE_EL2h;
 120         } else {
 121             env->pstate = PSTATE_MODE_EL1h;
 122         }
 123         env->pc = cpu->rvbar;
 124 #endif
 125     } else {
 126 #if defined(CONFIG_USER_ONLY)
 127         /* Userspace expects access to cp10 and cp11 for FP/Neon */
 128         env->cp15.cpacr_el1 = deposit64(env->cp15.cpacr_el1, 20, 4, 0xf);
 129 #endif
 130     }
 131
 132 #if defined(CONFIG_USER_ONLY)
 133     env->uncached_cpsr = ARM_CPU_MODE_USR;
 134     /* For user mode we must enable access to coprocessors */
 135     env->vfp.xregs[ARM_VFP_FPEXC] = 1 << 30;
 136     if (arm_feature(env, ARM_FEATURE_IWMMXT)) {
 137         env->cp15.c15_cpar = 3;
 138     } else if (arm_feature(env, ARM_FEATURE_XSCALE)) {
 139         env->cp15.c15_cpar = 1;
 140     }
 141 #else
 142     /* SVC mode with interrupts disabled.  */
 143     env->uncached_cpsr = ARM_CPU_MODE_SVC;
 144     env->daif = PSTATE_D | PSTATE_A | PSTATE_I | PSTATE_F;
 145     /* On ARMv7-M the CPSR_I is the value of the PRIMASK register, and is
 146      * clear at reset. Initial SP and PC are loaded from ROM.
 147      */
 148     if (IS_M(env)) {
 149         uint32_t initial_msp; /* Loaded from 0x0 */
 150         uint32_t initial_pc; /* Loaded from 0x4 */
 151         uint8_t *rom;
 152
 153         env->daif &= ~PSTATE_I;
 154         rom = rom_ptr(0);
 155         if (rom) {
 156             /* Address zero is covered by ROM which hasn't yet been
 157              * copied into physical memory.
 158              */
 159             initial_msp = ldl_p(rom);
 160             initial_pc = ldl_p(rom + 4);
 161         } else {
 162             /* Address zero not covered by a ROM blob, or the ROM blob
 163              * is in non-modifiable memory and this is a second reset after
 164              * it got copied into memory. In the latter case, rom_ptr
 165              * will return a NULL pointer and we should use ldl_phys instead.
 166              */
 167             initial_msp = ldl_phys(s->as, 0);
 168             initial_pc = ldl_phys(s->as, 4);
 169         }
 170
 171         env->regs[13] = initial_msp & 0xFFFFFFFC;
 172         env->regs[15] = initial_pc & ~1;
 173         env->thumb = initial_pc & 1;
 174     }
 175
 176     /* AArch32 has a hard highvec setting of 0xFFFF0000.  If we are currently
 177      * executing as AArch32 then check if highvecs are enabled and
 178      * adjust the PC accordingly.
 179      */
 180     if (A32_BANKED_CURRENT_REG_GET(env, sctlr) & SCTLR_V) {
 181         env->regs[15] = 0xFFFF0000;
 182     }
 183
 184     env->vfp.xregs[ARM_VFP_FPEXC] = 0;
 185 #endif
 186     set_flush_to_zero(1, &env->vfp.standard_fp_status);
 187     set_flush_inputs_to_zero(1, &env->vfp.standard_fp_status);
 188     set_default_nan_mode(1, &env->vfp.standard_fp_status);
 189     set_float_detect_tininess(float_tininess_before_rounding,
 190                               &env->vfp.fp_status);
 191     set_float_detect_tininess(float_tininess_before_rounding,
 192                               &env->vfp.standard_fp_status);
 193     tlb_flush(s, 1);
 194
 195 #ifndef CONFIG_USER_ONLY
 196     if (kvm_enabled()) {
 197         kvm_arm_reset_vcpu(cpu);
 198     }
 199 #endif
 200
 201     hw_breakpoint_update_all(cpu);
 202     hw_watchpoint_update_all(cpu);
 203 }
 204
 205 bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 206 {
 207     CPUClass *cc = CPU_GET_CLASS(cs);
 208     CPUARMState *env = cs->env_ptr;
 209     uint32_t cur_el = arm_current_el(env);
 210     bool secure = arm_is_secure(env);
 211     uint32_t target_el;
 212     uint32_t excp_idx;
 213     bool ret = false;
 214
 215     if (interrupt_request & CPU_INTERRUPT_FIQ) {
 216         excp_idx = EXCP_FIQ;
 217         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 218         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 219             cs->exception_index = excp_idx;
 220             env->exception.target_el = target_el;
 221             cc->do_interrupt(cs);
 222             ret = true;
 223         }
 224     }
 225     if (interrupt_request & CPU_INTERRUPT_HARD) {
 226         excp_idx = EXCP_IRQ;
 227         target_el = arm_phys_excp_target_el(cs, excp_idx, cur_el, secure);
 228         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 229             cs->exception_index = excp_idx;
 230             env->exception.target_el = target_el;
 231             cc->do_interrupt(cs);
 232             ret = true;
 233         }
 234     }
 235     if (interrupt_request & CPU_INTERRUPT_VIRQ) {
 236         excp_idx = EXCP_VIRQ;
 237         target_el = 1;
 238         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 239             cs->exception_index = excp_idx;
 240             env->exception.target_el = target_el;
 241             cc->do_interrupt(cs);
 242             ret = true;
 243         }
 244     }
 245     if (interrupt_request & CPU_INTERRUPT_VFIQ) {
 246         excp_idx = EXCP_VFIQ;
 247         target_el = 1;
 248         if (arm_excp_unmasked(cs, excp_idx, target_el)) {
 249             cs->exception_index = excp_idx;
 250             env->exception.target_el = target_el;
 251             cc->do_interrupt(cs);
 252             ret = true;
 253         }
 254     }
 255
 256     return ret;
 257 }
 258
 259 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 260 static bool arm_v7m_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
 261 {
 262     CPUClass *cc = CPU_GET_CLASS(cs);
 263     ARMCPU *cpu = ARM_CPU(cs);
 264     CPUARMState *env = &cpu->env;
 265     bool ret = false;
 266
 267
 268     if (interrupt_request & CPU_INTERRUPT_FIQ
 269         && !(env->daif & PSTATE_F)) {
 270         cs->exception_index = EXCP_FIQ;
 271         cc->do_interrupt(cs);
 272         ret = true;
 273     }
 274     /* ARMv7-M interrupt return works by loading a magic value
 275      * into the PC.  On real hardware the load causes the
 276      * return to occur.  The qemu implementation performs the
 277      * jump normally, then does the exception return when the
 278      * CPU tries to execute code at the magic address.
 279      * This will cause the magic PC value to be pushed to
 280      * the stack if an interrupt occurred at the wrong time.
 281      * We avoid this by disabling interrupts when
 282      * pc contains a magic address.
 283      */
 284     if (interrupt_request & CPU_INTERRUPT_HARD
 285         && !(env->daif & PSTATE_I)
 286         && (env->regs[15] < 0xfffffff0)) {
 287         cs->exception_index = EXCP_IRQ;
 288         cc->do_interrupt(cs);
 289         ret = true;
 290     }
 291     return ret;
 292 }
 293 #endif
 294
 295 #ifndef CONFIG_USER_ONLY
 296 static void arm_cpu_set_irq(void *opaque, int irq, int level)
 297 {
 298     ARMCPU *cpu = opaque;
 299     CPUARMState *env = &cpu->env;
 300     CPUState *cs = CPU(cpu);
 301     static const int mask[] = {
 302         [ARM_CPU_IRQ] = CPU_INTERRUPT_HARD,
 303         [ARM_CPU_FIQ] = CPU_INTERRUPT_FIQ,
 304         [ARM_CPU_VIRQ] = CPU_INTERRUPT_VIRQ,
 305         [ARM_CPU_VFIQ] = CPU_INTERRUPT_VFIQ
 306     };
 307
 308     switch (irq) {
 309     case ARM_CPU_VIRQ:
 310     case ARM_CPU_VFIQ:
 311         if (!arm_feature(env, ARM_FEATURE_EL2)) {
 312             hw_error("%s: Virtual interrupt line %d with no EL2 support\n",
 313                      __func__, irq);
 314         }
 315         /* fall through */
 316     case ARM_CPU_IRQ:
 317     case ARM_CPU_FIQ:
 318         if (level) {
 319             cpu_interrupt(cs, mask[irq]);
 320         } else {
 321             cpu_reset_interrupt(cs, mask[irq]);
 322         }
 323         break;
 324     default:
 325         hw_error("arm_cpu_set_irq: Bad interrupt line %d\n", irq);
 326     }
 327 }
 328
 329 static void arm_cpu_kvm_set_irq(void *opaque, int irq, int level)
 330 {
 331 #ifdef CONFIG_KVM
 332     ARMCPU *cpu = opaque;
 333     CPUState *cs = CPU(cpu);
 334     int kvm_irq = KVM_ARM_IRQ_TYPE_CPU << KVM_ARM_IRQ_TYPE_SHIFT;
 335
 336     switch (irq) {
 337     case ARM_CPU_IRQ:
 338         kvm_irq |= KVM_ARM_IRQ_CPU_IRQ;
 339         break;
 340     case ARM_CPU_FIQ:
 341         kvm_irq |= KVM_ARM_IRQ_CPU_FIQ;
 342         break;
 343     default:
 344         hw_error("arm_cpu_kvm_set_irq: Bad interrupt line %d\n", irq);
 345     }
 346     kvm_irq |= cs->cpu_index << KVM_ARM_IRQ_VCPU_SHIFT;
 347     kvm_set_irq(kvm_state, kvm_irq, level ? 1 : 0);
 348 #endif
 349 }
 350
 351 static bool arm_cpu_is_big_endian(CPUState *cs)
 352 {
 353     ARMCPU *cpu = ARM_CPU(cs);
 354     CPUARMState *env = &cpu->env;
 355     int cur_el;
 356
 357     cpu_synchronize_state(cs);
 358
 359     /* In 32bit guest endianness is determined by looking at CPSR's E bit */
 360     if (!is_a64(env)) {
 361         return (env->uncached_cpsr & CPSR_E) ? 1 : 0;
 362     }
 363
 364     cur_el = arm_current_el(env);
 365
 366     if (cur_el == 0) {
 367         return (env->cp15.sctlr_el[1] & SCTLR_E0E) != 0;
 368     }
 369
 370     return (env->cp15.sctlr_el[cur_el] & SCTLR_EE) != 0;
 371 }
 372
 373 #endif
 374
 375 static inline void set_feature(CPUARMState *env, int feature)
 376 {
 377     env->features |= 1ULL << feature;
 378 }
 379
 380 static inline void unset_feature(CPUARMState *env, int feature)
 381 {
 382     env->features &= ~(1ULL << feature);
 383 }
 384
 385 static int
 386 print_insn_thumb1(bfd_vma pc, disassemble_info *info)
 387 {
 388   return print_insn_arm(pc | 1, info);
 389 }
 390
 391 static void arm_disas_set_info(CPUState *cpu, disassemble_info *info)
 392 {
 393     ARMCPU *ac = ARM_CPU(cpu);
 394     CPUARMState *env = &ac->env;
 395
 396     if (is_a64(env)) {
 397         /* We might not be compiled with the A64 disassembler
 398          * because it needs a C++ compiler. Leave print_insn
 399          * unset in this case to use the caller default behaviour.
 400          */
 401 #if defined(CONFIG_ARM_A64_DIS)
 402         info->print_insn = print_insn_arm_a64;
 403 #endif
 404     } else if (env->thumb) {
 405         info->print_insn = print_insn_thumb1;
 406     } else {
 407         info->print_insn = print_insn_arm;
 408     }
 409     if (env->bswap_code) {
 410 #ifdef TARGET_WORDS_BIGENDIAN
 411         info->endian = BFD_ENDIAN_LITTLE;
 412 #else
 413         info->endian = BFD_ENDIAN_BIG;
 414 #endif
 415     }
 416 }
 417
 418 #define ARM_CPUS_PER_CLUSTER 8
 419
 420 static void arm_cpu_initfn(Object *obj)
 421 {
 422     CPUState *cs = CPU(obj);
 423     ARMCPU *cpu = ARM_CPU(obj);
 424     static bool inited;
 425     uint32_t Aff1, Aff0;
 426
 427     cs->env_ptr = &cpu->env;
 428     cpu_exec_init(cs, &error_abort);
 429     cpu->cp_regs = g_hash_table_new_full(g_int_hash, g_int_equal,
 430                                          g_free, g_free);
 431
 432     /* This cpu-id-to-MPIDR affinity is used only for TCG; KVM will override it.
 433      * We don't support setting cluster ID ([16..23]) (known as Aff2
 434      * in later ARM ARM versions), or any of the higher affinity level fields,
 435      * so these bits always RAZ.
 436      */
 437     Aff1 = cs->cpu_index / ARM_CPUS_PER_CLUSTER;
 438     Aff0 = cs->cpu_index % ARM_CPUS_PER_CLUSTER;
 439     cpu->mp_affinity = (Aff1 << 8) | Aff0;
 440
 441 #ifndef CONFIG_USER_ONLY
 442     /* Our inbound IRQ and FIQ lines */
 443     if (kvm_enabled()) {
 444         /* VIRQ and VFIQ are unused with KVM but we add them to maintain
 445          * the same interface as non-KVM CPUs.
 446          */
 447         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_kvm_set_irq, 4);
 448     } else {
 449         qdev_init_gpio_in(DEVICE(cpu), arm_cpu_set_irq, 4);
 450     }
 451
 452     cpu->gt_timer[GTIMER_PHYS] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 453                                                 arm_gt_ptimer_cb, cpu);
 454     cpu->gt_timer[GTIMER_VIRT] = timer_new(QEMU_CLOCK_VIRTUAL, GTIMER_SCALE,
 455                                                 arm_gt_vtimer_cb, cpu);
 456     qdev_init_gpio_out(DEVICE(cpu), cpu->gt_timer_outputs,
 457                        ARRAY_SIZE(cpu->gt_timer_outputs));
 458 #endif
 459
 460     /* DTB consumers generally don't in fact care what the 'compatible'
 461      * string is, so always provide some string and trust that a hypothetical
 462      * picky DTB consumer will also provide a helpful error message.
 463      */
 464     cpu->dtb_compatible = "qemu,unknown";
 465     cpu->psci_version = 1; /* By default assume PSCI v0.1 */
 466     cpu->kvm_target = QEMU_KVM_ARM_TARGET_NONE;
 467
 468     if (tcg_enabled()) {
 469         cpu->psci_version = 2; /* TCG implements PSCI 0.2 */
 470         if (!inited) {
 471             inited = true;
 472             arm_translate_init();
 473         }
 474     }
 475 }
 476
 477 static Property arm_cpu_reset_cbar_property =
 478             DEFINE_PROP_UINT64("reset-cbar", ARMCPU, reset_cbar, 0);
 479
 480 static Property arm_cpu_reset_hivecs_property =
 481             DEFINE_PROP_BOOL("reset-hivecs", ARMCPU, reset_hivecs, false);
 482
 483 static Property arm_cpu_rvbar_property =
 484             DEFINE_PROP_UINT64("rvbar", ARMCPU, rvbar, 0);
 485
 486 static Property arm_cpu_has_el3_property =
 487             DEFINE_PROP_BOOL("has_el3", ARMCPU, has_el3, true);
 488
 489 static Property arm_cpu_has_mpu_property =
 490             DEFINE_PROP_BOOL("has-mpu", ARMCPU, has_mpu, true);
 491
 492 static Property arm_cpu_pmsav7_dregion_property =
 493             DEFINE_PROP_UINT32("pmsav7-dregion", ARMCPU, pmsav7_dregion, 16);
 494
 495 static void arm_cpu_post_init(Object *obj)
 496 {
 497     ARMCPU *cpu = ARM_CPU(obj);
 498
 499     if (arm_feature(&cpu->env, ARM_FEATURE_CBAR) ||
 500         arm_feature(&cpu->env, ARM_FEATURE_CBAR_RO)) {
 501         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_cbar_property,
 502                                  &error_abort);
 503     }
 504
 505     if (!arm_feature(&cpu->env, ARM_FEATURE_M)) {
 506         qdev_property_add_static(DEVICE(obj), &arm_cpu_reset_hivecs_property,
 507                                  &error_abort);
 508     }
 509
 510     if (arm_feature(&cpu->env, ARM_FEATURE_AARCH64)) {
 511         qdev_property_add_static(DEVICE(obj), &arm_cpu_rvbar_property,
 512                                  &error_abort);
 513     }
 514
 515     if (arm_feature(&cpu->env, ARM_FEATURE_EL3)) {
 516         /* Add the has_el3 state CPU property only if EL3 is allowed.  This will
 517          * prevent "has_el3" from existing on CPUs which cannot support EL3.
 518          */
 519         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_el3_property,
 520                                  &error_abort);
 521     }
 522
 523     if (arm_feature(&cpu->env, ARM_FEATURE_MPU)) {
 524         qdev_property_add_static(DEVICE(obj), &arm_cpu_has_mpu_property,
 525                                  &error_abort);
 526         if (arm_feature(&cpu->env, ARM_FEATURE_V7)) {
 527             qdev_property_add_static(DEVICE(obj),
 528                                      &arm_cpu_pmsav7_dregion_property,
 529                                      &error_abort);
 530         }
 531     }
 532
 533 }
 534
 535 static void arm_cpu_finalizefn(Object *obj)
 536 {
 537     ARMCPU *cpu = ARM_CPU(obj);
 538     g_hash_table_destroy(cpu->cp_regs);
 539 }
 540
 541 static void arm_cpu_realizefn(DeviceState *dev, Error **errp)
 542 {
 543     CPUState *cs = CPU(dev);
 544     ARMCPU *cpu = ARM_CPU(dev);
 545     ARMCPUClass *acc = ARM_CPU_GET_CLASS(dev);
 546     CPUARMState *env = &cpu->env;
 547
 548     /* Some features automatically imply others: */
 549     if (arm_feature(env, ARM_FEATURE_V8)) {
 550         set_feature(env, ARM_FEATURE_V7);
 551         set_feature(env, ARM_FEATURE_ARM_DIV);
 552         set_feature(env, ARM_FEATURE_LPAE);
 553     }
 554     if (arm_feature(env, ARM_FEATURE_V7)) {
 555         set_feature(env, ARM_FEATURE_VAPA);
 556         set_feature(env, ARM_FEATURE_THUMB2);
 557         set_feature(env, ARM_FEATURE_MPIDR);
 558         if (!arm_feature(env, ARM_FEATURE_M)) {
 559             set_feature(env, ARM_FEATURE_V6K);
 560         } else {
 561             set_feature(env, ARM_FEATURE_V6);
 562         }
 563     }
 564     if (arm_feature(env, ARM_FEATURE_V6K)) {
 565         set_feature(env, ARM_FEATURE_V6);
 566         set_feature(env, ARM_FEATURE_MVFR);
 567     }
 568     if (arm_feature(env, ARM_FEATURE_V6)) {
 569         set_feature(env, ARM_FEATURE_V5);
 570         if (!arm_feature(env, ARM_FEATURE_M)) {
 571             set_feature(env, ARM_FEATURE_AUXCR);
 572         }
 573     }
 574     if (arm_feature(env, ARM_FEATURE_V5)) {
 575         set_feature(env, ARM_FEATURE_V4T);
 576     }
 577     if (arm_feature(env, ARM_FEATURE_M)) {
 578         set_feature(env, ARM_FEATURE_THUMB_DIV);
 579     }
 580     if (arm_feature(env, ARM_FEATURE_ARM_DIV)) {
 581         set_feature(env, ARM_FEATURE_THUMB_DIV);
 582     }
 583     if (arm_feature(env, ARM_FEATURE_VFP4)) {
 584         set_feature(env, ARM_FEATURE_VFP3);
 585         set_feature(env, ARM_FEATURE_VFP_FP16);
 586     }
 587     if (arm_feature(env, ARM_FEATURE_VFP3)) {
 588         set_feature(env, ARM_FEATURE_VFP);
 589     }
 590     if (arm_feature(env, ARM_FEATURE_LPAE)) {
 591         set_feature(env, ARM_FEATURE_V7MP);
 592         set_feature(env, ARM_FEATURE_PXN);
 593     }
 594     if (arm_feature(env, ARM_FEATURE_CBAR_RO)) {
 595         set_feature(env, ARM_FEATURE_CBAR);
 596     }
 597     if (arm_feature(env, ARM_FEATURE_THUMB2) &&
 598         !arm_feature(env, ARM_FEATURE_M)) {
 599         set_feature(env, ARM_FEATURE_THUMB_DSP);
 600     }
 601
 602     if (cpu->reset_hivecs) {
 603             cpu->reset_sctlr |= (1 << 13);
 604     }
 605
 606     if (!cpu->has_el3) {
 607         /* If the has_el3 CPU property is disabled then we need to disable the
 608          * feature.
 609          */
 610         unset_feature(env, ARM_FEATURE_EL3);
 611
 612         /* Disable the security extension feature bits in the processor feature
 613          * registers as well. These are id_pfr1[7:4] and id_aa64pfr0[15:12].
 614          */
 615         cpu->id_pfr1 &= ~0xf0;
 616         cpu->id_aa64pfr0 &= ~0xf000;
 617     }
 618
 619     if (!cpu->has_mpu) {
 620         unset_feature(env, ARM_FEATURE_MPU);
 621     }
 622
 623     if (arm_feature(env, ARM_FEATURE_MPU) &&
 624         arm_feature(env, ARM_FEATURE_V7)) {
 625         uint32_t nr = cpu->pmsav7_dregion;
 626
 627         if (nr > 0xff) {
 628             error_setg(errp, "PMSAv7 MPU #regions invalid %" PRIu32 "\n", nr);
 629             return;
 630         }
 631
 632         if (nr) {
 633             env->pmsav7.drbar = g_new0(uint32_t, nr);
 634             env->pmsav7.drsr = g_new0(uint32_t, nr);
 635             env->pmsav7.dracr = g_new0(uint32_t, nr);
 636         }
 637     }
 638
 639     register_cp_regs_for_features(cpu);
 640     arm_cpu_register_gdb_regs_for_features(cpu);
 641
 642     init_cpreg_list(cpu);
 643
 644     qemu_init_vcpu(cs);
 645     cpu_reset(cs);
 646
 647     acc->parent_realize(dev, errp);
 648 }
 649
 650 static ObjectClass *arm_cpu_class_by_name(const char *cpu_model)
 651 {
 652     ObjectClass *oc;
 653     char *typename;
 654     char **cpuname;
 655
 656     if (!cpu_model) {
 657         return NULL;
 658     }
 659
 660     cpuname = g_strsplit(cpu_model, ",", 1);
 661     typename = g_strdup_printf("%s-" TYPE_ARM_CPU, cpuname[0]);
 662     oc = object_class_by_name(typename);
 663     g_strfreev(cpuname);
 664     g_free(typename);
 665     if (!oc || !object_class_dynamic_cast(oc, TYPE_ARM_CPU) ||
 666         object_class_is_abstract(oc)) {
 667         return NULL;
 668     }
 669     return oc;
 670 }
 671
 672 /* CPU models. These are not needed for the AArch64 linux-user build. */
 673 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
 674
 675 static void arm926_initfn(Object *obj)
 676 {
 677     ARMCPU *cpu = ARM_CPU(obj);
 678
 679     cpu->dtb_compatible = "arm,arm926";
 680     set_feature(&cpu->env, ARM_FEATURE_V5);
 681     set_feature(&cpu->env, ARM_FEATURE_VFP);
 682     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 683     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 684     cpu->midr = 0x41069265;
 685     cpu->reset_fpsid = 0x41011090;
 686     cpu->ctr = 0x1dd20d2;
 687     cpu->reset_sctlr = 0x00090078;
 688 }
 689
 690 static void arm946_initfn(Object *obj)
 691 {
 692     ARMCPU *cpu = ARM_CPU(obj);
 693
 694     cpu->dtb_compatible = "arm,arm946";
 695     set_feature(&cpu->env, ARM_FEATURE_V5);
 696     set_feature(&cpu->env, ARM_FEATURE_MPU);
 697     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 698     cpu->midr = 0x41059461;
 699     cpu->ctr = 0x0f004006;
 700     cpu->reset_sctlr = 0x00000078;
 701 }
 702
 703 static void arm1026_initfn(Object *obj)
 704 {
 705     ARMCPU *cpu = ARM_CPU(obj);
 706
 707     cpu->dtb_compatible = "arm,arm1026";
 708     set_feature(&cpu->env, ARM_FEATURE_V5);
 709     set_feature(&cpu->env, ARM_FEATURE_VFP);
 710     set_feature(&cpu->env, ARM_FEATURE_AUXCR);
 711     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 712     set_feature(&cpu->env, ARM_FEATURE_CACHE_TEST_CLEAN);
 713     cpu->midr = 0x4106a262;
 714     cpu->reset_fpsid = 0x410110a0;
 715     cpu->ctr = 0x1dd20d2;
 716     cpu->reset_sctlr = 0x00090078;
 717     cpu->reset_auxcr = 1;
 718     {
 719         /* The 1026 had an IFAR at c6,c0,0,1 rather than the ARMv6 c6,c0,0,2 */
 720         ARMCPRegInfo ifar = {
 721             .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 1,
 722             .access = PL1_RW,
 723             .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
 724             .resetvalue = 0
 725         };
 726         define_one_arm_cp_reg(cpu, &ifar);
 727     }
 728 }
 729
 730 static void arm1136_r2_initfn(Object *obj)
 731 {
 732     ARMCPU *cpu = ARM_CPU(obj);
 733     /* What qemu calls "arm1136_r2" is actually the 1136 r0p2, ie an
 734      * older core than plain "arm1136". In particular this does not
 735      * have the v6K features.
 736      * These ID register values are correct for 1136 but may be wrong
 737      * for 1136_r2 (in particular r0p2 does not actually implement most
 738      * of the ID registers).
 739      */
 740
 741     cpu->dtb_compatible = "arm,arm1136";
 742     set_feature(&cpu->env, ARM_FEATURE_V6);
 743     set_feature(&cpu->env, ARM_FEATURE_VFP);
 744     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 745     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 746     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 747     cpu->midr = 0x4107b362;
 748     cpu->reset_fpsid = 0x410120b4;
 749     cpu->mvfr0 = 0x11111111;
 750     cpu->mvfr1 = 0x00000000;
 751     cpu->ctr = 0x1dd20d2;
 752     cpu->reset_sctlr = 0x00050078;
 753     cpu->id_pfr0 = 0x111;
 754     cpu->id_pfr1 = 0x1;
 755     cpu->id_dfr0 = 0x2;
 756     cpu->id_afr0 = 0x3;
 757     cpu->id_mmfr0 = 0x01130003;
 758     cpu->id_mmfr1 = 0x10030302;
 759     cpu->id_mmfr2 = 0x01222110;
 760     cpu->id_isar0 = 0x00140011;
 761     cpu->id_isar1 = 0x12002111;
 762     cpu->id_isar2 = 0x11231111;
 763     cpu->id_isar3 = 0x01102131;
 764     cpu->id_isar4 = 0x141;
 765     cpu->reset_auxcr = 7;
 766 }
 767
 768 static void arm1136_initfn(Object *obj)
 769 {
 770     ARMCPU *cpu = ARM_CPU(obj);
 771
 772     cpu->dtb_compatible = "arm,arm1136";
 773     set_feature(&cpu->env, ARM_FEATURE_V6K);
 774     set_feature(&cpu->env, ARM_FEATURE_V6);
 775     set_feature(&cpu->env, ARM_FEATURE_VFP);
 776     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 777     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 778     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 779     cpu->midr = 0x4117b363;
 780     cpu->reset_fpsid = 0x410120b4;
 781     cpu->mvfr0 = 0x11111111;
 782     cpu->mvfr1 = 0x00000000;
 783     cpu->ctr = 0x1dd20d2;
 784     cpu->reset_sctlr = 0x00050078;
 785     cpu->id_pfr0 = 0x111;
 786     cpu->id_pfr1 = 0x1;
 787     cpu->id_dfr0 = 0x2;
 788     cpu->id_afr0 = 0x3;
 789     cpu->id_mmfr0 = 0x01130003;
 790     cpu->id_mmfr1 = 0x10030302;
 791     cpu->id_mmfr2 = 0x01222110;
 792     cpu->id_isar0 = 0x00140011;
 793     cpu->id_isar1 = 0x12002111;
 794     cpu->id_isar2 = 0x11231111;
 795     cpu->id_isar3 = 0x01102131;
 796     cpu->id_isar4 = 0x141;
 797     cpu->reset_auxcr = 7;
 798 }
 799
 800 static void arm1176_initfn(Object *obj)
 801 {
 802     ARMCPU *cpu = ARM_CPU(obj);
 803
 804     cpu->dtb_compatible = "arm,arm1176";
 805     set_feature(&cpu->env, ARM_FEATURE_V6K);
 806     set_feature(&cpu->env, ARM_FEATURE_VFP);
 807     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 808     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 809     set_feature(&cpu->env, ARM_FEATURE_CACHE_DIRTY_REG);
 810     set_feature(&cpu->env, ARM_FEATURE_CACHE_BLOCK_OPS);
 811     set_feature(&cpu->env, ARM_FEATURE_EL3);
 812     cpu->midr = 0x410fb767;
 813     cpu->reset_fpsid = 0x410120b5;
 814     cpu->mvfr0 = 0x11111111;
 815     cpu->mvfr1 = 0x00000000;
 816     cpu->ctr = 0x1dd20d2;
 817     cpu->reset_sctlr = 0x00050078;
 818     cpu->id_pfr0 = 0x111;
 819     cpu->id_pfr1 = 0x11;
 820     cpu->id_dfr0 = 0x33;
 821     cpu->id_afr0 = 0;
 822     cpu->id_mmfr0 = 0x01130003;
 823     cpu->id_mmfr1 = 0x10030302;
 824     cpu->id_mmfr2 = 0x01222100;
 825     cpu->id_isar0 = 0x0140011;
 826     cpu->id_isar1 = 0x12002111;
 827     cpu->id_isar2 = 0x11231121;
 828     cpu->id_isar3 = 0x01102131;
 829     cpu->id_isar4 = 0x01141;
 830     cpu->reset_auxcr = 7;
 831 }
 832
 833 static void arm11mpcore_initfn(Object *obj)
 834 {
 835     ARMCPU *cpu = ARM_CPU(obj);
 836
 837     cpu->dtb_compatible = "arm,arm11mpcore";
 838     set_feature(&cpu->env, ARM_FEATURE_V6K);
 839     set_feature(&cpu->env, ARM_FEATURE_VFP);
 840     set_feature(&cpu->env, ARM_FEATURE_VAPA);
 841     set_feature(&cpu->env, ARM_FEATURE_MPIDR);
 842     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 843     cpu->midr = 0x410fb022;
 844     cpu->reset_fpsid = 0x410120b4;
 845     cpu->mvfr0 = 0x11111111;
 846     cpu->mvfr1 = 0x00000000;
 847     cpu->ctr = 0x1d192992; /* 32K icache 32K dcache */
 848     cpu->id_pfr0 = 0x111;
 849     cpu->id_pfr1 = 0x1;
 850     cpu->id_dfr0 = 0;
 851     cpu->id_afr0 = 0x2;
 852     cpu->id_mmfr0 = 0x01100103;
 853     cpu->id_mmfr1 = 0x10020302;
 854     cpu->id_mmfr2 = 0x01222000;
 855     cpu->id_isar0 = 0x00100011;
 856     cpu->id_isar1 = 0x12002111;
 857     cpu->id_isar2 = 0x11221011;
 858     cpu->id_isar3 = 0x01102131;
 859     cpu->id_isar4 = 0x141;
 860     cpu->reset_auxcr = 1;
 861 }
 862
 863 static void cortex_m3_initfn(Object *obj)
 864 {
 865     ARMCPU *cpu = ARM_CPU(obj);
 866     set_feature(&cpu->env, ARM_FEATURE_V7);
 867     set_feature(&cpu->env, ARM_FEATURE_M);
 868     cpu->midr = 0x410fc231;
 869 }
 870
 871 static void cortex_m4_initfn(Object *obj)
 872 {
 873     ARMCPU *cpu = ARM_CPU(obj);
 874
 875     set_feature(&cpu->env, ARM_FEATURE_V7);
 876     set_feature(&cpu->env, ARM_FEATURE_M);
 877     set_feature(&cpu->env, ARM_FEATURE_THUMB_DSP);
 878     cpu->midr = 0x410fc240; /* r0p0 */
 879 }
 880 static void arm_v7m_class_init(ObjectClass *oc, void *data)
 881 {
 882     CPUClass *cc = CPU_CLASS(oc);
 883
 884 #ifndef CONFIG_USER_ONLY
 885     cc->do_interrupt = arm_v7m_cpu_do_interrupt;
 886 #endif
 887
 888     cc->cpu_exec_interrupt = arm_v7m_cpu_exec_interrupt;
 889 }
 890
 891 static const ARMCPRegInfo cortexr5_cp_reginfo[] = {
 892     /* Dummy the TCM region regs for the moment */
 893     { .name = "ATCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 0,
 894       .access = PL1_RW, .type = ARM_CP_CONST },
 895     { .name = "BTCM", .cp = 15, .opc1 = 0, .crn = 9, .crm = 1, .opc2 = 1,
 896       .access = PL1_RW, .type = ARM_CP_CONST },
 897     REGINFO_SENTINEL
 898 };
 899
 900 static void cortex_r5_initfn(Object *obj)
 901 {
 902     ARMCPU *cpu = ARM_CPU(obj);
 903
 904     set_feature(&cpu->env, ARM_FEATURE_V7);
 905     set_feature(&cpu->env, ARM_FEATURE_THUMB_DIV);
 906     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
 907     set_feature(&cpu->env, ARM_FEATURE_V7MP);
 908     set_feature(&cpu->env, ARM_FEATURE_MPU);
 909     cpu->midr = 0x411fc153; /* r1p3 */
 910     cpu->id_pfr0 = 0x0131;
 911     cpu->id_pfr1 = 0x001;
 912     cpu->id_dfr0 = 0x010400;
 913     cpu->id_afr0 = 0x0;
 914     cpu->id_mmfr0 = 0x0210030;
 915     cpu->id_mmfr1 = 0x00000000;
 916     cpu->id_mmfr2 = 0x01200000;
 917     cpu->id_mmfr3 = 0x0211;
 918     cpu->id_isar0 = 0x2101111;
 919     cpu->id_isar1 = 0x13112111;
 920     cpu->id_isar2 = 0x21232141;
 921     cpu->id_isar3 = 0x01112131;
 922     cpu->id_isar4 = 0x0010142;
 923     cpu->id_isar5 = 0x0;
 924     cpu->mp_is_up = true;
 925     define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
 926 }
 927
 928 static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
 929     { .name = "L2LOCKDOWN", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 0,
 930       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 931     { .name = "L2AUXCR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
 932       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
 933     REGINFO_SENTINEL
 934 };
 935
 936 static void cortex_a8_initfn(Object *obj)
 937 {
 938     ARMCPU *cpu = ARM_CPU(obj);
 939
 940     cpu->dtb_compatible = "arm,cortex-a8";
 941     set_feature(&cpu->env, ARM_FEATURE_V7);
 942     set_feature(&cpu->env, ARM_FEATURE_VFP3);
 943     set_feature(&cpu->env, ARM_FEATURE_NEON);
 944     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
 945     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
 946     set_feature(&cpu->env, ARM_FEATURE_EL3);
 947     cpu->midr = 0x410fc080;
 948     cpu->reset_fpsid = 0x410330c0;
 949     cpu->mvfr0 = 0x11110222;
 950     cpu->mvfr1 = 0x00011100;
 951     cpu->ctr = 0x82048004;
 952     cpu->reset_sctlr = 0x00c50078;
 953     cpu->id_pfr0 = 0x1031;
 954     cpu->id_pfr1 = 0x11;
 955     cpu->id_dfr0 = 0x400;
 956     cpu->id_afr0 = 0;
 957     cpu->id_mmfr0 = 0x31100003;
 958     cpu->id_mmfr1 = 0x20000000;
 959     cpu->id_mmfr2 = 0x01202000;
 960     cpu->id_mmfr3 = 0x11;
 961     cpu->id_isar0 = 0x00101111;
 962     cpu->id_isar1 = 0x12112111;
 963     cpu->id_isar2 = 0x21232031;
 964     cpu->id_isar3 = 0x11112131;
 965     cpu->id_isar4 = 0x00111142;
 966     cpu->dbgdidr = 0x15141000;
 967     cpu->clidr = (1 << 27) | (2 << 24) | 3;
 968     cpu->ccsidr[0] = 0xe007e01a; /* 16k L1 dcache. */
 969     cpu->ccsidr[1] = 0x2007e01a; /* 16k L1 icache. */
 970     cpu->ccsidr[2] = 0xf0000000; /* No L2 icache. */
 971     cpu->reset_auxcr = 2;
 972     define_arm_cp_regs(cpu, cortexa8_cp_reginfo);
 973 }
 974
 975 static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
 976     /* power_control should be set to maximum latency. Again,
 977      * default to 0 and set by private hook
 978      */
 979     { .name = "A9_PWRCTL", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 0,
 980       .access = PL1_RW, .resetvalue = 0,
 981       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_control) },
 982     { .name = "A9_DIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 1,
 983       .access = PL1_RW, .resetvalue = 0,
 984       .fieldoffset = offsetof(CPUARMState, cp15.c15_diagnostic) },
 985     { .name = "A9_PWRDIAG", .cp = 15, .crn = 15, .crm = 0, .opc1 = 0, .opc2 = 2,
 986       .access = PL1_RW, .resetvalue = 0,
 987       .fieldoffset = offsetof(CPUARMState, cp15.c15_power_diagnostic) },
 988     { .name = "NEONBUSY", .cp = 15, .crn = 15, .crm = 1, .opc1 = 0, .opc2 = 0,
 989       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 990     /* TLB lockdown control */
 991     { .name = "TLB_LOCKR", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 2,
 992       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 993     { .name = "TLB_LOCKW", .cp = 15, .crn = 15, .crm = 4, .opc1 = 5, .opc2 = 4,
 994       .access = PL1_W, .resetvalue = 0, .type = ARM_CP_NOP },
 995     { .name = "TLB_VA", .cp = 15, .crn = 15, .crm = 5, .opc1 = 5, .opc2 = 2,
 996       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 997     { .name = "TLB_PA", .cp = 15, .crn = 15, .crm = 6, .opc1 = 5, .opc2 = 2,
 998       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
 999     { .name = "TLB_ATTR", .cp = 15, .crn = 15, .crm = 7, .opc1 = 5, .opc2 = 2,
1000       .access = PL1_RW, .resetvalue = 0, .type = ARM_CP_CONST },
1001     REGINFO_SENTINEL
1002 };
1003
1004 static void cortex_a9_initfn(Object *obj)
1005 {
1006     ARMCPU *cpu = ARM_CPU(obj);
1007
1008     cpu->dtb_compatible = "arm,cortex-a9";
1009     set_feature(&cpu->env, ARM_FEATURE_V7);
1010     set_feature(&cpu->env, ARM_FEATURE_VFP3);
1011     set_feature(&cpu->env, ARM_FEATURE_VFP_FP16);
1012     set_feature(&cpu->env, ARM_FEATURE_NEON);
1013     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1014     set_feature(&cpu->env, ARM_FEATURE_EL3);
1015     /* Note that A9 supports the MP extensions even for
1016      * A9UP and single-core A9MP (which are both different
1017      * and valid configurations; we don't model A9UP).
1018      */
1019     set_feature(&cpu->env, ARM_FEATURE_V7MP);
1020     set_feature(&cpu->env, ARM_FEATURE_CBAR);
1021     cpu->midr = 0x410fc090;
1022     cpu->reset_fpsid = 0x41033090;
1023     cpu->mvfr0 = 0x11110222;
1024     cpu->mvfr1 = 0x01111111;
1025     cpu->ctr = 0x80038003;
1026     cpu->reset_sctlr = 0x00c50078;
1027     cpu->id_pfr0 = 0x1031;
1028     cpu->id_pfr1 = 0x11;
1029     cpu->id_dfr0 = 0x000;
1030     cpu->id_afr0 = 0;
1031     cpu->id_mmfr0 = 0x00100103;
1032     cpu->id_mmfr1 = 0x20000000;
1033     cpu->id_mmfr2 = 0x01230000;
1034     cpu->id_mmfr3 = 0x00002111;
1035     cpu->id_isar0 = 0x00101111;
1036     cpu->id_isar1 = 0x13112111;
1037     cpu->id_isar2 = 0x21232041;
1038     cpu->id_isar3 = 0x11112131;
1039     cpu->id_isar4 = 0x00111142;
1040     cpu->dbgdidr = 0x35141000;
1041     cpu->clidr = (1 << 27) | (1 << 24) | 3;
1042     cpu->ccsidr[0] = 0xe00fe019; /* 16k L1 dcache. */
1043     cpu->ccsidr[1] = 0x200fe019; /* 16k L1 icache. */
1044     define_arm_cp_regs(cpu, cortexa9_cp_reginfo);
1045 }
1046
1047 #ifndef CONFIG_USER_ONLY
1048 static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
1049 {
1050     /* Linux wants the number of processors from here.
1051      * Might as well set the interrupt-controller bit too.
1052      */
1053     return ((smp_cpus - 1) << 24) | (1 << 23);
1054 }
1055 #endif
1056
1057 static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
1058 #ifndef CONFIG_USER_ONLY
1059     { .name = "L2CTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 2,
1060       .access = PL1_RW, .resetvalue = 0, .readfn = a15_l2ctlr_read,
1061       .writefn = arm_cp_write_ignore, },
1062 #endif
1063     { .name = "L2ECTLR", .cp = 15, .crn = 9, .crm = 0, .opc1 = 1, .opc2 = 3,
1064       .access = PL1_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
1065     REGINFO_SENTINEL
1066 };
1067
1068 static void cortex_a15_initfn(Object *obj)
1069 {
1070     ARMCPU *cpu = ARM_CPU(obj);
1071
1072     cpu->dtb_compatible = "arm,cortex-a15";
1073     set_feature(&cpu->env, ARM_FEATURE_V7);
1074     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1075     set_feature(&cpu->env, ARM_FEATURE_NEON);
1076     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1077     set_feature(&cpu->env, ARM_FEATURE_ARM_DIV);
1078     set_feature(&cpu->env, ARM_FEATURE_GENERIC_TIMER);
1079     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1080     set_feature(&cpu->env, ARM_FEATURE_CBAR_RO);
1081     set_feature(&cpu->env, ARM_FEATURE_LPAE);
1082     set_feature(&cpu->env, ARM_FEATURE_EL3);
1083     cpu->kvm_target = QEMU_KVM_ARM_TARGET_CORTEX_A15;
1084     cpu->midr = 0x412fc0f1;
1085     cpu->reset_fpsid = 0x410430f0;
1086     cpu->mvfr0 = 0x10110222;
1087     cpu->mvfr1 = 0x11111111;
1088     cpu->ctr = 0x8444c004;
1089     cpu->reset_sctlr = 0x00c50078;
1090     cpu->id_pfr0 = 0x00001131;
1091     cpu->id_pfr1 = 0x00011011;
1092     cpu->id_dfr0 = 0x02010555;
1093     cpu->id_afr0 = 0x00000000;
1094     cpu->id_mmfr0 = 0x10201105;
1095     cpu->id_mmfr1 = 0x20000000;
1096     cpu->id_mmfr2 = 0x01240000;
1097     cpu->id_mmfr3 = 0x02102211;
1098     cpu->id_isar0 = 0x02101110;
1099     cpu->id_isar1 = 0x13112111;
1100     cpu->id_isar2 = 0x21232041;
1101     cpu->id_isar3 = 0x11112131;
1102     cpu->id_isar4 = 0x10011142;
1103     cpu->dbgdidr = 0x3515f021;
1104     cpu->clidr = 0x0a200023;
1105     cpu->ccsidr[0] = 0x701fe00a; /* 32K L1 dcache */
1106     cpu->ccsidr[1] = 0x201fe00a; /* 32K L1 icache */
1107     cpu->ccsidr[2] = 0x711fe07a; /* 4096K L2 unified cache */
1108     define_arm_cp_regs(cpu, cortexa15_cp_reginfo);
1109 }
1110
1111 static void ti925t_initfn(Object *obj)
1112 {
1113     ARMCPU *cpu = ARM_CPU(obj);
1114     set_feature(&cpu->env, ARM_FEATURE_V4T);
1115     set_feature(&cpu->env, ARM_FEATURE_OMAPCP);
1116     cpu->midr = ARM_CPUID_TI925T;
1117     cpu->ctr = 0x5109149;
1118     cpu->reset_sctlr = 0x00000070;
1119 }
1120
1121 static void sa1100_initfn(Object *obj)
1122 {
1123     ARMCPU *cpu = ARM_CPU(obj);
1124
1125     cpu->dtb_compatible = "intel,sa1100";
1126     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1127     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1128     cpu->midr = 0x4401A11B;
1129     cpu->reset_sctlr = 0x00000070;
1130 }
1131
1132 static void sa1110_initfn(Object *obj)
1133 {
1134     ARMCPU *cpu = ARM_CPU(obj);
1135     set_feature(&cpu->env, ARM_FEATURE_STRONGARM);
1136     set_feature(&cpu->env, ARM_FEATURE_DUMMY_C15_REGS);
1137     cpu->midr = 0x6901B119;
1138     cpu->reset_sctlr = 0x00000070;
1139 }
1140
1141 static void pxa250_initfn(Object *obj)
1142 {
1143     ARMCPU *cpu = ARM_CPU(obj);
1144
1145     cpu->dtb_compatible = "marvell,xscale";
1146     set_feature(&cpu->env, ARM_FEATURE_V5);
1147     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1148     cpu->midr = 0x69052100;
1149     cpu->ctr = 0xd172172;
1150     cpu->reset_sctlr = 0x00000078;
1151 }
1152
1153 static void pxa255_initfn(Object *obj)
1154 {
1155     ARMCPU *cpu = ARM_CPU(obj);
1156
1157     cpu->dtb_compatible = "marvell,xscale";
1158     set_feature(&cpu->env, ARM_FEATURE_V5);
1159     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1160     cpu->midr = 0x69052d00;
1161     cpu->ctr = 0xd172172;
1162     cpu->reset_sctlr = 0x00000078;
1163 }
1164
1165 static void pxa260_initfn(Object *obj)
1166 {
1167     ARMCPU *cpu = ARM_CPU(obj);
1168
1169     cpu->dtb_compatible = "marvell,xscale";
1170     set_feature(&cpu->env, ARM_FEATURE_V5);
1171     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1172     cpu->midr = 0x69052903;
1173     cpu->ctr = 0xd172172;
1174     cpu->reset_sctlr = 0x00000078;
1175 }
1176
1177 static void pxa261_initfn(Object *obj)
1178 {
1179     ARMCPU *cpu = ARM_CPU(obj);
1180
1181     cpu->dtb_compatible = "marvell,xscale";
1182     set_feature(&cpu->env, ARM_FEATURE_V5);
1183     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1184     cpu->midr = 0x69052d05;
1185     cpu->ctr = 0xd172172;
1186     cpu->reset_sctlr = 0x00000078;
1187 }
1188
1189 static void pxa262_initfn(Object *obj)
1190 {
1191     ARMCPU *cpu = ARM_CPU(obj);
1192
1193     cpu->dtb_compatible = "marvell,xscale";
1194     set_feature(&cpu->env, ARM_FEATURE_V5);
1195     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1196     cpu->midr = 0x69052d06;
1197     cpu->ctr = 0xd172172;
1198     cpu->reset_sctlr = 0x00000078;
1199 }
1200
1201 static void pxa270a0_initfn(Object *obj)
1202 {
1203     ARMCPU *cpu = ARM_CPU(obj);
1204
1205     cpu->dtb_compatible = "marvell,xscale";
1206     set_feature(&cpu->env, ARM_FEATURE_V5);
1207     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1208     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1209     cpu->midr = 0x69054110;
1210     cpu->ctr = 0xd172172;
1211     cpu->reset_sctlr = 0x00000078;
1212 }
1213
1214 static void pxa270a1_initfn(Object *obj)
1215 {
1216     ARMCPU *cpu = ARM_CPU(obj);
1217
1218     cpu->dtb_compatible = "marvell,xscale";
1219     set_feature(&cpu->env, ARM_FEATURE_V5);
1220     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1221     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1222     cpu->midr = 0x69054111;
1223     cpu->ctr = 0xd172172;
1224     cpu->reset_sctlr = 0x00000078;
1225 }
1226
1227 static void pxa270b0_initfn(Object *obj)
1228 {
1229     ARMCPU *cpu = ARM_CPU(obj);
1230
1231     cpu->dtb_compatible = "marvell,xscale";
1232     set_feature(&cpu->env, ARM_FEATURE_V5);
1233     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1234     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1235     cpu->midr = 0x69054112;
1236     cpu->ctr = 0xd172172;
1237     cpu->reset_sctlr = 0x00000078;
1238 }
1239
1240 static void pxa270b1_initfn(Object *obj)
1241 {
1242     ARMCPU *cpu = ARM_CPU(obj);
1243
1244     cpu->dtb_compatible = "marvell,xscale";
1245     set_feature(&cpu->env, ARM_FEATURE_V5);
1246     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1247     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1248     cpu->midr = 0x69054113;
1249     cpu->ctr = 0xd172172;
1250     cpu->reset_sctlr = 0x00000078;
1251 }
1252
1253 static void pxa270c0_initfn(Object *obj)
1254 {
1255     ARMCPU *cpu = ARM_CPU(obj);
1256
1257     cpu->dtb_compatible = "marvell,xscale";
1258     set_feature(&cpu->env, ARM_FEATURE_V5);
1259     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1260     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1261     cpu->midr = 0x69054114;
1262     cpu->ctr = 0xd172172;
1263     cpu->reset_sctlr = 0x00000078;
1264 }
1265
1266 static void pxa270c5_initfn(Object *obj)
1267 {
1268     ARMCPU *cpu = ARM_CPU(obj);
1269
1270     cpu->dtb_compatible = "marvell,xscale";
1271     set_feature(&cpu->env, ARM_FEATURE_V5);
1272     set_feature(&cpu->env, ARM_FEATURE_XSCALE);
1273     set_feature(&cpu->env, ARM_FEATURE_IWMMXT);
1274     cpu->midr = 0x69054117;
1275     cpu->ctr = 0xd172172;
1276     cpu->reset_sctlr = 0x00000078;
1277 }
1278
1279 #ifdef CONFIG_USER_ONLY
1280 static void arm_any_initfn(Object *obj)
1281 {
1282     ARMCPU *cpu = ARM_CPU(obj);
1283     set_feature(&cpu->env, ARM_FEATURE_V8);
1284     set_feature(&cpu->env, ARM_FEATURE_VFP4);
1285     set_feature(&cpu->env, ARM_FEATURE_NEON);
1286     set_feature(&cpu->env, ARM_FEATURE_THUMB2EE);
1287     set_feature(&cpu->env, ARM_FEATURE_V8_AES);
1288     set_feature(&cpu->env, ARM_FEATURE_V8_SHA1);
1289     set_feature(&cpu->env, ARM_FEATURE_V8_SHA256);
1290     set_feature(&cpu->env, ARM_FEATURE_V8_PMULL);
1291     set_feature(&cpu->env, ARM_FEATURE_CRC);
1292     cpu->midr = 0xffffffff;
1293 }
1294 #endif
1295
1296 #endif /* !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64) */
1297
1298 typedef struct ARMCPUInfo {
1299     const char *name;
1300     void (*initfn)(Object *obj);
1301     void (*class_init)(ObjectClass *oc, void *data);
1302 } ARMCPUInfo;
1303
1304 static const ARMCPUInfo arm_cpus[] = {
1305 #if !defined(CONFIG_USER_ONLY) || !defined(TARGET_AARCH64)
1306     { .name = "arm926",      .initfn = arm926_initfn },
1307     { .name = "arm946",      .initfn = arm946_initfn },
1308     { .name = "arm1026",     .initfn = arm1026_initfn },
1309     /* What QEMU calls "arm1136-r2" is actually the 1136 r0p2, i.e. an
1310      * older core than plain "arm1136". In particular this does not
1311      * have the v6K features.
1312      */
1313     { .name = "arm1136-r2",  .initfn = arm1136_r2_initfn },
1314     { .name = "arm1136",     .initfn = arm1136_initfn },
1315     { .name = "arm1176",     .initfn = arm1176_initfn },
1316     { .name = "arm11mpcore", .initfn = arm11mpcore_initfn },
1317     { .name = "cortex-m3",   .initfn = cortex_m3_initfn,
1318                              .class_init = arm_v7m_class_init },
1319     { .name = "cortex-m4",   .initfn = cortex_m4_initfn,
1320                              .class_init = arm_v7m_class_init },
1321     { .name = "cortex-r5",   .initfn = cortex_r5_initfn },
1322     { .name = "cortex-a8",   .initfn = cortex_a8_initfn },
1323     { .name = "cortex-a9",   .initfn = cortex_a9_initfn },
1324     { .name = "cortex-a15",  .initfn = cortex_a15_initfn },
1325     { .name = "ti925t",      .initfn = ti925t_initfn },
1326     { .name = "sa1100",      .initfn = sa1100_initfn },
1327     { .name = "sa1110",      .initfn = sa1110_initfn },
1328     { .name = "pxa250",      .initfn = pxa250_initfn },
1329     { .name = "pxa255",      .initfn = pxa255_initfn },
1330     { .name = "pxa260",      .initfn = pxa260_initfn },
1331     { .name = "pxa261",      .initfn = pxa261_initfn },
1332     { .name = "pxa262",      .initfn = pxa262_initfn },
1333     /* "pxa270" is an alias for "pxa270-a0" */
1334     { .name = "pxa270",      .initfn = pxa270a0_initfn },
1335     { .name = "pxa270-a0",   .initfn = pxa270a0_initfn },
1336     { .name = "pxa270-a1",   .initfn = pxa270a1_initfn },
1337     { .name = "pxa270-b0",   .initfn = pxa270b0_initfn },
1338     { .name = "pxa270-b1",   .initfn = pxa270b1_initfn },
1339     { .name = "pxa270-c0",   .initfn = pxa270c0_initfn },
1340     { .name = "pxa270-c5",   .initfn = pxa270c5_initfn },
1341 #ifdef CONFIG_USER_ONLY
1342     { .name = "any",         .initfn = arm_any_initfn },
1343 #endif
1344 #endif
1345     { .name = NULL }
1346 };
1347
1348 static Property arm_cpu_properties[] = {
1349     DEFINE_PROP_BOOL("start-powered-off", ARMCPU, start_powered_off, false),
1350     DEFINE_PROP_UINT32("psci-conduit", ARMCPU, psci_conduit, 0),
1351     DEFINE_PROP_UINT32("midr", ARMCPU, midr, 0),
1352     DEFINE_PROP_END_OF_LIST()
1353 };
1354
1355 #ifdef CONFIG_USER_ONLY
1356 static int arm_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
1357                                     int mmu_idx)
1358 {
1359     ARMCPU *cpu = ARM_CPU(cs);
1360     CPUARMState *env = &cpu->env;
1361
1362     env->exception.vaddress = address;
1363     if (rw == 2) {
1364         cs->exception_index = EXCP_PREFETCH_ABORT;
1365     } else {
1366         cs->exception_index = EXCP_DATA_ABORT;
1367     }
1368     return 1;
1369 }
1370 #endif
1371
1372 static void arm_cpu_class_init(ObjectClass *oc, void *data)
1373 {
1374     ARMCPUClass *acc = ARM_CPU_CLASS(oc);
1375     CPUClass *cc = CPU_CLASS(acc);
1376     DeviceClass *dc = DEVICE_CLASS(oc);
1377
1378     acc->parent_realize = dc->realize;
1379     dc->realize = arm_cpu_realizefn;
1380     dc->props = arm_cpu_properties;
1381
1382     acc->parent_reset = cc->reset;
1383     cc->reset = arm_cpu_reset;
1384
1385     cc->class_by_name = arm_cpu_class_by_name;
1386     cc->has_work = arm_cpu_has_work;
1387     cc->cpu_exec_interrupt = arm_cpu_exec_interrupt;
1388     cc->dump_state = arm_cpu_dump_state;
1389     cc->set_pc = arm_cpu_set_pc;
1390     cc->gdb_read_register = arm_cpu_gdb_read_register;
1391     cc->gdb_write_register = arm_cpu_gdb_write_register;
1392 #ifdef CONFIG_USER_ONLY
1393     cc->handle_mmu_fault = arm_cpu_handle_mmu_fault;
1394 #else
1395     cc->do_interrupt = arm_cpu_do_interrupt;
1396     cc->get_phys_page_debug = arm_cpu_get_phys_page_debug;
1397     cc->vmsd = &vmstate_arm_cpu;
1398     cc->virtio_is_big_endian = arm_cpu_is_big_endian;
1399 #endif
1400     cc->gdb_num_core_regs = 26;
1401     cc->gdb_core_xml_file = "arm-core.xml";
1402     cc->gdb_stop_before_watchpoint = true;
1403     cc->debug_excp_handler = arm_debug_excp_handler;
1404
1405     cc->disas_set_info = arm_disas_set_info;
1406 }
1407
1408 static void cpu_register(const ARMCPUInfo *info)
1409 {
1410     TypeInfo type_info = {
1411         .parent = TYPE_ARM_CPU,
1412         .instance_size = sizeof(ARMCPU),
1413         .instance_init = info->initfn,
1414         .class_size = sizeof(ARMCPUClass),
1415         .class_init = info->class_init,
1416     };
1417
1418     type_info.name = g_strdup_printf("%s-" TYPE_ARM_CPU, info->name);
1419     type_register(&type_info);
1420     g_free((void *)type_info.name);
1421 }
1422
1423 static const TypeInfo arm_cpu_type_info = {
1424     .name = TYPE_ARM_CPU,
1425     .parent = TYPE_CPU,
1426     .instance_size = sizeof(ARMCPU),
1427     .instance_init = arm_cpu_initfn,
1428     .instance_post_init = arm_cpu_post_init,
1429     .instance_finalize = arm_cpu_finalizefn,
1430     .abstract = true,
1431     .class_size = sizeof(ARMCPUClass),
1432     .class_init = arm_cpu_class_init,
1433 };
1434
1435 static void arm_cpu_register_types(void)
1436 {
1437     const ARMCPUInfo *info = arm_cpus;
1438
1439     type_register_static(&arm_cpu_type_info);
1440
1441     while (info->name) {
1442         cpu_register(info);
1443         info++;
1444     }
1445 }
1446
1447 type_init(arm_cpu_register_types)