qemu/roms/u-boot/drivers/usb/gadget/atmel_usba_udc.h

   1 /*
   2  * Register definition for Atmel USBA high speed USB device controller
   3  * [Original from Linux kernel: drivers/usb/gadget/atmel_usba_udc.h]
   4  *
   5  * Copyright (C) 2005-2013 Atmel Corporation
   6  *                         Bo Shen <voice.shen@atmel.com>
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __LINUX_USB_GADGET_USBA_UDC_H__
  12 #define __LINUX_USB_GADGET_USBA_UDC_H__
  13
  14 /* USB register offsets */
  15 #define USBA_CTRL                               0x0000
  16 #define USBA_FNUM                               0x0004
  17 #define USBA_INT_ENB                            0x0010
  18 #define USBA_INT_STA                            0x0014
  19 #define USBA_INT_CLR                            0x0018
  20 #define USBA_EPT_RST                            0x001c
  21 #define USBA_TST                                0x00e0
  22
  23 /* USB endpoint register offsets */
  24 #define USBA_EPT_CFG                            0x0000
  25 #define USBA_EPT_CTL_ENB                        0x0004
  26 #define USBA_EPT_CTL_DIS                        0x0008
  27 #define USBA_EPT_CTL                            0x000c
  28 #define USBA_EPT_SET_STA                        0x0014
  29 #define USBA_EPT_CLR_STA                        0x0018
  30 #define USBA_EPT_STA                            0x001c
  31
  32 /* USB DMA register offsets */
  33 #define USBA_DMA_NXT_DSC                        0x0000
  34 #define USBA_DMA_ADDRESS                        0x0004
  35 #define USBA_DMA_CONTROL                        0x0008
  36 #define USBA_DMA_STATUS                         0x000c
  37
  38 /* Bitfields in CTRL */
  39 #define USBA_DEV_ADDR_OFFSET                    0
  40 #define USBA_DEV_ADDR_SIZE                      7
  41 #define USBA_FADDR_EN                           (1 <<  7)
  42 #define USBA_EN_USBA                            (1 <<  8)
  43 #define USBA_DETACH                             (1 <<  9)
  44 #define USBA_REMOTE_WAKE_UP                     (1 << 10)
  45 #define USBA_PULLD_DIS                          (1 << 11)
  46
  47 #if defined(CONFIG_AVR32)
  48 #define USBA_ENABLE_MASK                        USBA_EN_USBA
  49 #define USBA_DISABLE_MASK                       0
  50 #elif defined(CONFIG_AT91FAMILY)
  51 #define USBA_ENABLE_MASK                        (USBA_EN_USBA | USBA_PULLD_DIS)
  52 #define USBA_DISABLE_MASK                       USBA_DETACH
  53 #endif /* CONFIG_ARCH_AT91 */
  54
  55 /* Bitfields in FNUM */
  56 #define USBA_MICRO_FRAME_NUM_OFFSET             0
  57 #define USBA_MICRO_FRAME_NUM_SIZE               3
  58 #define USBA_FRAME_NUMBER_OFFSET                3
  59 #define USBA_FRAME_NUMBER_SIZE                  11
  60 #define USBA_FRAME_NUM_ERROR                    (1 << 31)
  61
  62 /* Bitfields in INT_ENB/INT_STA/INT_CLR */
  63 #define USBA_HIGH_SPEED                         (1 <<  0)
  64 #define USBA_DET_SUSPEND                        (1 <<  1)
  65 #define USBA_MICRO_SOF                          (1 <<  2)
  66 #define USBA_SOF                                (1 <<  3)
  67 #define USBA_END_OF_RESET                       (1 <<  4)
  68 #define USBA_WAKE_UP                            (1 <<  5)
  69 #define USBA_END_OF_RESUME                      (1 <<  6)
  70 #define USBA_UPSTREAM_RESUME                    (1 <<  7)
  71 #define USBA_EPT_INT_OFFSET                     8
  72 #define USBA_EPT_INT_SIZE                       16
  73 #define USBA_DMA_INT_OFFSET                     24
  74 #define USBA_DMA_INT_SIZE                       8
  75
  76 /* Bitfields in EPT_RST */
  77 #define USBA_RST_OFFSET                         0
  78 #define USBA_RST_SIZE                           16
  79
  80 /* Bitfields in USBA_TST */
  81 #define USBA_SPEED_CFG_OFFSET                   0
  82 #define USBA_SPEED_CFG_SIZE                     2
  83 #define USBA_TST_J_MODE                         (1 <<  2)
  84 #define USBA_TST_K_MODE                         (1 <<  3)
  85 #define USBA_TST_PKT_MODE                       (1 <<  4)
  86 #define USBA_OPMODE2                            (1 <<  5)
  87
  88 /* Bitfields in EPT_CFG */
  89 #define USBA_EPT_SIZE_OFFSET                    0
  90 #define USBA_EPT_SIZE_SIZE                      3
  91 #define USBA_EPT_DIR_IN                         (1 <<  3)
  92 #define USBA_EPT_TYPE_OFFSET                    4
  93 #define USBA_EPT_TYPE_SIZE                      2
  94 #define USBA_BK_NUMBER_OFFSET                   6
  95 #define USBA_BK_NUMBER_SIZE                     2
  96 #define USBA_NB_TRANS_OFFSET                    8
  97 #define USBA_NB_TRANS_SIZE                      2
  98 #define USBA_EPT_MAPPED                         (1 << 31)
  99
 100 /* Bitfields in EPT_CTL/EPT_CTL_ENB/EPT_CTL_DIS */
 101 #define USBA_EPT_ENABLE                         (1 <<  0)
 102 #define USBA_AUTO_VALID                         (1 <<  1)
 103 #define USBA_INTDIS_DMA                         (1 <<  3)
 104 #define USBA_NYET_DIS                           (1 <<  4)
 105 #define USBA_DATAX_RX                           (1 <<  6)
 106 #define USBA_MDATA_RX                           (1 <<  7)
 107 /* Bits 8-15 and 31 enable interrupts for respective bits in EPT_STA */
 108 #define USBA_BUSY_BANK_IE                       (1 << 18)
 109
 110 /* Bitfields in EPT_SET_STA/EPT_CLR_STA/EPT_STA */
 111 #define USBA_FORCE_STALL                        (1 <<  5)
 112 #define USBA_TOGGLE_CLR                         (1 <<  6)
 113 #define USBA_TOGGLE_SEQ_OFFSET                  6
 114 #define USBA_TOGGLE_SEQ_SIZE                    2
 115 #define USBA_ERR_OVFLW                          (1 <<  8)
 116 #define USBA_RX_BK_RDY                          (1 <<  9)
 117 #define USBA_KILL_BANK                          (1 <<  9)
 118 #define USBA_TX_COMPLETE                        (1 << 10)
 119 #define USBA_TX_PK_RDY                          (1 << 11)
 120 #define USBA_ISO_ERR_TRANS                      (1 << 11)
 121 #define USBA_RX_SETUP                           (1 << 12)
 122 #define USBA_ISO_ERR_FLOW                       (1 << 12)
 123 #define USBA_STALL_SENT                         (1 << 13)
 124 #define USBA_ISO_ERR_CRC                        (1 << 13)
 125 #define USBA_ISO_ERR_NBTRANS                    (1 << 13)
 126 #define USBA_NAK_IN                             (1 << 14)
 127 #define USBA_ISO_ERR_FLUSH                      (1 << 14)
 128 #define USBA_NAK_OUT                            (1 << 15)
 129 #define USBA_CURRENT_BANK_OFFSET                16
 130 #define USBA_CURRENT_BANK_SIZE                  2
 131 #define USBA_BUSY_BANKS_OFFSET                  18
 132 #define USBA_BUSY_BANKS_SIZE                    2
 133 #define USBA_BYTE_COUNT_OFFSET                  20
 134 #define USBA_BYTE_COUNT_SIZE                    11
 135 #define USBA_SHORT_PACKET                       (1 << 31)
 136
 137 /* Bitfields in DMA_CONTROL */
 138 #define USBA_DMA_CH_EN                          (1 <<  0)
 139 #define USBA_DMA_LINK                           (1 <<  1)
 140 #define USBA_DMA_END_TR_EN                      (1 <<  2)
 141 #define USBA_DMA_END_BUF_EN                     (1 <<  3)
 142 #define USBA_DMA_END_TR_IE                      (1 <<  4)
 143 #define USBA_DMA_END_BUF_IE                     (1 <<  5)
 144 #define USBA_DMA_DESC_LOAD_IE                   (1 <<  6)
 145 #define USBA_DMA_BURST_LOCK                     (1 <<  7)
 146 #define USBA_DMA_BUF_LEN_OFFSET                 16
 147 #define USBA_DMA_BUF_LEN_SIZE                   16
 148
 149 /* Bitfields in DMA_STATUS */
 150 #define USBA_DMA_CH_ACTIVE                      (1 <<  1)
 151 #define USBA_DMA_END_TR_ST                      (1 <<  4)
 152 #define USBA_DMA_END_BUF_ST                     (1 <<  5)
 153 #define USBA_DMA_DESC_LOAD_ST                   (1 <<  6)
 154
 155 /* Constants for SPEED_CFG */
 156 #define USBA_SPEED_CFG_NORMAL                   0
 157 #define USBA_SPEED_CFG_FORCE_HIGH               2
 158 #define USBA_SPEED_CFG_FORCE_FULL               3
 159
 160 /* Constants for EPT_SIZE */
 161 #define USBA_EPT_SIZE_8                         0
 162 #define USBA_EPT_SIZE_16                        1
 163 #define USBA_EPT_SIZE_32                        2
 164 #define USBA_EPT_SIZE_64                        3
 165 #define USBA_EPT_SIZE_128                       4
 166 #define USBA_EPT_SIZE_256                       5
 167 #define USBA_EPT_SIZE_512                       6
 168 #define USBA_EPT_SIZE_1024                      7
 169
 170 /* Constants for EPT_TYPE */
 171 #define USBA_EPT_TYPE_CONTROL                   0
 172 #define USBA_EPT_TYPE_ISO                       1
 173 #define USBA_EPT_TYPE_BULK                      2
 174 #define USBA_EPT_TYPE_INT                       3
 175
 176 /* Constants for BK_NUMBER */
 177 #define USBA_BK_NUMBER_ZERO                     0
 178 #define USBA_BK_NUMBER_ONE                      1
 179 #define USBA_BK_NUMBER_DOUBLE                   2
 180 #define USBA_BK_NUMBER_TRIPLE                   3
 181
 182 /* Bit manipulation macros */
 183 #define USBA_BF(name, value)                                    \
 184         (((value) & ((1 << USBA_##name##_SIZE) - 1))            \
 185          << USBA_##name##_OFFSET)
 186 #define USBA_BFEXT(name, value)                                 \
 187         (((value) >> USBA_##name##_OFFSET)                      \
 188          & ((1 << USBA_##name##_SIZE) - 1))
 189 #define USBA_BFINS(name, value, old)                            \
 190         (((old) & ~(((1 << USBA_##name##_SIZE) - 1)             \
 191                     << USBA_##name##_OFFSET))                   \
 192          | USBA_BF(name, value))
 193
 194 /* Register access macros */
 195 #define usba_readl(udc, reg)                                    \
 196         __raw_readl((udc)->regs + USBA_##reg)
 197 #define usba_writel(udc, reg, value)                            \
 198         __raw_writel((value), (udc)->regs + USBA_##reg)
 199 #define usba_ep_readl(ep, reg)                                  \
 200         __raw_readl((ep)->ep_regs + USBA_EPT_##reg)
 201 #define usba_ep_writel(ep, reg, value)                          \
 202         __raw_writel((value), (ep)->ep_regs + USBA_EPT_##reg)
 203 #define usba_dma_readl(ep, reg)                                 \
 204         __raw_readl((ep)->dma_regs + USBA_DMA_##reg)
 205 #define usba_dma_writel(ep, reg, value)                         \
 206         __raw_writel((value), (ep)->dma_regs + USBA_DMA_##reg)
 207
 208 /* Calculate base address for a given endpoint or DMA controller */
 209 #define USBA_EPT_BASE(x)        (0x100 + (x) * 0x20)
 210 #define USBA_DMA_BASE(x)        (0x300 + (x) * 0x10)
 211 #define USBA_FIFO_BASE(x)       ((x) << 16)
 212
 213 /* Synth parameters */
 214 #define USBA_NR_ENDPOINTS       7
 215
 216 #define EP0_FIFO_SIZE           64
 217 #define EP0_EPT_SIZE            USBA_EPT_SIZE_64
 218 #define EP0_NR_BANKS            1
 219
 220 #define DBG_ERR         0x0001  /* report all error returns */
 221 #define DBG_HW          0x0002  /* debug hardware initialization */
 222 #define DBG_GADGET      0x0004  /* calls to/from gadget driver */
 223 #define DBG_INT         0x0008  /* interrupts */
 224 #define DBG_BUS         0x0010  /* report changes in bus state */
 225 #define DBG_QUEUE       0x0020  /* debug request queue processing */
 226 #define DBG_FIFO        0x0040  /* debug FIFO contents */
 227 #define DBG_DMA         0x0080  /* debug DMA handling */
 228 #define DBG_REQ         0x0100  /* print out queued request length */
 229 #define DBG_ALL         0xffff
 230 #define DBG_NONE        0x0000
 231
 232 #define DEBUG_LEVEL     (DBG_ERR)
 233
 234 #define DBG(level, fmt, ...)                                    \
 235         do {                                                    \
 236                 if ((level) & DEBUG_LEVEL)                      \
 237                         debug("udc: " fmt, ## __VA_ARGS__);     \
 238         } while (0)
 239
 240 enum usba_ctrl_state {
 241         WAIT_FOR_SETUP,
 242         DATA_STAGE_IN,
 243         DATA_STAGE_OUT,
 244         STATUS_STAGE_IN,
 245         STATUS_STAGE_OUT,
 246         STATUS_STAGE_ADDR,
 247         STATUS_STAGE_TEST,
 248 };
 249
 250 struct usba_dma_desc {
 251         dma_addr_t next;
 252         dma_addr_t addr;
 253         u32 ctrl;
 254 };
 255
 256 struct usba_ep {
 257         int                                     state;
 258         void                                    *ep_regs;
 259         void                                    *dma_regs;
 260         void                                    *fifo;
 261         struct usb_ep                           ep;
 262         struct usba_udc                         *udc;
 263
 264         struct list_head                        queue;
 265
 266         u16                                     fifo_size;
 267         u8                                      nr_banks;
 268         u8                                      index;
 269         unsigned int                            can_dma:1;
 270         unsigned int                            can_isoc:1;
 271         unsigned int                            is_isoc:1;
 272         unsigned int                            is_in:1;
 273
 274         const struct usb_endpoint_descriptor    *desc;
 275 };
 276
 277 struct usba_request {
 278         struct usb_request                      req;
 279         struct list_head                        queue;
 280
 281         u32                                     ctrl;
 282
 283         unsigned int                            submitted:1;
 284         unsigned int                            last_transaction:1;
 285         unsigned int                            using_dma:1;
 286         unsigned int                            mapped:1;
 287 };
 288
 289 struct usba_udc {
 290         void *regs;
 291         void *fifo;
 292
 293         struct usb_gadget gadget;
 294         struct usb_gadget_driver *driver;
 295         struct platform_device *pdev;
 296         int irq;
 297         int vbus_pin;
 298         int vbus_pin_inverted;
 299         int num_ep;
 300         struct usba_ep *usba_ep;
 301
 302         u16 devstatus;
 303
 304         u16 test_mode;
 305         int vbus_prev;
 306 };
 307
 308 static inline struct usba_ep *to_usba_ep(struct usb_ep *ep)
 309 {
 310         return container_of(ep, struct usba_ep, ep);
 311 }
 312
 313 static inline struct usba_request *to_usba_req(struct usb_request *req)
 314 {
 315         return container_of(req, struct usba_request, req);
 316 }
 317
 318 static inline struct usba_udc *to_usba_udc(struct usb_gadget *gadget)
 319 {
 320         return container_of(gadget, struct usba_udc, gadget);
 321 }
 322
 323 #define ep_is_control(ep)       ((ep)->index == 0)
 324 #define ep_is_idle(ep)          ((ep)->state == EP_STATE_IDLE)
 325
 326 #endif /* __LINUX_USB_GADGET_USBA_UDC_H */