qemu/roms/u-boot/board/syteco/jadecpu/lowlevel_init.S

   1 /*
   2  * Board specific setup info
   3  *
   4  * (C) Copyright 2007, mycable GmbH
   5  * Carsten Schneider <cs@mycable.de>, Alexander Bigga <ab@mycable.de>
   6  *
   7  * (C) Copyright 2003, ARM Ltd.
   8  * Philippe Robin, <philippe.robin@arm.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <config.h>
  14 #include <version.h>
  15 #include <asm/macro.h>
  16 #include <asm/arch/mb86r0x.h>
  17 #include <generated/asm-offsets.h>
  18
  19 /* Set up the platform, once the cpu has been initialized */
  20 .globl lowlevel_init
  21 lowlevel_init:
  22 /*
  23  * Initialize Clock Reset Generator (CRG)
  24  */
  25
  26         ldr             r0, =MB86R0x_CRG_BASE
  27
  28         /* Not change the initial value that is set by external pin.*/
  29 WAIT_PLL:
  30         ldr             r2, [r0, #CRG_CRPR]     /* Wait for PLLREADY */
  31         tst             r2, #MB86R0x_CRG_CRPR_PLLRDY
  32         beq             WAIT_PLL
  33
  34         /* Set clock gate control */
  35         ldr             r1, =CONFIG_SYS_CRG_CRHA_INIT
  36         str             r1, [r0, #CRG_CRHA]
  37         ldr             r1, =CONFIG_SYS_CRG_CRPA_INIT
  38         str             r1, [r0, #CRG_CRPA]
  39         ldr             r1, =CONFIG_SYS_CRG_CRPB_INIT
  40         str             r1, [r0, #CRG_CRPB]
  41         ldr             r1, =CONFIG_SYS_CRG_CRHB_INIT
  42         str             r1, [r0, #CRG_CRHB]
  43         ldr             r1, =CONFIG_SYS_CRG_CRAM_INIT
  44         str             r1, [r0, #CRG_CRAM]
  45
  46 /*
  47  * Initialize External Bus Interface
  48  */
  49         ldr             r0, =MB86R0x_MEMC_BASE
  50
  51         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE0_INIT
  52         str             r1, [r0, #MEMC_MCFMODE0]
  53         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE2_INIT
  54         str             r1, [r0, #MEMC_MCFMODE2]
  55         ldr             r1, =CONFIG_SYS_MEMC_MCFMODE4_INIT
  56         str             r1, [r0, #MEMC_MCFMODE4]
  57
  58         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM0_INIT
  59         str             r1, [r0, #MEMC_MCFTIM0]
  60         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM2_INIT
  61         str             r1, [r0, #MEMC_MCFTIM2]
  62         ldr             r1, =CONFIG_SYS_MEMC_MCFTIM4_INIT
  63         str             r1, [r0, #MEMC_MCFTIM4]
  64
  65         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA0_INIT
  66         str             r1, [r0, #MEMC_MCFAREA0]
  67         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA2_INIT
  68         str             r1, [r0, #MEMC_MCFAREA2]
  69         ldr             r1, =CONFIG_SYS_MEMC_MCFAREA4_INIT
  70         str             r1, [r0, #MEMC_MCFAREA4]
  71
  72 /*
  73  * Initialize DDR2 Controller
  74  */
  75
  76         /* Wait for PLL LOCK up time or more */
  77         wait_timer      20
  78
  79         /*
  80          * (2) Initialize DDRIF
  81          */
  82         ldr     r0, =MB86R0x_DDR2_BASE
  83         ldr     r1, =CONFIG_SYS_DDR2_DRIMS_INIT
  84         strh    r1, [r0, #DDR2_DRIMS]
  85
  86         /*
  87          * (3) Wait for 20MCKPs(120nsec) or more
  88          */
  89         wait_timer      20
  90
  91         /*
  92          * (4) IRESET/IUSRRST release
  93          */
  94         ldr     r0, =MB86R0x_CCNT_BASE
  95         ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_1
  96         str     r1, [r0, #CCNT_CDCRC]
  97
  98         /*
  99          * (5) Wait for 20MCKPs(120nsec) or more
 100          */
 101         wait_timer      20
 102
 103         /*
 104          * (6) IDLLRST release
 105          */
 106         ldr     r0, =MB86R0x_CCNT_BASE
 107         ldr     r1, =CONFIG_SYS_CCNT_CDCRC_INIT_2
 108         str     r1, [r0, #CCNT_CDCRC]
 109
 110         /*
 111          * (7+8) Wait for 200us(=200000ns) or more (DDR2 Spec)
 112          */
 113         wait_timer      33536
 114
 115         /*
 116          * (9) MCKE ON
 117          */
 118         ldr     r0, =MB86R0x_DDR2_BASE
 119         ldr     r1, =CONFIG_SYS_DDR2_DRIC1_INIT
 120         strh    r1, [r0, #DDR2_DRIC1]
 121         ldr     r1, =CONFIG_SYS_DDR2_DRIC2_INIT
 122         strh    r1, [r0, #DDR2_DRIC2]
 123         ldr     r1, =CONFIG_SYS_DDR2_DRCA_INIT
 124         strh    r1, [r0, #DDR2_DRCA]
 125         ldr     r1, =MB86R0x_DDR2_DRCI_INIT
 126         strh    r1, [r0, #DDR2_DRIC]
 127
 128         /*
 129          * (10) Initialize SDRAM
 130          */
 131
 132         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 133         strh    r1, [r0, #DDR2_DRIC]
 134
 135         wait_timer      67                      /* 400ns wait */
 136
 137         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_1
 138         strh    r1, [r0, #DDR2_DRIC1]
 139         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_1
 140         strh    r1, [r0, #DDR2_DRIC2]
 141         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 142         strh    r1, [r0, #DDR2_DRIC]
 143
 144         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_2
 145         strh    r1, [r0, #DDR2_DRIC1]
 146         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_2
 147         strh    r1, [r0, #DDR2_DRIC2]
 148         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 149         strh    r1, [r0, #DDR2_DRIC]
 150
 151         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_3
 152         strh    r1, [r0, #DDR2_DRIC1]
 153         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_3
 154         strh    r1, [r0, #DDR2_DRIC2]
 155         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 156         strh    r1, [r0, #DDR2_DRIC]
 157
 158         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_4
 159         strh    r1, [r0, #DDR2_DRIC1]
 160         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_4
 161         strh    r1, [r0, #DDR2_DRIC2]
 162         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 163         strh    r1, [r0, #DDR2_DRIC]
 164
 165         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_5
 166         strh    r1, [r0, #DDR2_DRIC1]
 167         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_5
 168         strh    r1, [r0, #DDR2_DRIC2]
 169         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 170         strh    r1, [r0, #DDR2_DRIC]
 171
 172         wait_timer 200
 173
 174         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_6
 175         strh    r1, [r0, #DDR2_DRIC1]
 176         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_6
 177         strh    r1, [r0, #DDR2_DRIC2]
 178         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 179         strh    r1, [r0, #DDR2_DRIC]
 180
 181         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_7
 182         strh    r1, [r0, #DDR2_DRIC1]
 183         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_7
 184         strh    r1, [r0, #DDR2_DRIC2]
 185         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 186         strh    r1, [r0, #DDR2_DRIC]
 187
 188         wait_timer      18                      /* 105ns wait */
 189
 190         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_8
 191         strh    r1, [r0, #DDR2_DRIC1]
 192         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_8
 193         strh    r1, [r0, #DDR2_DRIC2]
 194         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 195         strh    r1, [r0, #DDR2_DRIC]
 196
 197         wait_timer      200                     /* MRS to OCD: 200clock */
 198
 199         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_9
 200         strh    r1, [r0, #DDR2_DRIC1]
 201         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_9
 202         strh    r1, [r0, #DDR2_DRIC2]
 203         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 204         strh    r1, [r0, #DDR2_DRIC]
 205
 206         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC1_10
 207         strh    r1, [r0, #DDR2_DRIC1]
 208         ldr     r1, =CONFIG_SYS_DDR2_INIT_DRIC2_10
 209         strh    r1, [r0, #DDR2_DRIC2]
 210         ldr     r1, =MB86R0x_DDR2_DRCI_CMD
 211         strh    r1, [r0, #DDR2_DRIC]
 212
 213         ldr     r1, =CONFIG_SYS_DDR2_DRCM_INIT
 214         strh    r1, [r0, #DDR2_DRCM]
 215
 216         ldr     r1, =CONFIG_SYS_DDR2_DRCST1_INIT
 217         strh    r1, [r0, #DDR2_DRCST1]
 218
 219         ldr     r1, =CONFIG_SYS_DDR2_DRCST2_INIT
 220         strh    r1, [r0, #DDR2_DRCST2]
 221
 222         ldr     r1, =CONFIG_SYS_DDR2_DRCR_INIT
 223         strh    r1, [r0, #DDR2_DRCR]
 224
 225         ldr     r1, =CONFIG_SYS_DDR2_DRCF_INIT
 226         strh    r1, [r0, #DDR2_DRCF]
 227
 228         ldr     r1, =CONFIG_SYS_DDR2_DRASR_INIT
 229         strh    r1, [r0, #DDR2_DRASR]
 230
 231         /*
 232          * (11) ODT setting
 233          */
 234         ldr     r1, =CONFIG_SYS_DDR2_DROBS_INIT
 235         strh    r1, [r0, #DDR2_DROBS]
 236         ldr     r1, =CONFIG_SYS_DDR2_DROABA_INIT
 237         strh    r1, [r0, #DDR2_DROABA]
 238         ldr     r1, =CONFIG_SYS_DDR2_DRIBSODT1_INIT
 239         strh    r1, [r0, #DDR2_DRIBSODT1]
 240
 241         /*
 242          * (12) Shift to ODTCONT ON (SDRAM side) and DDR2 usual operation mode
 243          */
 244         ldr     r1, =CONFIG_SYS_DDR2_DROS_INIT
 245         strh    r1, [r0, #DDR2_DROS]
 246         ldr     r1, =MB86R0x_DDR2_DRCI_NORMAL
 247         strh    r1, [r0, #DDR2_DRIC]
 248
 249         mov pc, lr