qemu/roms/u-boot/board/sc3/sc3nand.c

   1 /*
   2  * (C) Copyright 2007
   3  * Heiko Schocher, DENX Software Engineering, hs@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9
  10 #if defined(CONFIG_CMD_NAND)
  11
  12 #include <nand.h>
  13 #include <asm/processor.h>
  14
  15 #define readb(addr)     *(volatile u_char *)(addr)
  16 #define readl(addr)     *(volatile u_long *)(addr)
  17 #define writeb(d,addr)  *(volatile u_char *)(addr) = (d)
  18
  19 #define SC3_NAND_ALE 29 /* GPIO PIN 3 */
  20 #define SC3_NAND_CLE 30 /* GPIO PIN 2 */
  21 #define SC3_NAND_CE  27 /* GPIO PIN 5 */
  22
  23 static void *sc3_io_base;
  24 static void *sc3_control_base = (void *)0xEF600700;
  25
  26 static void sc3_nand_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl)
  27 {
  28         struct nand_chip *this = mtd->priv;
  29         if (ctrl & NAND_CTRL_CHANGE) {
  30                 if ( ctrl & NAND_CLE )
  31                         set_bit (SC3_NAND_CLE, sc3_control_base);
  32                 else
  33                         clear_bit (SC3_NAND_CLE, sc3_control_base);
  34                 if ( ctrl & NAND_ALE )
  35                         set_bit (SC3_NAND_ALE, sc3_control_base);
  36                 else
  37                         clear_bit (SC3_NAND_ALE, sc3_control_base);
  38                 if ( ctrl & NAND_NCE )
  39                         set_bit (SC3_NAND_CE, sc3_control_base);
  40                 else
  41                         clear_bit (SC3_NAND_CE, sc3_control_base);
  42         }
  43
  44         if (cmd != NAND_CMD_NONE)
  45                 writeb(cmd, this->IO_ADDR_W);
  46 }
  47
  48 static int sc3_nand_dev_ready(struct mtd_info *mtd)
  49 {
  50         if (!(readl(sc3_control_base + 0x1C) & 0x4000))
  51                 return 0;
  52         return 1;
  53 }
  54
  55 static void sc3_select_chip(struct mtd_info *mtd, int chip)
  56 {
  57         clear_bit (SC3_NAND_CE, sc3_control_base);
  58 }
  59
  60 int board_nand_init(struct nand_chip *nand)
  61 {
  62         nand->ecc.mode = NAND_ECC_SOFT;
  63
  64         sc3_io_base = (void *) CONFIG_SYS_NAND_BASE;
  65         /* Set address of NAND IO lines (Using Linear Data Access Region) */
  66         nand->IO_ADDR_R = (void __iomem *) sc3_io_base;
  67         nand->IO_ADDR_W = (void __iomem *) sc3_io_base;
  68         /* Reference hardware control function */
  69         nand->cmd_ctrl  = sc3_nand_hwcontrol;
  70         nand->dev_ready  = sc3_nand_dev_ready;
  71         nand->select_chip = sc3_select_chip;
  72         return 0;
  73 }
  74 #endif