qemu/roms/u-boot/board/manroland/uc100/uc100.c

   1 /*
   2  * (C) Copyright 2000-2004
   3  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #if 0
   9 #define DEBUG
  10 #endif
  11
  12 #include <common.h>
  13 #include <mpc8xx.h>
  14 #include <i2c.h>
  15 #include <miiphy.h>
  16
  17 int fec8xx_miiphy_write(char *devname, unsigned char  addr,
  18                 unsigned char  reg, unsigned short value);
  19
  20 /*********************************************************************/
  21 /* UPMA Pre Initilization Table by WV (Miron MT48LC16M16A2-7E B)     */
  22 /*********************************************************************/
  23 const uint sdram_init_upm_table[] = {
  24         /* SDRAM Initialisation Sequence (offset 0 in UPMA RAM) WV */
  25         /* NOP    - Precharge - AutoRefr  - NOP       - NOP        */
  26         /* NOP    - AutoRefr  - NOP                                */
  27         /* NOP    - NOP       - LoadModeR - NOP       - Active     */
  28         /* Position of Single Read                                 */
  29         0x0ffffc04, 0x0ff77c04, 0x0ff5fc04, 0x0ffffc04, 0x0ffffc04,
  30         0x0ffffc04, 0x0ff5fc04, 0x0ffffc04,
  31
  32         /* Burst Read. (offset 8 in UPMA RAM)     */
  33         /* Cycle lent for Initialisation WV */
  34         0x0ffffc04, 0x0ffffc34, 0x0f057c34, 0x0ffffc30, 0x1ff7fc05,
  35         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  36         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  37
  38         /* Single Write. (offset 18 in UPMA RAM) */
  39         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  40         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  41
  42         /* Burst Write. (offset 20 in UPMA RAM) */
  43         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  44         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  45         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  46
  47         /* Refresh  (offset 30 in UPMA RAM) */
  48         0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
  49         0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  50         0xFFFFFFFF, 0xFFFFFFFF,
  51
  52         /* Exception. (offset 3c in UPMA RAM) */
  53         0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  54 };
  55
  56 /*********************************************************************/
  57 /* UPMA initilization table.                                         */
  58 /*********************************************************************/
  59 const uint sdram_upm_table[] = {
  60         /* single read. (offset 0 in UPMA RAM) */
  61         0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x0FF77C00, 0x1FFFFC05,
  62         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,     /* 0x05-0x07 new WV */
  63
  64         /* Burst Read. (offset 8 in UPMA RAM) */
  65         0x0F07FC04, 0x0FFFFC04, 0x00BDFC04, 0x00FFFC00, 0x00FFFC00,
  66         0x00FFFC00, 0x0FF77C00, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  67         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  68
  69         /* Single Write. (offset 18 in UPMA RAM) */
  70         0x0F07FC04, 0x0FFFFC00, 0x00BD7C04, 0x0FFFFC04, 0x0FF77C04,
  71         0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF,
  72
  73         /* Burst Write. (offset 20 in UPMA RAM) */
  74         0x0F07FC04, 0x0FFFFC00, 0x00BD7C00, 0x00FFFC00, 0x00FFFC00,
  75         0x00FFFC04, 0x0FFFFC04, 0x0FF77C04, 0x1FFFFC05, 0xFFFFFFFF,
  76         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  77
  78         /* Refresh  (offset 30 in UPMA RAM) */
  79         0x0FF77C04, 0x0FFFFC04, 0x0FF5FC84, 0x0FFFFC04, 0x0FFFFC04,
  80         0x0FFFFC84, 0x1FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  81         0xFFFFFFFF, 0xFFFFFFFF,
  82
  83         /* Exception. (offset 3c in UPMA RAM) */
  84         0x7FFFFC05, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, /* 0x3C new WV */
  85 };
  86
  87 /*********************************************************************/
  88 /* UPMB initilization table.                                         */
  89 /*********************************************************************/
  90 const uint mpm_upm_table[] = {
  91         /*  single read. (offset 0 in upm RAM) */
  92         0x8FF00004, 0x0FF00004, 0x0FF81004, 0x1FF00001,
  93         0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  94
  95         /* burst read. (Offset 8 in upm RAM)   */
  96         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  97         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  98         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
  99         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 100
 101         /* single write. (Offset 0x18 in upm RAM) */
 102         0x8FF00004, 0x0FF00004, 0x0FF81004, 0x0FF00004,
 103         0x0FF00004, 0x1FF00001, 0xFFFFFFFF, 0xFFFFFFFF,
 104
 105         /*  burst write. (Offset 0x20 in upm RAM) */
 106         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 107         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 108         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 109         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 110
 111         /* Refresh cycle, offset 0x30 */
 112         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 113         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 114         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 115
 116         /* Exception, 0ffset 0x3C */
 117         0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF, 0xFFFFFFFF,
 118 };
 119
 120
 121 int board_switch(void)
 122 {
 123         volatile pcmconf8xx_t   *pcmp;
 124
 125         pcmp  = (pcmconf8xx_t *)(&(((immap_t *)CONFIG_SYS_IMMR)->im_pcmcia));
 126
 127         return ((pcmp->pcmc_pipr >> 24) & 0xf);
 128 }
 129
 130
 131 /*
 132  * Check Board Identity:
 133  */
 134 int checkboard (void)
 135 {
 136         char str[64];
 137         int i = getenv_f("serial#", str, sizeof(str));
 138
 139         puts ("Board: ");
 140
 141         if (i == -1) {
 142                 puts ("### No HW ID - assuming UC100");
 143         } else {
 144                 puts(str);
 145         }
 146
 147         printf (" (SWITCH=%1X)\n", board_switch());
 148
 149         return 0;
 150 }
 151
 152
 153 /*
 154  * Initialize SDRAM
 155  */
 156 phys_size_t initdram (int board_type)
 157 {
 158         volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
 159         volatile memctl8xx_t *memctl = &immap->im_memctl;
 160
 161         /*---------------------------------------------------------------------*/
 162         /* Initialize the UPMA/UPMB registers with the appropriate table.      */
 163         /*---------------------------------------------------------------------*/
 164         upmconfig (UPMA, (uint *) sdram_init_upm_table,
 165                    sizeof (sdram_init_upm_table) / sizeof (uint));
 166         upmconfig (UPMB, (uint *) mpm_upm_table,
 167                    sizeof (mpm_upm_table) / sizeof (uint));
 168
 169         /*---------------------------------------------------------------------*/
 170         /* Memory Periodic Timer Prescaler: divide by 16                       */
 171         /*---------------------------------------------------------------------*/
 172         memctl->memc_mptpr = 0x0200; /* Divide by 32 WV */
 173
 174         memctl->memc_mamr = CONFIG_SYS_MAMR_VAL & 0xFF7FFFFF; /* Bit 8 := "0" Kein Refresh WV */
 175         memctl->memc_mbmr = CONFIG_SYS_MBMR_VAL;
 176
 177         /*---------------------------------------------------------------------*/
 178         /* Initialize the Memory Controller registers, MPTPR, Chip Select 1    */
 179         /* for SDRAM                                                           */
 180         /*                                                                     */
 181         /* NOTE: The refresh rate in MAMR reg is set according to the lowest   */
 182         /*       clock rate (16.67MHz) to allow proper operation for all ADS   */
 183         /*       clock frequencies.                                            */
 184         /*---------------------------------------------------------------------*/
 185         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 186         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 187
 188         /*-------------------------------------------------------------------*/
 189         /* Wait at least 200 usec for DRAM to stabilize, this magic number   */
 190         /* obtained from the init code.                                      */
 191         /*-------------------------------------------------------------------*/
 192         udelay(200);
 193
 194         memctl->memc_mamr = (memctl->memc_mamr | 0x04) & ~0x08;
 195
 196         memctl->memc_br1 = CONFIG_SYS_BR1_PRELIM;
 197         memctl->memc_or1 = CONFIG_SYS_OR1_PRELIM;
 198
 199         /*---------------------------------------------------------------------*/
 200         /* run MRS command in location 5-8 of UPMB.                            */
 201         /*---------------------------------------------------------------------*/
 202         memctl->memc_mar = 0x88;
 203         /* RUN UPMA on CS1 1-time from UPMA addr 0x05 */
 204
 205         memctl->memc_mcr = 0x80002100;
 206         /* RUN UPMA on CS1 1-time from UPMA addr 0x00 WV */
 207
 208         udelay(200);
 209
 210         /*---------------------------------------------------------------------*/
 211         /* Initialisation for normal access WV                                 */
 212         /*---------------------------------------------------------------------*/
 213
 214         /*---------------------------------------------------------------------*/
 215         /* Initialize the UPMA register with the appropriate table.            */
 216         /*---------------------------------------------------------------------*/
 217         upmconfig (UPMA, (uint *) sdram_upm_table,
 218                    sizeof (sdram_upm_table) / sizeof (uint));
 219
 220         /*---------------------------------------------------------------------*/
 221         /* rerstore MBMR value (4-beat refresh burst.)                         */
 222         /*---------------------------------------------------------------------*/
 223         memctl->memc_mamr = CONFIG_SYS_MAMR_VAL | 0x00800000; /* Bit 8 := "1" Refresh Enable WV */
 224
 225         udelay(200);
 226
 227         return (64 * 1024 * 1024); /* fixed setup for 64MBytes! */
 228 }
 229
 230
 231 int misc_init_r (void)
 232 {
 233         uchar val;
 234
 235         /*
 236          * Make sure that RTC has clock output enabled (triggers watchdog!)
 237          */
 238         val = i2c_reg_read (CONFIG_SYS_I2C_RTC_ADDR, 0x0D);
 239         val |= 0x80;
 240         i2c_reg_write (CONFIG_SYS_I2C_RTC_ADDR, 0x0D, val);
 241
 242         /*
 243          * Configure PHY to setup LED's correctly and use 100MBit, FD
 244          */
 245         mii_init();
 246
 247         /* disable auto-negotiation, 100mbit, full-duplex */
 248         fec8xx_miiphy_write(NULL, 0, MII_BMCR, 0x2100);
 249
 250         /* set LED's to Link, Transmit, Receive           */
 251         fec8xx_miiphy_write(NULL,  0, MII_NWAYTEST, 0x4122);
 252
 253         return 0;
 254 }