qemu/roms/u-boot/board/gdsys/p1022/tlb.c

   1 /*
   2  * Copyright 2010 Freescale Semiconductor, Inc.
   3  * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
   4  *          Timur Tabi <timur@freescale.com>
   5  *
   6  * This program is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License as published by the Free
   8  * Software Foundation; either version 2 of the License, or (at your option)
   9  * any later version.
  10  */
  11
  12 #include <common.h>
  13 #include <asm/mmu.h>
  14
  15 struct fsl_e_tlb_entry tlb_table[] = {
  16         /* TLB 0 - for temp stack in cache */
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  21                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  22                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23                       0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  25                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  26                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  27                       0, 0, BOOKE_PAGESZ_4K, 0),
  28         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  29                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  30                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  31                       0, 0, BOOKE_PAGESZ_4K, 0),
  32
  33         /* TLB 1 */
  34         /* *I*** - Covers boot page */
  35         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  36                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  37                       0, 0, BOOKE_PAGESZ_4K, 1),
  38
  39         /* *I*G* - CCSRBAR */
  40         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  41                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  42                       0, 1, BOOKE_PAGESZ_1M, 1),
  43
  44         /* *I*G* - eLBC */
  45         SET_TLB_ENTRY(1, CONFIG_SYS_ELBC_BASE, CONFIG_SYS_ELBC_BASE_PHYS,
  46                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  47                       0, 2, BOOKE_PAGESZ_1M, 1),
  48
  49 #if defined(CONFIG_TRAILBLAZER)
  50         /* *I*G - L2SRAM */
  51         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  52                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53                       0, 9, BOOKE_PAGESZ_256K, 1),
  54 #else
  55         /* *I*G* - PCI */
  56         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  57                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  58                       0, 3, BOOKE_PAGESZ_256M, 1),
  59         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000,
  60                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000,
  61                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62                       0, 4, BOOKE_PAGESZ_256M, 1),
  63
  64         /* *I*G* - PCI I/O */
  65         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  66                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  67                       0, 5, BOOKE_PAGESZ_256K, 1),
  68
  69 #ifdef CONFIG_SYS_RAMBOOT
  70         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  71                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  72                       0, 6, BOOKE_PAGESZ_1G, 1),
  73 #endif
  74 #endif
  75 };
  76
  77 int num_tlb_entries = ARRAY_SIZE(tlb_table);