qemu/roms/u-boot/board/gdsys/405ep/neo.c

   1 /*
   2  * (C) Copyright 2011
   3  * Dirk Eibach,  Guntermann & Drunck GmbH, eibach@gdsys.de
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #include <common.h>
   9 #include <command.h>
  10 #include <asm/processor.h>
  11 #include <asm/io.h>
  12 #include <asm/ppc4xx-gpio.h>
  13 #include <dtt.h>
  14
  15 #include "405ep.h"
  16 #include <gdsys_fpga.h>
  17
  18 #define LATCH0_BASE (CONFIG_SYS_LATCH_BASE)
  19 #define LATCH1_BASE (CONFIG_SYS_LATCH_BASE + 0x100)
  20 #define LATCH2_BASE (CONFIG_SYS_LATCH_BASE + 0x200)
  21
  22 enum {
  23         UNITTYPE_CCX16 = 1,
  24         UNITTYPE_CCIP216 = 2,
  25 };
  26
  27 enum {
  28         HWVER_300 = 3,
  29 };
  30
  31 struct ihs_fpga *fpga_ptr[] = CONFIG_SYS_FPGA_PTR;
  32
  33 int misc_init_r(void)
  34 {
  35         /* startup fans */
  36         dtt_init();
  37
  38         return 0;
  39 }
  40
  41 int checkboard(void)
  42 {
  43         char *s = getenv("serial#");
  44
  45         puts("Board: CATCenter Neo");
  46
  47         if (s != NULL) {
  48                 puts(", serial# ");
  49                 puts(s);
  50         }
  51
  52         puts("\n");
  53
  54         return 0;
  55 }
  56
  57 static void print_fpga_info(void)
  58 {
  59         u16 versions;
  60         u16 fpga_version;
  61         u16 fpga_features;
  62         int fpga_state = get_fpga_state(0);
  63         unsigned unit_type;
  64         unsigned hardware_version;
  65         unsigned feature_channels;
  66
  67         puts("FPGA:  ");
  68         if (fpga_state & FPGA_STATE_DONE_FAILED) {
  69                 printf(" done timed out\n");
  70                 return;
  71         }
  72
  73         if (fpga_state & FPGA_STATE_REFLECTION_FAILED) {
  74                 printf(" refelectione test failed\n");
  75                 return;
  76         }
  77
  78         FPGA_GET_REG(0, versions, &versions);
  79         FPGA_GET_REG(0, fpga_version, &fpga_version);
  80         FPGA_GET_REG(0, fpga_features, &fpga_features);
  81
  82         unit_type = (versions & 0xf000) >> 12;
  83         hardware_version = versions & 0x000f;
  84         feature_channels = fpga_features & 0x007f;
  85
  86         switch (unit_type) {
  87         case UNITTYPE_CCX16:
  88                 printf("CCX-Switch");
  89                 break;
  90
  91         default:
  92                 printf("UnitType %d(not supported)", unit_type);
  93                 break;
  94         }
  95
  96         switch (hardware_version) {
  97         case HWVER_300:
  98                 printf(" HW-Ver 3.00-3.12\n");
  99                 break;
 100
 101         default:
 102                 printf(" HW-Ver %d(not supported)\n",
 103                        hardware_version);
 104                 break;
 105         }
 106
 107         printf("       FPGA V %d.%02d, features:",
 108                 fpga_version / 100, fpga_version % 100);
 109
 110         printf(" %d channel(s)\n", feature_channels);
 111 }
 112
 113 int last_stage_init(void)
 114 {
 115         print_fpga_info();
 116
 117         return 0;
 118 }
 119
 120 void gd405ep_init(void)
 121 {
 122 }
 123
 124 void gd405ep_set_fpga_reset(unsigned state)
 125 {
 126         if (state) {
 127                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_RESET);
 128                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_RESET);
 129         } else {
 130                 out_le16((void *)LATCH0_BASE, CONFIG_SYS_LATCH0_BOOT);
 131                 out_le16((void *)LATCH1_BASE, CONFIG_SYS_LATCH1_BOOT);
 132         }
 133 }
 134
 135 void gd405ep_setup_hw(void)
 136 {
 137         /*
 138          * set "startup-finished"-gpios
 139          */
 140         gpio_write_bit(21, 0);
 141         gpio_write_bit(22, 1);
 142 }
 143
 144 int gd405ep_get_fpga_done(unsigned fpga)
 145 {
 146         /*
 147          * Neo hardware has no FPGA-DONE GPIO
 148          */
 149         return 1;
 150 }