qemu/roms/u-boot/board/freescale/p1_p2_rdb/tlb.c

   1 /*
   2  * Copyright 2011 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <asm/mmu.h>
   9
  10 struct fsl_e_tlb_entry tlb_table[] = {
  11         /* TLB 0 - for temp stack in cache */
  12         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  13                         CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  14                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15                         0, 0, BOOKE_PAGESZ_4K, 0),
  16         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 ,
  17                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  18                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                         0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 ,
  21                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  22                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23                         0, 0, BOOKE_PAGESZ_4K, 0),
  24         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 ,
  25                         CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  26                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  27                         0, 0, BOOKE_PAGESZ_4K, 0),
  28
  29         /* TLB 1 */
  30         /* *I*** - Covers boot page */
  31         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  32                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  33                         0, 0, BOOKE_PAGESZ_4K, 1),
  34
  35         /* *I*G* - CCSRBAR */
  36         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  37                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  38                         0, 1, BOOKE_PAGESZ_1M, 1),
  39
  40         /* W**G* - Flash/promjet, localbus */
  41         /* This will be changed to *I*G* after relocation to RAM. */
  42         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  43                         MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  44                         0, 2, BOOKE_PAGESZ_16M, 1),
  45
  46 #if defined(CONFIG_PCI)
  47         /* *I*G* - PCI */
  48         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  49                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50                         0, 3, BOOKE_PAGESZ_1G, 1),
  51
  52         /* *I*G* - PCI I/O */
  53         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  54                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  55                         0, 4, BOOKE_PAGESZ_256K, 1),
  56
  57 #endif /* #if defined(CONFIG_PCI) */
  58         /* *I*G - NAND */
  59         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  60                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  61                         0, 5, BOOKE_PAGESZ_1M, 1),
  62
  63         /* *I*G - VSC7385 Switch */
  64         SET_TLB_ENTRY(1, CONFIG_SYS_VSC7385_BASE, CONFIG_SYS_VSC7385_BASE_PHYS,
  65                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  66                         0, 6, BOOKE_PAGESZ_1M, 1),
  67
  68 #if defined(CONFIG_SYS_RAMBOOT)
  69         SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE,
  70                         MAS3_SX|MAS3_SW|MAS3_SR, 0,
  71                         0, 7, BOOKE_PAGESZ_1G, 1)
  72 #endif
  73 };
  74
  75 int num_tlb_entries = ARRAY_SIZE(tlb_table);