qemu/roms/u-boot/board/freescale/common/p_corenet/tlb.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <asm/mmu.h>
  12
  13 struct fsl_e_tlb_entry tlb_table[] = {
  14         /* TLB 0 - for temp stack in cache */
  15         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR,
  16                       CONFIG_SYS_INIT_RAM_ADDR_PHYS,
  17                       MAS3_SW|MAS3_SR, 0,
  18                       0, 0, BOOKE_PAGESZ_4K, 0),
  19         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  20                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 4 * 1024,
  21                       MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  24                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 8 * 1024,
  25                       MAS3_SW|MAS3_SR, 0,
  26                       0, 0, BOOKE_PAGESZ_4K, 0),
  27         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  28                       CONFIG_SYS_INIT_RAM_ADDR_PHYS + 12 * 1024,
  29                       MAS3_SW|MAS3_SR, 0,
  30                       0, 0, BOOKE_PAGESZ_4K, 0),
  31 #ifdef CPLD_BASE
  32         SET_TLB_ENTRY(0, CPLD_BASE, CPLD_BASE_PHYS,
  33                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  34                       0, 0, BOOKE_PAGESZ_4K, 0),
  35 #endif
  36
  37 #ifdef PIXIS_BASE
  38         SET_TLB_ENTRY(0, PIXIS_BASE, PIXIS_BASE_PHYS,
  39                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  40                       0, 0, BOOKE_PAGESZ_4K, 0),
  41 #endif
  42
  43         /* TLB 1 */
  44         /* *I*** - Covers boot page */
  45 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L3_ADDR)
  46         /*
  47          * *I*G - L3SRAM. When L3 is used as 1M SRAM, the address of the
  48          * SRAM is at 0xfff00000, it covered the 0xfffff000.
  49          */
  50         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L3_ADDR, CONFIG_SYS_INIT_L3_ADDR,
  51                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  52                         0, 0, BOOKE_PAGESZ_1M, 1),
  53 #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE)
  54         /*
  55          * SRIO_PCIE_BOOT-SLAVE. When slave boot, the address of the
  56          * space is at 0xfff00000, it covered the 0xfffff000.
  57          */
  58         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR,
  59                         CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
  60                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  61                         0, 0, BOOKE_PAGESZ_1M, 1),
  62 #else
  63         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  64                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  65                       0, 0, BOOKE_PAGESZ_4K, 1),
  66 #endif
  67
  68         /* *I*G* - CCSRBAR */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  70                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 1, BOOKE_PAGESZ_16M, 1),
  72
  73         /* *I*G* - Flash, localbus */
  74         /* This will be changed to *I*G* after relocation to RAM. */
  75         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  76                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  77                       0, 2, BOOKE_PAGESZ_256M, 1),
  78
  79         /* *I*G* - PCI */
  80         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  81                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  82                       0, 3, BOOKE_PAGESZ_1G, 1),
  83
  84         /* *I*G* - PCI */
  85         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x40000000,
  86                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x40000000,
  87                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  88                       0, 4, BOOKE_PAGESZ_256M, 1),
  89
  90         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT + 0x50000000,
  91                       CONFIG_SYS_PCIE1_MEM_PHYS + 0x50000000,
  92                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  93                       0, 5, BOOKE_PAGESZ_256M, 1),
  94
  95         /* *I*G* - PCI I/O */
  96         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
  97                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  98                       0, 6, BOOKE_PAGESZ_256K, 1),
  99
 100         /* Bman/Qman */
 101 #ifdef CONFIG_SYS_BMAN_MEM_PHYS
 102         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
 103                       MAS3_SW|MAS3_SR, 0,
 104                       0, 9, BOOKE_PAGESZ_1M, 1),
 105         SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
 106                       CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
 107                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 108                       0, 10, BOOKE_PAGESZ_1M, 1),
 109 #endif
 110 #ifdef CONFIG_SYS_QMAN_MEM_PHYS
 111         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
 112                       MAS3_SW|MAS3_SR, 0,
 113                       0, 11, BOOKE_PAGESZ_1M, 1),
 114         SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
 115                       CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
 116                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 117                       0, 12, BOOKE_PAGESZ_1M, 1),
 118 #endif
 119 #ifdef CONFIG_SYS_DCSRBAR_PHYS
 120         SET_TLB_ENTRY(1, CONFIG_SYS_DCSRBAR, CONFIG_SYS_DCSRBAR_PHYS,
 121                       MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 122                       0, 13, BOOKE_PAGESZ_4M, 1),
 123 #endif
 124 #ifdef CONFIG_SYS_NAND_BASE
 125         /*
 126          * *I*G - NAND
 127          * entry 14 and 15 has been used hard coded, they will be disabled
 128          * in cpu_init_f, so we use entry 16 for nand.
 129          */
 130         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
 131                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
 132                         0, 16, BOOKE_PAGESZ_1M, 1),
 133 #endif
 134 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 135         /*
 136          * SRIO_PCIE_BOOT-SLAVE. 1M space from 0xffe00000 for
 137          * fetching ucode and ENV from master
 138          */
 139         SET_TLB_ENTRY(1, CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR,
 140                 CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 141                 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_G,
 142                 0, 17, BOOKE_PAGESZ_1M, 1),
 143 #endif
 144 };
 145
 146 int num_tlb_entries = ARRAY_SIZE(tlb_table);