2 * (C) Copyright 2009 Faraday Technology
3 * Po-Yu Chuang <ratbert@faraday-tech.com>
5 * SPDX-License-Identifier: GPL-2.0+
11 #include <asm/macro.h>
12 #include <faraday/ftsdmc020.h>
15 * parameters for the SDRAM controller
17 #define TP0_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP0)
18 #define TP1_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_TP1)
19 #define CR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_CR)
20 #define B0_BSR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_BANK0_BSR)
21 #define ACR_A (CONFIG_FTSDMC020_BASE + FTSDMC020_OFFSET_ACR)
23 #define TP0_D CONFIG_SYS_FTSDMC020_TP0
24 #define TP1_D CONFIG_SYS_FTSDMC020_TP1
25 #define CR_D1 FTSDMC020_CR_IPREC
26 #define CR_D2 FTSDMC020_CR_ISMR
27 #define CR_D3 FTSDMC020_CR_IREF
29 #define B0_BSR_D (CONFIG_SYS_FTSDMC020_BANK0_BSR | \
30 FTSDMC020_BANK_BASE(PHYS_SDRAM_1))
31 #define ACR_D FTSDMC020_ACR_TOC(0x18)
34 * numeric 7 segment display
37 write32 CONFIG_DEBUG_LED, \num
41 * Waiting for SDRAM to set up
44 ldr r0, =CONFIG_FTSDMC020_BASE
46 ldr r1, [r0, #FTSDMC020_OFFSET_CR]
61 /* everything is fine now */
66 * memory initialization
71 /* set SDRAM register */
79 /* set to precharge */
86 /* set mode register */
100 write32 B0_BSR_A, B0_BSR_D