qemu/roms/u-boot/board/esd/pci405/writeibm.S

   1 /*
   2  * SPDX-License-Identifier:     GPL-2.0 IBM-pibs
   3  */
   4 /*----------------------------------------------------------------------------- */
   5 /* Function:     ext_bus_cntlr_init */
   6 /* Description:  Initializes the External Bus Controller for the external */
   7 /*              peripherals. IMPORTANT: For pass1 this code must run from */
   8 /*              cache since you can not reliably change a peripheral banks */
   9 /*              timing register (pbxap) while running code from that bank. */
  10 /*              For ex., since we are running from ROM on bank 0, we can NOT */
  11 /*              execute the code that modifies bank 0 timings from ROM, so */
  12 /*              we run it from cache. */
  13 /*      Bank 0 - Flash and SRAM */
  14 /*      Bank 1 - NVRAM/RTC */
  15 /*      Bank 2 - Keyboard/Mouse controller */
  16 /*      Bank 3 - IR controller */
  17 /*      Bank 4 - not used */
  18 /*      Bank 5 - not used */
  19 /*      Bank 6 - not used */
  20 /*      Bank 7 - FPGA registers */
  21 /*----------------------------------------------------------------------------- */
  22 #include <asm/ppc4xx.h>
  23
  24 #include <ppc_asm.tmpl>
  25 #include <ppc_defs.h>
  26
  27 #include <asm/cache.h>
  28 #include <asm/mmu.h>
  29
  30
  31         .globl  write_without_sync
  32 write_without_sync:
  33                 /*
  34                  * Write one values to host via pci busmastering
  35                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
  36                  * *ptr = 0x01234567;
  37                  */
  38         addi    r31,0,0
  39         lis     r31,0xc000
  40
  41 start1:
  42         lis     r0,0x0123
  43         ori     r0,r0,0x4567
  44         stw     r0,0(r31)
  45
  46                 /*
  47                  * Read one value back
  48                  * ptr = (volatile unsigned long *)addr;
  49                  * val = *ptr;
  50                  */
  51
  52         lwz     r0,0(r31)
  53
  54                 /*
  55                  * One pci config write
  56                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
  57                  */
  58                 /* subsystem id */
  59
  60         li      r4,0x002C
  61         oris    r4,r4,0x8000
  62         lis     r3,0xEEC0
  63         stwbrx  r4,0,r3
  64
  65         li      r5,0x1234
  66         ori     r3,r3,0x4
  67         stwbrx  r5,0,r3
  68
  69         b       start1
  70
  71         blr     /* never reached !!!! */
  72
  73         .globl  write_with_sync
  74 write_with_sync:
  75                 /*
  76                  * Write one values to host via pci busmastering
  77                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
  78                  * *ptr = 0x01234567;
  79                  */
  80         addi    r31,0,0
  81         lis     r31,0xc000
  82
  83 start2:
  84         lis     r0,0x0123
  85         ori     r0,r0,0x4567
  86         stw     r0,0(r31)
  87
  88                 /*
  89                  * Read one value back
  90                  * ptr = (volatile unsigned long *)addr;
  91                  * val = *ptr;
  92                  */
  93
  94         lwz     r0,0(r31)
  95
  96                 /*
  97                  * One pci config write
  98                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
  99                  */
 100                 /* subsystem id */
 101
 102         li      r4,0x002C
 103         oris    r4,r4,0x8000
 104         lis     r3,0xEEC0
 105         stwbrx  r4,0,r3
 106         sync
 107
 108         li      r5,0x1234
 109         ori     r3,r3,0x4
 110         stwbrx  r5,0,r3
 111         sync
 112
 113         b       start2
 114
 115         blr     /* never reached !!!! */
 116
 117         .globl  write_with_less_sync
 118 write_with_less_sync:
 119                 /*
 120                  * Write one values to host via pci busmastering
 121                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
 122                  * *ptr = 0x01234567;
 123                  */
 124         addi    r31,0,0
 125         lis     r31,0xc000
 126
 127 start2b:
 128         lis     r0,0x0123
 129         ori     r0,r0,0x4567
 130         stw     r0,0(r31)
 131
 132                 /*
 133                  * Read one value back
 134                  * ptr = (volatile unsigned long *)addr;
 135                  * val = *ptr;
 136                  */
 137
 138         lwz     r0,0(r31)
 139
 140                 /*
 141                  * One pci config write
 142                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
 143                  */
 144                 /* subsystem id */
 145
 146         li      r4,0x002C
 147         oris    r4,r4,0x8000
 148         lis     r3,0xEEC0
 149         stwbrx  r4,0,r3
 150         sync
 151
 152         li      r5,0x1234
 153         ori     r3,r3,0x4
 154         stwbrx  r5,0,r3
 155 /*        sync */
 156
 157         b       start2b
 158
 159         blr     /* never reached !!!! */
 160
 161         .globl  write_with_more_sync
 162 write_with_more_sync:
 163                 /*
 164                  * Write one values to host via pci busmastering
 165                  * ptr = 0xc0000000 -> 0x01000000 (PCI)
 166                  * *ptr = 0x01234567;
 167                  */
 168         addi    r31,0,0
 169         lis     r31,0xc000
 170
 171 start3:
 172         lis     r0,0x0123
 173         ori     r0,r0,0x4567
 174         stw     r0,0(r31)
 175         sync
 176
 177                 /*
 178                  * Read one value back
 179                  * ptr = (volatile unsigned long *)addr;
 180                  * val = *ptr;
 181                  */
 182
 183         lwz     r0,0(r31)
 184         sync
 185
 186                 /*
 187                  * One pci config write
 188                  * ibmPciConfigWrite(0x2e, 2, 0x1234);
 189                  */
 190                 /* subsystem id (PCIC0_SBSYSVID)*/
 191
 192         li      r4,0x002C
 193         oris    r4,r4,0x8000
 194         lis     r3,0xEEC0
 195         stwbrx  r4,0,r3
 196         sync
 197
 198         li      r5,0x1234
 199         ori     r3,r3,0x4
 200         stwbrx  r5,0,r3
 201         sync
 202
 203         b       start3
 204
 205         blr     /* never reached !!!! */