2 * Creative ZEN X-Fi3 board
4 * Copyright (C) 2013 Marek Vasut <marex@denx.de>
6 * Hardware investigation done by:
8 * Amaury Pouly <amaury.pouly@gmail.com>
10 * SPDX-License-Identifier: GPL-2.0+
17 #include <asm/arch/iomux-mx23.h>
18 #include <asm/arch/imx-regs.h>
19 #include <asm/arch/clock.h>
20 #include <asm/arch/sys_proto.h>
22 DECLARE_GLOBAL_DATA_PTR;
27 int board_early_init_f(void)
29 /* IO0 clock at 480MHz */
30 mxs_set_ioclk(MXC_IOCLK0, 480000);
32 /* SSP0 clock at 96MHz */
33 mxs_set_sspclk(MXC_SSPCLK0, 96000, 0);
40 return mxs_dram_init();
44 static int xfi3_mmc_cd(int id)
48 /* The SSP_DETECT is inverted on this board. */
49 return gpio_get_value(MX23_PAD_SSP1_DETECT__GPIO_2_1);
51 /* Phison bridge always present */
58 int board_mmc_init(bd_t *bis)
63 gpio_direction_input(MX23_PAD_SSP1_DETECT__GPIO_2_1);
64 gpio_direction_output(MX23_PAD_GPMI_D07__GPIO_0_7, 0);
65 ret = mxsmmc_initialize(bis, 0, NULL, xfi3_mmc_cd);
69 /* Phison SD-NAND bridge */
70 ret = mxsmmc_initialize(bis, 1, NULL, xfi3_mmc_cd);
76 #ifdef CONFIG_VIDEO_MXS
77 static int mxsfb_write_byte(uint32_t payload, const unsigned int data)
79 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
80 const unsigned int timeout = 0x10000;
82 if (mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
86 writel((1 << LCDIF_TRANSFER_COUNT_V_COUNT_OFFSET) |
87 (1 << LCDIF_TRANSFER_COUNT_H_COUNT_OFFSET),
88 ®s->hw_lcdif_transfer_count);
90 writel(LCDIF_CTRL_DATA_SELECT | LCDIF_CTRL_RUN,
91 ®s->hw_lcdif_ctrl_clr);
94 writel(LCDIF_CTRL_DATA_SELECT, ®s->hw_lcdif_ctrl_set);
96 writel(LCDIF_CTRL_RUN, ®s->hw_lcdif_ctrl_set);
98 if (mxs_wait_mask_clr(®s->hw_lcdif_lcdif_stat_reg, 1 << 29,
102 writel(payload, ®s->hw_lcdif_data);
103 return mxs_wait_mask_clr(®s->hw_lcdif_ctrl_reg, LCDIF_CTRL_RUN,
107 static void mxsfb_write_register(uint32_t reg, uint32_t data)
109 mxsfb_write_byte(reg, 0);
110 mxsfb_write_byte(data, 1);
113 static const struct {
120 /* Writing 0x30 to reg. 0x03 flips the LCD */
123 /* This can contain 0x111 to rotate the LCD. */
127 { 0x21, 30, 0x0000 },
128 /* Wait 30 mS here */
130 { 0x11, 30, 0x1038 },
131 /* Wait 30 mS here */
154 { 0x59, 30, 0x0a09 },
155 /* Wait 30 mS here */
156 { 0x07, 30, 0x1017 },
157 /* Wait 40 mS here */
166 void board_mxsfb_system_setup(void)
168 struct mxs_lcdif_regs *regs = (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
171 /* Switch the LCDIF into System-Mode */
172 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DOTCLK_MODE |
173 LCDIF_CTRL_BYPASS_COUNT, ®s->hw_lcdif_ctrl_clr);
175 /* Restart the SmartLCD controller */
177 writel(1, ®s->hw_lcdif_ctrl1_set);
179 writel(1, ®s->hw_lcdif_ctrl1_clr);
181 writel(1, ®s->hw_lcdif_ctrl1_set);
184 /* Program the SmartLCD controller */
185 writel(LCDIF_CTRL1_RECOVER_ON_UNDERFLOW, ®s->hw_lcdif_ctrl1_set);
187 writel((0x03 << LCDIF_TIMING_CMD_HOLD_OFFSET) |
188 (0x03 << LCDIF_TIMING_CMD_SETUP_OFFSET) |
189 (0x03 << LCDIF_TIMING_DATA_HOLD_OFFSET) |
190 (0x02 << LCDIF_TIMING_DATA_SETUP_OFFSET),
191 ®s->hw_lcdif_timing);
194 * OTM2201A init and configuration sequence.
196 for (i = 0; i < ARRAY_SIZE(lcd_regs); i++) {
197 mxsfb_write_register(lcd_regs[i].reg, lcd_regs[i].val);
198 if (lcd_regs[i].delay)
199 mdelay(lcd_regs[i].delay);
201 /* Turn on Framebuffer Upload Mode */
202 mxsfb_write_byte(0x22, 0);
204 writel(LCDIF_CTRL_LCDIF_MASTER | LCDIF_CTRL_DATA_SELECT,
205 ®s->hw_lcdif_ctrl_set);
211 /* Adress of boot parameters */
212 gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
214 /* Turn on PWM backlight */
215 gpio_direction_output(MX23_PAD_PWM2__GPIO_1_28, 1);
220 int board_eth_init(bd_t *bis)
222 usb_eth_initialize(bis);