qemu/roms/u-boot/board/amcc/sequoia/sequoia.c

   1 /*
   2  * (C) Copyright 2006-2009
   3  * Stefan Roese, DENX Software Engineering, sr@denx.de.
   4  *
   5  * (C) Copyright 2006
   6  * Jacqueline Pira-Ferriol, AMCC/IBM, jpira-ferriol@fr.ibm.com
   7  * Alain Saurel,            AMCC/IBM, alain.saurel@fr.ibm.com
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <libfdt.h>
  14 #include <fdt_support.h>
  15 #include <asm/ppc4xx.h>
  16 #include <asm/ppc4xx-gpio.h>
  17 #include <asm/processor.h>
  18 #include <asm/io.h>
  19 #include <asm/bitops.h>
  20
  21 DECLARE_GLOBAL_DATA_PTR;
  22
  23 #if !defined(CONFIG_SYS_NO_FLASH)
  24 extern flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; /* info for FLASH chips */
  25 #endif
  26
  27 extern void __ft_board_setup(void *blob, bd_t *bd);
  28 ulong flash_get_size(ulong base, int banknum);
  29
  30 static inline u32 get_async_pci_freq(void)
  31 {
  32         if (in_8((void *)(CONFIG_SYS_BCSR_BASE + 5)) &
  33                 CONFIG_SYS_BCSR5_PCI66EN)
  34                 return 66666666;
  35         else
  36                 return 33333333;
  37 }
  38
  39 int board_early_init_f(void)
  40 {
  41         u32 sdr0_cust0;
  42         u32 sdr0_pfc1, sdr0_pfc2;
  43         u32 reg;
  44
  45         mtdcr(EBC0_CFGADDR, EBC0_CFG);
  46         mtdcr(EBC0_CFGDATA, 0xb8400000);
  47
  48         /*
  49          * Setup the interrupt controller polarities, triggers, etc.
  50          */
  51         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  52         mtdcr(UIC0ER, 0x00000000);      /* disable all */
  53         mtdcr(UIC0CR, 0x00000005);      /* ATI & UIC1 crit are critical */
  54         mtdcr(UIC0PR, 0xfffff7ff);      /* per ref-board manual */
  55         mtdcr(UIC0TR, 0x00000000);      /* per ref-board manual */
  56         mtdcr(UIC0VR, 0x00000000);      /* int31 highest, base=0x000 */
  57         mtdcr(UIC0SR, 0xffffffff);      /* clear all */
  58
  59         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  60         mtdcr(UIC1ER, 0x00000000);      /* disable all */
  61         mtdcr(UIC1CR, 0x00000000);      /* all non-critical */
  62         mtdcr(UIC1PR, 0xffffffff);      /* per ref-board manual */
  63         mtdcr(UIC1TR, 0x00000000);      /* per ref-board manual */
  64         mtdcr(UIC1VR, 0x00000000);      /* int31 highest, base=0x000 */
  65         mtdcr(UIC1SR, 0xffffffff);      /* clear all */
  66
  67         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  68         mtdcr(UIC2ER, 0x00000000);      /* disable all */
  69         mtdcr(UIC2CR, 0x00000000);      /* all non-critical */
  70         mtdcr(UIC2PR, 0xffffffff);      /* per ref-board manual */
  71         mtdcr(UIC2TR, 0x00000000);      /* per ref-board manual */
  72         mtdcr(UIC2VR, 0x00000000);      /* int31 highest, base=0x000 */
  73         mtdcr(UIC2SR, 0xffffffff);      /* clear all */
  74
  75         /* Check and reconfigure the PCI sync clock if necessary */
  76         ppc4xx_pci_sync_clock_config(get_async_pci_freq());
  77
  78         /* 50MHz tmrclk */
  79         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x04, 0x00);
  80
  81         /* clear write protects */
  82         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x07, 0x00);
  83
  84         /* enable Ethernet */
  85         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x08, 0x00);
  86
  87         /* enable USB device */
  88         out_8((u8 *) CONFIG_SYS_BCSR_BASE + 0x09, 0x20);
  89
  90         /* select Ethernet (and optionally IIC1) pins */
  91         mfsdr(SDR0_PFC1, sdr0_pfc1);
  92         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_SELECT_MASK) |
  93                 SDR0_PFC1_SELECT_CONFIG_4;
  94 #ifdef CONFIG_I2C_MULTI_BUS
  95         sdr0_pfc1 |= ((sdr0_pfc1 & ~SDR0_PFC1_SIS_MASK) | SDR0_PFC1_SIS_IIC1_SEL);
  96 #endif
  97         /* Two UARTs, so we need 4-pin mode.  Also, we want CTS/RTS mode. */
  98         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0IM_MASK) | SDR0_PFC1_U0IM_4PINS;
  99         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U0ME_MASK) | SDR0_PFC1_U0ME_CTS_RTS;
 100         sdr0_pfc1 = (sdr0_pfc1 & ~SDR0_PFC1_U1ME_MASK) | SDR0_PFC1_U1ME_CTS_RTS;
 101
 102         mfsdr(SDR0_PFC2, sdr0_pfc2);
 103         sdr0_pfc2 = (sdr0_pfc2 & ~SDR0_PFC2_SELECT_MASK) |
 104                 SDR0_PFC2_SELECT_CONFIG_4;
 105         mtsdr(SDR0_PFC2, sdr0_pfc2);
 106         mtsdr(SDR0_PFC1, sdr0_pfc1);
 107
 108         /* PCI arbiter enabled */
 109         mfsdr(SDR0_PCI0, reg);
 110         mtsdr(SDR0_PCI0, 0x80000000 | reg);
 111
 112         /* setup NAND FLASH */
 113         mfsdr(SDR0_CUST0, sdr0_cust0);
 114         sdr0_cust0 = SDR0_CUST0_MUX_NDFC_SEL    |
 115                 SDR0_CUST0_NDFC_ENABLE          |
 116                 SDR0_CUST0_NDFC_BW_8_BIT        |
 117                 SDR0_CUST0_NDFC_ARE_MASK        |
 118                 (0x80000000 >> (28 + CONFIG_SYS_NAND_CS));
 119         mtsdr(SDR0_CUST0, sdr0_cust0);
 120
 121         return 0;
 122 }
 123
 124 int misc_init_r(void)
 125 {
 126 #if !defined(CONFIG_SYS_NO_FLASH)
 127         uint pbcr;
 128         int size_val = 0;
 129 #endif
 130 #ifdef CONFIG_440EPX
 131         unsigned long usb2d0cr = 0;
 132         unsigned long usb2phy0cr, usb2h0cr = 0;
 133         unsigned long sdr0_pfc1;
 134         char *act = getenv("usbact");
 135 #endif
 136         u32 reg;
 137
 138 #if !defined(CONFIG_SYS_NO_FLASH)
 139         /* Re-do flash sizing to get full correct info */
 140
 141         /* adjust flash start and offset */
 142         gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize;
 143         gd->bd->bi_flashoffset = 0;
 144
 145 #if defined(CONFIG_SYS_RAMBOOT)
 146         mtdcr(EBC0_CFGADDR, PB3CR);
 147 #else
 148         mtdcr(EBC0_CFGADDR, PB0CR);
 149 #endif
 150         pbcr = mfdcr(EBC0_CFGDATA);
 151         size_val = ffs(gd->bd->bi_flashsize) - 21;
 152         pbcr = (pbcr & 0x0001ffff) | gd->bd->bi_flashstart | (size_val << 17);
 153 #if defined(CONFIG_SYS_RAMBOOT)
 154         mtdcr(EBC0_CFGADDR, PB3CR);
 155 #else
 156         mtdcr(EBC0_CFGADDR, PB0CR);
 157 #endif
 158         mtdcr(EBC0_CFGDATA, pbcr);
 159
 160         /*
 161          * Re-check to get correct base address
 162          */
 163         flash_get_size(gd->bd->bi_flashstart, 0);
 164
 165 #ifdef CONFIG_ENV_IS_IN_FLASH
 166         /* Monitor protection ON by default */
 167         (void)flash_protect(FLAG_PROTECT_SET,
 168                             -CONFIG_SYS_MONITOR_LEN,
 169                             0xffffffff,
 170                             &flash_info[0]);
 171
 172         /* Env protection ON by default */
 173         (void)flash_protect(FLAG_PROTECT_SET,
 174                             CONFIG_ENV_ADDR_REDUND,
 175                             CONFIG_ENV_ADDR_REDUND + 2*CONFIG_ENV_SECT_SIZE - 1,
 176                             &flash_info[0]);
 177 #endif
 178 #endif /* CONFIG_SYS_NO_FLASH */
 179
 180         /*
 181          * USB suff...
 182          */
 183 #ifdef CONFIG_440EPX
 184         if (act == NULL || strcmp(act, "hostdev") == 0) {
 185                 /* SDR Setting */
 186                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 187                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 188                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 189                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 190
 191                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 192                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 193                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 194                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_16BIT_30MHZ;
 195                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 196                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 197                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 198                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 199                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 200                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 201
 202                 /*
 203                  * An 8-bit/60MHz interface is the only possible alternative
 204                  * when connecting the Device to the PHY
 205                  */
 206                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 207                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_16BIT_30MHZ;
 208
 209                 /*
 210                  * To enable the USB 2.0 Device function
 211                  * through the UTMI interface
 212                  */
 213                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 214                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_USB2DEV_SELECTION;
 215
 216                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 217                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_USB2D_SEL;
 218
 219                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 220                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 221                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 222                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 223
 224                 /*clear resets*/
 225                 udelay (1000);
 226                 mtsdr(SDR0_SRST1, 0x00000000);
 227                 udelay (1000);
 228                 mtsdr(SDR0_SRST0, 0x00000000);
 229
 230                 printf("USB:   Host(int phy) Device(ext phy)\n");
 231
 232         } else if (strcmp(act, "dev") == 0) {
 233                 /*-------------------PATCH-------------------------------*/
 234                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 235
 236                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 237                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 238                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 239                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PURDIS;
 240                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 241                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_HOST;
 242                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 243                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_HOST;
 244                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 245
 246                 udelay (1000);
 247                 mtsdr(SDR0_SRST1, 0x672c6000);
 248
 249                 udelay (1000);
 250                 mtsdr(SDR0_SRST0, 0x00000080);
 251
 252                 udelay (1000);
 253                 mtsdr(SDR0_SRST1, 0x60206000);
 254
 255                 *(unsigned int *)(0xe0000350) = 0x00000001;
 256
 257                 udelay (1000);
 258                 mtsdr(SDR0_SRST1, 0x60306000);
 259                 /*-------------------PATCH-------------------------------*/
 260
 261                 /* SDR Setting */
 262                 mfsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 263                 mfsdr(SDR0_USB2H0CR, usb2h0cr);
 264                 mfsdr(SDR0_USB2D0CR, usb2d0cr);
 265                 mfsdr(SDR0_PFC1, sdr0_pfc1);
 266
 267                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_XOCLK_MASK;
 268                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_XOCLK_EXTERNAL;
 269                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_WDINT_MASK;
 270                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_WDINT_8BIT_60MHZ;
 271                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DVBUS_MASK;
 272                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DVBUS_PUREN;
 273                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_DWNSTR_MASK;
 274                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_DWNSTR_DEV;
 275                 usb2phy0cr = usb2phy0cr &~SDR0_USB2PHY0CR_UTMICN_MASK;
 276                 usb2phy0cr = usb2phy0cr | SDR0_USB2PHY0CR_UTMICN_DEV;
 277
 278                 usb2h0cr   = usb2h0cr &~SDR0_USB2H0CR_WDINT_MASK;
 279                 usb2h0cr   = usb2h0cr | SDR0_USB2H0CR_WDINT_8BIT_60MHZ;
 280
 281                 usb2d0cr = usb2d0cr &~SDR0_USB2D0CR_USB2DEV_EBC_SEL_MASK;
 282                 usb2d0cr = usb2d0cr | SDR0_USB2D0CR_EBC_SELECTION;
 283
 284                 sdr0_pfc1 = sdr0_pfc1 &~SDR0_PFC1_UES_MASK;
 285                 sdr0_pfc1 = sdr0_pfc1 | SDR0_PFC1_UES_EBCHR_SEL;
 286
 287                 mtsdr(SDR0_USB2H0CR, usb2h0cr);
 288                 mtsdr(SDR0_USB2PHY0CR, usb2phy0cr);
 289                 mtsdr(SDR0_USB2D0CR, usb2d0cr);
 290                 mtsdr(SDR0_PFC1, sdr0_pfc1);
 291
 292                 /* clear resets */
 293                 udelay (1000);
 294                 mtsdr(SDR0_SRST1, 0x00000000);
 295                 udelay (1000);
 296                 mtsdr(SDR0_SRST0, 0x00000000);
 297
 298                 printf("USB:   Device(int phy)\n");
 299         }
 300 #endif /* CONFIG_440EPX */
 301
 302         mfsdr(SDR0_SRST1, reg);         /* enable security/kasumi engines */
 303         reg &= ~(SDR0_SRST1_CRYP0 | SDR0_SRST1_KASU0);
 304         mtsdr(SDR0_SRST1, reg);
 305
 306         /*
 307          * Clear PLB4A0_ACR[WRP]
 308          * This fix will make the MAL burst disabling patch for the Linux
 309          * EMAC driver obsolete.
 310          */
 311         reg = mfdcr(PLB4A0_ACR) & ~PLB4Ax_ACR_WRP_MASK;
 312         mtdcr(PLB4A0_ACR, reg);
 313
 314         return 0;
 315 }
 316
 317 int checkboard(void)
 318 {
 319         char buf[64];
 320         int i = getenv_f("serial#", buf, sizeof(buf));
 321         u8 rev;
 322         u32 clock = get_async_pci_freq();
 323
 324 #ifdef CONFIG_440EPX
 325         printf("Board: Sequoia - AMCC PPC440EPx Evaluation Board");
 326 #else
 327         printf("Board: Rainier - AMCC PPC440GRx Evaluation Board");
 328 #endif
 329
 330         rev = in_8((void *)(CONFIG_SYS_BCSR_BASE + 0));
 331         printf(", Rev. %X, PCI-Async=%d MHz", rev, clock / 1000000);
 332
 333         if (i > 0) {
 334                 puts(", serial# ");
 335                 puts(buf);
 336         }
 337         putc('\n');
 338
 339         /*
 340          * Reconfiguration of the PCI sync clock is already done,
 341          * now check again if everything is in range:
 342          */
 343         if (ppc4xx_pci_sync_clock_config(clock)) {
 344                 printf("ERROR: PCI clocking incorrect (async=%d "
 345                        "sync=%ld)!\n", clock, get_PCI_freq());
 346         }
 347
 348         return (0);
 349 }
 350
 351 #if defined(CONFIG_PCI) && defined(CONFIG_PCI_PNP)
 352 /*
 353  * Assign interrupts to PCI devices.
 354  */
 355 void board_pci_fixup_irq(struct pci_controller *hose, pci_dev_t dev)
 356 {
 357         pci_hose_write_config_byte(hose, dev, PCI_INTERRUPT_LINE, VECNUM_EIRQ2);
 358 }
 359 #endif
 360
 361 #if defined(CONFIG_SYS_RAMBOOT)
 362 /*
 363  * On NAND-booting sequoia, we need to patch the chips select numbers
 364  * in the dtb (CS0 - NAND, CS3 - NOR)
 365  */
 366 void ft_board_setup(void *blob, bd_t *bd)
 367 {
 368         int rc;
 369         int len;
 370         int nodeoffset;
 371         struct fdt_property *prop;
 372         u32 *reg;
 373         char path[32];
 374
 375         /* First do common fdt setup */
 376         __ft_board_setup(blob, bd);
 377
 378         /* And now configure NOR chip select to 3 instead of 0 */
 379         strcpy(path, "/plb/opb/ebc/nor_flash@0,0");
 380         nodeoffset = fdt_path_offset(blob, path);
 381         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 382         if (prop == NULL) {
 383                 printf("Unable to update NOR chip select for NAND booting\n");
 384                 return;
 385         }
 386         reg = (u32 *)&prop->data[0];
 387         reg[0] = 3;
 388         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 389         if (rc) {
 390                 printf("Unable to update property NOR mappings, err=%s\n",
 391                        fdt_strerror(rc));
 392                 return;
 393         }
 394
 395         /* And now configure NAND chip select to 0 instead of 3 */
 396         strcpy(path, "/plb/opb/ebc/ndfc@3,0");
 397         nodeoffset = fdt_path_offset(blob, path);
 398         prop = fdt_get_property_w(blob, nodeoffset, "reg", &len);
 399         if (prop == NULL) {
 400                 printf("Unable to update NDFC chip select for NAND booting\n");
 401                 return;
 402         }
 403         reg = (u32 *)&prop->data[0];
 404         reg[0] = 0;
 405         rc = fdt_find_and_setprop(blob, path, "reg", reg, 3 * sizeof(u32), 1);
 406         if (rc) {
 407                 printf("Unable to update property NDFC mappings, err=%s\n",
 408                        fdt_strerror(rc));
 409                 return;
 410         }
 411 }
 412 #endif /* CONFIG_SYS_RAMBOOT */