2 * MCF5441X Internal Memory Map
4 * Copyright 2010-2012 Freescale Semiconductor, Inc.
5 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
7 * SPDX-License-Identifier: GPL-2.0+
13 /* Interrupt Controller (INTC) */
14 #define INT0_LO_RSVD0 (0)
15 #define INT0_LO_EPORT1 (1)
16 #define INT0_LO_EPORT2 (2)
17 #define INT0_LO_EPORT3 (3)
18 #define INT0_LO_EPORT4 (4)
19 #define INT0_LO_EPORT5 (5)
20 #define INT0_LO_EPORT6 (6)
21 #define INT0_LO_EPORT7 (7)
22 #define INT0_LO_EDMA_00 (8)
23 #define INT0_LO_EDMA_01 (9)
24 #define INT0_LO_EDMA_02 (10)
25 #define INT0_LO_EDMA_03 (11)
26 #define INT0_LO_EDMA_04 (12)
27 #define INT0_LO_EDMA_05 (13)
28 #define INT0_LO_EDMA_06 (14)
29 #define INT0_LO_EDMA_07 (15)
30 #define INT0_LO_EDMA_08 (16)
31 #define INT0_LO_EDMA_09 (17)
32 #define INT0_LO_EDMA_10 (18)
33 #define INT0_LO_EDMA_11 (19)
34 #define INT0_LO_EDMA_12 (20)
35 #define INT0_LO_EDMA_13 (21)
36 #define INT0_LO_EDMA_14 (22)
37 #define INT0_LO_EDMA_15 (23)
38 #define INT0_LO_EDMA_ERR (24)
39 #define INT0_LO_SCM (25)
40 #define INT0_LO_UART0 (26)
41 #define INT0_LO_UART1 (27)
42 #define INT0_LO_UART2 (28)
43 #define INT0_LO_UART3 (29)
44 #define INT0_LO_I2C0 (30)
45 #define INT0_LO_DSPI0 (31)
46 #define INT0_HI_DTMR0 (32)
47 #define INT0_HI_DTMR1 (33)
48 #define INT0_HI_DTMR2 (34)
49 #define INT0_HI_DTMR3 (35)
50 #define INT0_HI_MACNET0_TXF (36)
51 #define INT0_HI_MACNET0_TXB (37)
52 #define INT0_HI_MACNET0_UN (38)
53 #define INT0_HI_MACNET0_RL (39)
54 #define INT0_HI_MACNET0_RXF (40)
55 #define INT0_HI_MACNET0_RXB (41)
56 #define INT0_HI_MACNET0_MII (42)
57 #define INT0_HI_MACNET0_LC (43)
59 #define INT0_HI_MACNET0_GRA (45)
60 #define INT0_HI_MACNET0_EBERR (46)
61 #define INT0_HI_MACNET0_BABT (47)
62 #define INT0_HI_MACNET0_BABR (48)
63 #define INT0_HI_MACNET1_TXF (49)
64 #define INT0_HI_MACNET1_TXB (50)
65 #define INT0_HI_MACNET1_UN (51)
66 #define INT0_HI_MACNET1_RL (52)
67 #define INT0_HI_MACNET1_RXF (53)
68 #define INT0_HI_MACNET1_RXB (54)
69 #define INT0_HI_MACNET1_MII (55)
70 #define INT0_HI_MACNET1_LC (56)
72 #define INT0_HI_MACNET1_GRA (58)
73 #define INT0_HI_MACNET1_EBERR (59)
74 #define INT0_HI_MACNET1_BABT (60)
75 #define INT0_HI_MACNET1_BABR (61)
76 #define INT0_HI_SCMIR (62)
77 #define INT0_HI_OW (63)
79 #define INT1_LO_CAN0_IFG (0)
80 #define INT1_LO_CAN0_BOFF (1)
82 #define INT1_LO_CAN0_TXRXWRN (3)
83 #define INT1_LO_CAN1_IFG (4)
84 #define INT1_LO_CAN1_BOFF (5)
86 #define INT1_LO_CAN1_TXRXWRN (7)
87 #define INT1_LO_EDMA_16 (8)
88 #define INT1_LO_EDMA_17 (9)
89 #define INT1_LO_EDMA_18 (10)
90 #define INT1_LO_EDMA_19 (11)
91 #define INT1_LO_EDMA_20 (12)
92 #define INT1_LO_EDMA_21 (13)
93 #define INT1_LO_EDMA_22 (14)
94 #define INT1_LO_EDMA_23 (15)
95 #define INT1_LO_EDMA_24 (16)
96 #define INT1_LO_EDMA_25 (17)
97 #define INT1_LO_EDMA_26 (18)
98 #define INT1_LO_EDMA_27 (19)
99 #define INT1_LO_EDMA_28 (20)
100 #define INT1_LO_EDMA_29 (21)
101 #define INT1_LO_EDMA_30 (22)
102 #define INT1_LO_EDMA_31 (23)
103 #define INT1_LO_EDMA_32 (24)
104 #define INT1_LO_EDMA_33 (25)
105 #define INT1_LO_EDMA_34 (26)
106 #define INT1_LO_EDMA_35 (27)
107 #define INT1_LO_EDMA_36 (28)
108 #define INT1_LO_EDMA_37 (29)
109 #define INT1_LO_EDMA_38 (30)
110 #define INT1_LO_EDMA_39 (31)
111 #define INT1_LO_EDMA_40 (32)
112 #define INT1_HI_EDMA_41 (33)
113 #define INT1_HI_EDMA_42 (34)
114 #define INT1_HI_EDMA_43 (35)
115 #define INT1_HI_EDMA_44 (36)
116 #define INT1_HI_EDMA_45 (37)
117 #define INT1_HI_EDMA_46 (38)
118 #define INT1_HI_EDMA_47 (39)
119 #define INT1_HI_EDMA_48 (40)
120 #define INT1_HI_EDMA_49 (41)
121 #define INT1_HI_EDMA_50 (42)
122 #define INT1_HI_EDMA_51 (43)
123 #define INT1_HI_EDMA_52 (44)
124 #define INT1_HI_EDMA_53 (45)
125 #define INT1_HI_EDMA_54 (46)
126 #define INT1_HI_EDMA_55 (47)
127 #define INT1_HI_UART4 (48)
128 #define INT1_HI_UART5 (49)
129 #define INT1_HI_UART6 (50)
130 #define INT1_HI_UART7 (51)
131 #define INT1_HI_UART8 (52)
132 #define INT1_HI_UART9 (53)
133 #define INT1_HI_DSPI1 (54)
134 #define INT1_HI_DSPI2 (55)
135 #define INT1_HI_DSPI3 (56)
136 #define INT1_HI_I2C1 (57)
137 #define INT1_HI_I2C2 (58)
138 #define INT1_HI_I2C3 (59)
139 #define INT1_HI_I2C4 (60)
140 #define INT1_HI_I2C5 (61)
142 #define INT2_LO_EDMA56_63 (0)
143 #define INT2_LO_PWM_SM0SR_CF (1)
144 #define INT2_LO_PWM_SM1SR_CF (2)
145 #define INT2_LO_PWM_SM2SR_CF (3)
146 #define INT2_LO_PWM_SM3SR_CF (4)
147 #define INT2_LO_PWM_SM0SR_RF (5)
148 #define INT2_LO_PWM_SM1SR_RF (6)
149 #define INT2_LO_PWM_SM2SR_RF (7)
150 #define INT2_LO_PWM_SM3SR_RF (8)
151 #define INT2_LO_PWM_FSR (9)
152 #define INT2_LO_PWM_SMSR_REF (10)
153 #define INT2_LO_PLL_SR_LOCF (11)
154 #define INT2_LO_PLL_SR_LOLF (12)
155 #define INT2_LO_PIT0_PIF (13)
156 #define INT2_LO_PIT1_PIF (14)
157 #define INT2_LO_PIT2_PIF (15)
158 #define INT2_LO_PIT3_PIF (16)
159 #define INT2_LO_USBOTG_USBSTS (17)
160 #define INT2_LO_USBH_USBSTS (18)
162 #define INT2_LO_SSI0 (21)
163 #define INT2_LO_SSI1 (22)
164 #define INT2_LO_NFC (23)
166 #define INT2_LO_RTC (26)
167 #define INT2_LO_CCM_UOCSR (27)
168 #define INT2_LO_RNG_EI (28)
169 #define INT2_LO_SIM1_DATA (29)
170 #define INT2_LO_SIM1 (30)
171 #define INT2_LO_SDHC (31)
173 #define INT2_HI_L2SW_BERR (38)
174 #define INT2_HI_L2SW_RXB (39)
175 #define INT2_HI_L2SW_RXF (40)
176 #define INT2_HI_L2SW_TXB (41)
177 #define INT2_HI_L2SW_TXF (42)
178 #define INT2_HI_L2SW_QM (43)
179 #define INT2_HI_L2SW_OD0 (44)
180 #define INT2_HI_L2SW_OD1 (45)
181 #define INT2_HI_L2SW_OD2 (46)
182 #define INT2_HI_L2SW_LRN (47)
183 #define INT2_HI_MACNET0_TS (48)
184 #define INT2_HI_MACNET0_WAKE (49)
185 #define INT2_HI_MACNET0_PLR (50)
187 #define INT2_HI_MACNET1_TS (51)
188 #define INT2_HI_MACNET1_WAKE (52)
189 #define INT2_HI_MACNET1_PLR (53)
191 /* Serial Boot Facility (SBF) */
192 #define SBF_SBFCR_BLDIV(x) (((x)&0x000F))
193 #define SBF_SBFCR_FR (0x0010)
195 /* Reset Controller Module (RCM) */
196 #define RCM_RCR_SOFTRST (0x80)
197 #define RCM_RCR_FRCRSTOUT (0x40)
199 #define RCM_RSR_SOFT (0x20)
200 #define RCM_RSR_LOC (0x10)
201 #define RCM_RSR_POR (0x08)
202 #define RCM_RSR_EXT (0x04)
203 #define RCM_RSR_WDR_CORE (0x02)
204 #define RCM_RSR_LOL (0x01)
206 /* Chip Configuration Module (CCM) */
207 #define CCM_CCR_BOOTMOD (0xC000)
208 #define CCM_CCR_PLLMULT (0x0FC0)
209 #define CCM_CCR_BOOTPS (0x0030)
210 #define CCM_CCR_BOOTPS_32 (0x0000)
211 #define CCM_CCR_BOOTPS_16 (0x0020)
212 #define CCM_CCR_BOOTPS_8 (0x0010)
213 #define CCM_CCR_BOOTPS_ (0x0000)
214 #define CCM_CCR_ALESEL (0x0008)
215 #define CCM_CCR_OSCMOD (0x0004)
216 #define CCM_CCR_PLLMOD (0x0002)
217 #define CCM_CCR_BOOTMEM (0x0001)
219 #define CCM_CIR_PIN_MASK (0xFFC0)
220 #define CCM_CIR_PRN_MASK (0x003F)
221 #define CCM_CIR_PIN_MCF54410 (0x9F<<6)
222 #define CCM_CIR_PIN_MCF54415 (0xA0<<6)
223 #define CCM_CIR_PIN_MCF54416 (0xA1<<6)
224 #define CCM_CIR_PIN_MCF54417 (0xA2<<6)
225 #define CCM_CIR_PIN_MCF54418 (0xA3<<6)
227 #define CCM_MISCCR_PWM_EXTCLK(x) (((x)&(0x0003)<<14)
228 #define CCM_MISCCR_PWM_EXTCLK_MASK (0x3FFF)
229 #define CCM_MISCCR_PWM_EXTCLK_TMR0 (0x0000)
230 #define CCM_MISCCR_PWM_EXTCLK_TMR1 (0x4000)
231 #define CCM_MISCCR_PWM_EXTCLK_TMR2 (0x8000)
232 #define CCM_MISCCR_PWM_EXTCLK_TMR3 (0xC000)
233 #define CCM_MISCCR_LIMP (0x1000)
234 #define CCM_MISCCR_BME (0x0800)
235 #define CCM_MISCCR_BMT(x) (((x)&0x0007)<<8)
236 #define CCM_MISCCR_BMT_65536 (0)
237 #define CCM_MISCCR_BMT_32768 (1)
238 #define CCM_MISCCR_BMT_16384 (2)
239 #define CCM_MISCCR_BMT_8192 (3)
240 #define CCM_MISCCR_BMT_4096 (4)
241 #define CCM_MISCCR_BMT_2048 (5)
242 #define CCM_MISCCR_BMT_1024 (6)
243 #define CCM_MISCCR_BMT_512 (7)
244 #define CCM_MISCCR_SDHCSRC (0x0040)
245 #define CCM_MISCCR_SSI1SRC (0x0020)
246 #define CCM_MISCCR_SSI0SRC (0x0010)
247 #define CCM_MISCCR_USBHOC (0x0008)
248 #define CCM_MISCCR_USBOOC (0x0004)
249 #define CCM_MISCCR_USBPUE (0x0002)
250 #define CCM_MISCCR_USBSRC (0x0001)
252 #define CCM_CDRH_SSI0DIV(x) (((x)&0x00FF)<<8)
253 #define CCM_CDRH_SSI0DIV_MASK (0x00FF)
254 #define CCM_CDRH_SSI1DIV(x) (((x)&0x00FF))
255 #define CCM_CDRH_SSI1DIV_MASK (0xFF00)
256 #define CCM_CDRL_LPDIV(x) (((x)&0x000F)<<8)
257 #define CCM_CDRL_LPDIV_MASK (0xFF0F)
258 #define CCM_CDR_LPDIV(x) CCM_CDRL_LPDIV(x)
260 #define CCM_UOCSR_DPPD (0x2000)
261 #define CCM_UOCSR_DMPD (0x1000)
262 #define CCM_UOCSR_DRV_VBUS (0x0800)
263 #define CCM_UOCSR_CRG_VBUS (0x0400)
264 #define CCM_UOCSR_DCR_VBUS (0x0200)
265 #define CCM_UOCSR_DPPU (0x0100)
266 #define CCM_UOCSR_AVLD (0x0080)
267 #define CCM_UOCSR_BVLD (0x0040)
268 #define CCM_UOCSR_VVLD (0x0020)
269 #define CCM_UOCSR_SEND (0x0010)
270 #define CCM_UOCSR_PWRFLT (0x0008)
271 #define CCM_UOCSR_WKUP (0x0004)
272 #define CCM_UOCSR_UOMIE (0x0002)
273 #define CCM_UOCSR_XPDE (0x0001)
275 #define CCM_UHCSR_DRV_VBUS (0x0010)
276 #define CCM_UHCSR_PWRFLT (0x0008)
277 #define CCM_UHCSR_WKUP (0x0004)
278 #define CCM_UHCSR_UOMIE (0x0002)
279 #define CCM_UHCSR_XPDE (0x0001)
281 #define CCM_MISCCR3_TMR_ENET (0x1000)
282 #define CCM_MISCCR3_ENETCLK(x) (((x)&7)<<8)
283 #define CCM_MISCCR3_ENETCLK_MASK (0xF8FF)
284 #define CCM_MISCCR3_ENETCLK_MII (0x0700)
285 #define CCM_MISCCR3_ENETCLK_OSC (0x0600)
286 #define CCM_MISCCR3_ENETCLK_USB (0x0500)
287 #define CCM_MISCCR3_ENETCLK_TMR3 (0x0400)
288 #define CCM_MISCCR3_ENETCLK_TMR2 (0x0300)
289 #define CCM_MISCCR3_ENETCLK_TMR1 (0x0200)
290 #define CCM_MISCCR3_ENETCLK_TMR0 (0x0100)
291 #define CCM_MISCCR3_ENETCLK_INTBUS (0x0000)
293 #define CCM_MISCCR2_EXTCLKBYP (0x8000)
294 #define CCM_MISCCR2_DDR2CLK (0x4000)
295 #define CCM_MISCCR2_RGPIO_HALF (0x2000)
296 #define CCM_MISCCR2_SWTSCR (0x1000)
297 #define CCM_MISCCR2_PLLMODE(x) (((x)&7)<<8)
298 #define CCM_MISCCR2_PLLMODE_MASK (0xF8FF)
299 #define CCM_MISCCR2_DCCBYP (0x0080)
300 #define CCM_MISCCR2_DAC1SEL (0x0040)
301 #define CCM_MISCCR2_DAC0SEL (0x0020)
302 #define CCM_MISCCR2_ADCEN (0x0010)
303 #define CCM_MISCCR2_ADC7SEL (0x0008)
304 #define CCM_MISCCR2_ADC3SEL (0x0004)
305 #define CCM_MISCCR2_FBHALF (0x0002)
306 #define CCM_MISCCR2_ULPI (0x0001)
308 #define CCM_FNACR_PCR(x) (((x)&0x0F)<<24)
309 #define CCM_FNACR_PCR_MASK (0xF0FFFFFF)
310 #define CCM_FNACR_MCC(x) ((x)&0xFFFF)
311 #define CCM_FNACR_MCC_MASK (0xFFFF0000)
313 /* General Purpose I/O Module (GPIO) */
314 #define GPIO_PAR_FBCTL_ALE(x) (((x)&3)<<6)
315 #define GPIO_PAR_FBCTL_ALE_MASK (0x3F)
316 #define GPIO_PAR_FBCTL_ALE_FB_ALE (0xC0)
317 #define GPIO_PAR_FBCTL_ALE_FB_TS (0x80)
318 #define GPIO_PAR_FBCTL_ALE_GPIO (0x00)
319 #define GPIO_PAR_FBCTL_OE(x) (((x)&3)<<4)
320 #define GPIO_PAR_FBCTL_OE_MASK (0xCF)
321 #define GPIO_PAR_FBCTL_OE_FB_OE (0x30)
322 #define GPIO_PAR_FBCTL_OE_FB_TBST (0x20)
323 #define GPIO_PAR_FBCTL_OE_NFC_RE (0x20)
324 #define GPIO_PAR_FBCTL_OE_GPIO (0x00)
325 #define GPIO_PAR_FBCTL_FBCLK (0x08)
326 #define GPIO_PAR_FBCTL_RW (0x04)
327 #define GPIO_PAR_FBCTL_TA(x) ((x)&3)
328 #define GPIO_PAR_FBCTL_TA_MASK (0xFC)
329 #define GPIO_PAR_FBCTL_TA_TA (0x03)
330 #define GPIO_PAR_FBCTL_TA_NFC_RB (0x01)
331 #define GPIO_PAR_FBCTL_TA_GPIO (0x00)
333 #define GPIO_PAR_BE_BS3(x) (((x)&0x03)<<6)
334 #define GPIO_PAR_BE_BE3_MASK (0x3F)
335 #define GPIO_PAR_BE_BE3_BE3 (0xC0)
336 #define GPIO_PAR_BE_BE3_CS3 (0x80)
337 #define GPIO_PAR_BE_BE3_FB_A1 (0x40)
338 #define GPIO_PAR_BE_BE3_NFC_ALE (0x40)
339 #define GPIO_PAR_BE_BE3_GPIO (0x00)
340 #define GPIO_PAR_BE_BS2(x) (((x)&0x03)<<4)
341 #define GPIO_PAR_BE_BE2_MASK (0xCF)
342 #define GPIO_PAR_BE_BE2_BE2 (0x30)
343 #define GPIO_PAR_BE_BE2_CS2 (0x20)
344 #define GPIO_PAR_BE_BE2_FB_A0 (0x10)
345 #define GPIO_PAR_BE_BE2_NFC_CLE (0x10)
346 #define GPIO_PAR_BE_BE2_GPIO (0x00)
347 #define GPIO_PAR_BE_BS1(x) (((x)&0x03)<<2)
348 #define GPIO_PAR_BE_BE1_MASK (0xF3)
349 #define GPIO_PAR_BE_BE1_BE1 (0x0C)
350 #define GPIO_PAR_BE_BE1_FB_TSZ1 (0x08)
351 #define GPIO_PAR_BE_BE1_GPIO (0x00)
352 #define GPIO_PAR_BE_BS0(x) ((x)&0x03)
353 #define GPIO_PAR_BE_BE0_MASK (0xFC)
354 #define GPIO_PAR_BE_BE0_BE0 (0x03)
355 #define GPIO_PAR_BE_BE0_FB_TSZ0 (0x02)
356 #define GPIO_PAR_BE_BE0_GPIO (0x00)
358 #define GPIO_PAR_CS_CS5(x) (((x)&0x03)<<6)
359 #define GPIO_PAR_CS_CS5_MASK (0x3F)
360 #define GPIO_PAR_CS_CS5_CS5 (0xC0)
361 #define GPIO_PAR_CS_CS5_DACK1 (0x80)
362 #define GPIO_PAR_CS_CS5_GPIO (0x00)
363 #define GPIO_PAR_CS_CS4(x) (((x)&0x03)<<4)
364 #define GPIO_PAR_CS_CS4_MASK (0xCF)
365 #define GPIO_PAR_CS_CS4_CS4 (0x30)
366 #define GPIO_PAR_CS_CS4_DREQ1 (0x20)
367 #define GPIO_PAR_CS_CS4_GPIO (0x00)
368 #define GPIO_PAR_CS_CS1(x) (((x)&0x03)<<2)
369 #define GPIO_PAR_CS_CS1_MASK (0xF3)
370 #define GPIO_PAR_CS_CS1_CS1 (0x0C)
371 #define GPIO_PAR_CS_CS1_NFC_CE (0x04)
372 #define GPIO_PAR_CS_CS1_GPIO (0x00)
373 #define GPIO_PAR_CS_CS0_CS0 (0x01)
375 #define GPIO_PAR_CANI2C_I2C0SCL(x) (((x)&0x03)<<6)
376 #define GPIO_PAR_CANI2C_I2C0SCL_MASK (0x3F)
377 #define GPIO_PAR_CANI2C_I2C0SCL_I2C0SCL (0xC0)
378 #define GPIO_PAR_CANI2C_I2C0SCL_U8TXD (0x80)
379 #define GPIO_PAR_CANI2C_I2C0SCL_CAN0TX (0x40)
380 #define GPIO_PAR_CANI2C_I2C0SCL_GPIO (0x00)
381 #define GPIO_PAR_CANI2C_I2C0SDA(x) (((x)&0x03)<<4)
382 #define GPIO_PAR_CANI2C_I2C0SDA_MASK (0xCF)
383 #define GPIO_PAR_CANI2C_I2C0SDA_I2C0SDA (0x30)
384 #define GPIO_PAR_CANI2C_I2C0SDA_U8RXD (0x20)
385 #define GPIO_PAR_CANI2C_I2C0SDA_CAN0RX (0x10)
386 #define GPIO_PAR_CANI2C_I2C0SDA_GPIO (0x00)
387 #define GPIO_PAR_CANI2C_CAN1TX(x) (((x)&0x03)<<2)
388 #define GPIO_PAR_CANI2C_CAN1TX_MASK (0xF3)
389 #define GPIO_PAR_CANI2C_CAN1TX_CAN1TX (0x0C)
390 #define GPIO_PAR_CANI2C_CAN1TX_U9TXD (0x08)
391 #define GPIO_PAR_CANI2C_CAN1TX_I2C1SCL (0x04)
392 #define GPIO_PAR_CANI2C_CAN1TX_GPIO (0x00)
393 #define GPIO_PAR_CANI2C_CAN1RX(x) ((x)&0x03)
394 #define GPIO_PAR_CANI2C_CAN1RX_MASK (0xFC)
395 #define GPIO_PAR_CANI2C_CAN1RX_CAN1RX (0x03)
396 #define GPIO_PAR_CANI2C_CAN1RX_U9RXD (0x02)
397 #define GPIO_PAR_CANI2C_CAN1RX_I2C1SDA (0x01)
398 #define GPIO_PAR_CANI2C_CAN1RX_GPIO (0x00)
400 #define GPIO_PAR_IRQH_IRQ7 (0x10)
401 #define GPIO_PAR_IRQH_IRQ4(x) (((x)&0x03)<<2)
402 #define GPIO_PAR_IRQH_IRQ4_MASK (0xF3)
403 #define GPIO_PAR_IRQH_IRQ4_IRQ4 (0x0C)
404 #define GPIO_PAR_IRQH_IRQ4_DREQ0 (0x08)
405 #define GPIO_PAR_IRQH_IRQ4_GPIO (0x00)
406 #define GPIO_PAR_IRQH_IRQ1 (0x03)
408 #define GPIO_PAR_IRQL_IRQ6(x) (((x)&0x03)<<6)
409 #define GPIO_PAR_IRQL_IRQ6_MASK (0x3F)
410 #define GPIO_PAR_IRQL_IRQ6_IRQ6 (0xC0)
411 #define GPIO_PAR_IRQL_IRQ6_USBCLKIN (0x40)
412 #define GPIO_PAR_IRQL_IRQ6_GPIO (0x00)
413 #define GPIO_PAR_IRQL_IRQ3(x) (((x)&0x03)<<4)
414 #define GPIO_PAR_IRQL_IRQ3_MASK (0xCF)
415 #define GPIO_PAR_IRQL_IRQ3_IRQ3 (0x30)
416 #define GPIO_PAR_IRQL_IRQ3_DSPI0_PCS3 (0x20)
417 #define GPIO_PAR_IRQL_IRQ3_USB1_VBUS_EN (0x10)
418 #define GPIO_PAR_IRQL_IRQ3_GPIO (0x00)
419 #define GPIO_PAR_IRQL_IRQ2(x) (((x)&0x03)<<2)
420 #define GPIO_PAR_IRQL_IRQ2_MASK (0xF3)
421 #define GPIO_PAR_IRQL_IRQ2_IRQ2 (0x0C)
422 #define GPIO_PAR_IRQL_IRQ2_DSPI0_PCS2 (0x08)
423 #define GPIO_PAR_IRQL_IRQ2_USB1_VBUS_OC (0x04)
424 #define GPIO_PAR_IRQL_IRQ2_GPIO (0x00)
426 #define GPIO_PAR_DSPI0_SIN(x) (((x)&0x03)<<6)
427 #define GPIO_PAR_DSPI0_SIN_MASK (0x3F)
428 #define GPIO_PAR_DSPI0_SIN_DSPI0SIN (0xC0)
429 #define GPIO_PAR_DSPI0_SIN_SBF_DI (0xC0)
430 #define GPIO_PAR_DSPI0_SIN_U3RXD (0x80)
431 #define GPIO_PAR_DSPI0_SIN_SDHC_CMD (0x40)
432 #define GPIO_PAR_DSPI0_SIN_GPIO (0x00)
433 #define GPIO_PAR_DSPI0_SOUT(x) (((x)&0x03)<<4)
434 #define GPIO_PAR_DSPI0_SOUT_MASK (0xCF)
435 #define GPIO_PAR_DSPI0_SOUT_DSPI0SOUT (0x30)
436 #define GPIO_PAR_DSPI0_SOUT_SBF_DO (0x30)
437 #define GPIO_PAR_DSPI0_SOUT_U3TXD (0x20)
438 #define GPIO_PAR_DSPI0_SOUT_SDHC_DAT0 (0x10)
439 #define GPIO_PAR_DSPI0_SOUT_GPIO (0x00)
440 #define GPIO_PAR_DSPI0_SCK(x) (((x)&0x03)<<2)
441 #define GPIO_PAR_DSPI0_SCK_MASK (0xF3)
442 #define GPIO_PAR_DSPI0_SCK_DSPI0SCK (0x0C)
443 #define GPIO_PAR_DSPI0_SCK_SBF_CK (0x0C)
444 #define GPIO_PAR_DSPI0_SCK_I2C3SCL (0x08)
445 #define GPIO_PAR_DSPI0_SCK_SDHC_CLK (0x04)
446 #define GPIO_PAR_DSPI0_SCK_GPIO (0x00)
447 #define GPIO_PAR_DSPI0_PCS0(x) ((x)&0x03)
448 #define GPIO_PAR_DSPI0_PCS0_MASK (0xFC)
449 #define GPIO_PAR_DSPI0_PCS0_DSPI0PCS0 (0x03)
450 #define GPIO_PAR_DSPI0_PCS0_SS (0x03)
451 #define GPIO_PAR_DSPI0_PCS0_I2C3SDA (0x02)
452 #define GPIO_PAR_DSPI0_PCS0_SDHC_DAT3 (0x01)
453 #define GPIO_PAR_DSPI0_PCS0_GPIO (0x00)
455 #define GPIO_PAR_DSPIOW_DSPI0PSC1 (0x80)
456 #define GPIO_PAR_DSPIOW_SBF_CS (0x80)
457 #define GPIO_PAR_DSPIOW_OWDAT (((x)&0x03)<<4)
458 #define GPIO_PAR_DSPIOW_OWDAT_MASK (0xCF)
459 #define GPIO_PAR_DSPIOW_OWDAT_OWDAT (0x30)
460 #define GPIO_PAR_DSPIOW_OWDAT_DACK0 (0x20)
461 #define GPIO_PAR_DSPIOW_OWDAT_GPIO (0x00)
463 #define GPIO_PAR_TIMER_T3IN(x) (((x)&0x03)<<6)
464 #define GPIO_PAR_TIMER_T3IN_MASK (0x3F)
465 #define GPIO_PAR_TIMER_T3IN_T3IN (0xC0)
466 #define GPIO_PAR_TIMER_T3IN_EXTA3 (0xC0)
467 #define GPIO_PAR_TIMER_T3IN_T3OUT (0x80)
468 #define GPIO_PAR_TIMER_T3IN_USB0_VBUSEN (0x40)
469 #define GPIO_PAR_TIMER_T3IN_ULIPI_DIR (0x40)
470 #define GPIO_PAR_TIMER_T3IN_GPIO (0x00)
471 #define GPIO_PAR_TIMER_T2IN(x) (((x)&0x03)<<4)
472 #define GPIO_PAR_TIMER_T2IN_MASK (0xCF)
473 #define GPIO_PAR_TIMER_T2IN_T2IN (0x30)
474 #define GPIO_PAR_TIMER_T2IN_EXTA2 (0x30)
475 #define GPIO_PAR_TIMER_T2IN_T2OUT (0x20)
476 #define GPIO_PAR_TIMER_T2IN_SDHC_DAT2 (0x10)
477 #define GPIO_PAR_TIMER_T2IN_GPIO (0x00)
478 #define GPIO_PAR_TIMER_T1IN(x) (((x)&0x03)<<2)
479 #define GPIO_PAR_TIMER_T1IN_MASK (0xF3)
480 #define GPIO_PAR_TIMER_T1IN_T1IN (0x0C)
481 #define GPIO_PAR_TIMER_T1IN_EXTA1 (0x0C)
482 #define GPIO_PAR_TIMER_T1IN_T1OUT (0x08)
483 #define GPIO_PAR_TIMER_T1IN_SDHC_DAT1 (0x04)
484 #define GPIO_PAR_TIMER_T1IN_GPIO (0x00)
485 #define GPIO_PAR_TIMER_T0IN(x) ((x)&0x03)
486 #define GPIO_PAR_TIMER_T0IN_MASK (0xFC)
487 #define GPIO_PAR_TIMER_T0IN_T0IN (0x03)
488 #define GPIO_PAR_TIMER_T0IN_EXTA0 (0x03)
489 #define GPIO_PAR_TIMER_T0IN_T0OUT (0x02)
490 #define GPIO_PAR_TIMER_T0IN_USBO_VBUSOC (0x01)
491 #define GPIO_PAR_TIMER_T0IN_ULPI_NXT (0x01)
492 #define GPIO_PAR_TIMER_T0IN_GPIO (0x00)
494 #define GPIO_PAR_UART2_U2CTS(x) (((x)&0x03)<<6)
495 #define GPIO_PAR_UART2_U2CTS_MASK (0x3F)
496 #define GPIO_PAR_UART2_U2CTS_U2CTS (0xC0)
497 #define GPIO_PAR_UART2_U2CTS_U6TXD (0x80)
498 #define GPIO_PAR_UART2_U2CTS_SSI1_BCLK (0x40)
499 #define GPIO_PAR_UART2_U2CTS_GPIO (0x00)
500 #define GPIO_PAR_UART2_U2RTS(x) (((x)&0x03)<<4)
501 #define GPIO_PAR_UART2_U2RTS_MASK (0xCF)
502 #define GPIO_PAR_UART2_U2RTS_U2RTS (0x30)
503 #define GPIO_PAR_UART2_U2RTS_U6RXD (0x20)
504 #define GPIO_PAR_UART2_U2RTS_SSI1_FS (0x10)
505 #define GPIO_PAR_UART2_U2RTS_GPIO (0x00)
506 #define GPIO_PAR_UART2_U2RXD(x) (((x)&0x03)<<2)
507 #define GPIO_PAR_UART2_U2RXD_MASK (0xF3)
508 #define GPIO_PAR_UART2_U2RXD_U2RXD (0x0C)
509 #define GPIO_PAR_UART2_U2RXD_PWM_A3 (0x08)
510 #define GPIO_PAR_UART2_U2RXD_SSI1_RXD (0x04)
511 #define GPIO_PAR_UART2_U2RXD_GPIO (0x00)
512 #define GPIO_PAR_UART2_U2TXD(x) ((x)&0x03)
513 #define GPIO_PAR_UART2_U2TXD_MASK (0xFC)
514 #define GPIO_PAR_UART2_U2TXD_U2TXD (0x03)
515 #define GPIO_PAR_UART2_U2TXD_PWM_B3 (0x02)
516 #define GPIO_PAR_UART2_U2TXD_SSI1_TXD (0x01)
517 #define GPIO_PAR_UART2_U2TXD_GPIO (0x00)
519 #define GPIO_PAR_UART1_U1CTS(x) (((x)&0x03)<<6)
520 #define GPIO_PAR_UART1_U1CTS_MASK (0x3F)
521 #define GPIO_PAR_UART1_U1CTS_U1CTS (0xC0)
522 #define GPIO_PAR_UART1_U1CTS_U5TXD (0x80)
523 #define GPIO_PAR_UART1_U1CTS_DSPI3_SCK (0x40)
524 #define GPIO_PAR_UART1_U1CTS_GPIO (0x00)
525 #define GPIO_PAR_UART1_U1RTS(x) (((x)&0x03)<<4)
526 #define GPIO_PAR_UART1_U1RTS_MASK (0xCF)
527 #define GPIO_PAR_UART1_U1RTS_U1RTS (0x30)
528 #define GPIO_PAR_UART1_U1RTS_U5RXD (0x20)
529 #define GPIO_PAR_UART1_U1RTS_DSPI3_PCS0 (0x10)
530 #define GPIO_PAR_UART1_U1RTS_GPIO (0x00)
531 #define GPIO_PAR_UART1_U1RXD(x) (((x)&0x03)<<2)
532 #define GPIO_PAR_UART1_U1RXD_MASK (0xF3)
533 #define GPIO_PAR_UART1_U1RXD_U1RXD (0x0C)
534 #define GPIO_PAR_UART1_U1RXD_I2C5SDA (0x08)
535 #define GPIO_PAR_UART1_U1RXD_DSPI3_SIN (0x04)
536 #define GPIO_PAR_UART1_U1RXD_GPIO (0x00)
537 #define GPIO_PAR_UART1_U1TXD(x) ((x)&0x03)
538 #define GPIO_PAR_UART1_U1TXD_MASK (0xFC)
539 #define GPIO_PAR_UART1_U1TXD_U1TXD (0x03)
540 #define GPIO_PAR_UART1_U1TXD_I2C5SCL (0x02)
541 #define GPIO_PAR_UART1_U1TXD_DSPI3_SOUT (0x01)
542 #define GPIO_PAR_UART1_U1TXD_GPIO (0x00)
544 #define GPIO_PAR_UART0_U0CTS(x) (((x)&0x03)<<6)
545 #define GPIO_PAR_UART0_U0CTS_MASK (0x3F)
546 #define GPIO_PAR_UART0_U0CTS_U0CTS (0xC0)
547 #define GPIO_PAR_UART0_U0CTS_U4TXD (0x80)
548 #define GPIO_PAR_UART0_U0CTS_DSPI2_SCK (0x40)
549 #define GPIO_PAR_UART0_U0CTS_GPIO (0x00)
550 #define GPIO_PAR_UART0_U0RTS(x) (((x)&0x03)<<4)
551 #define GPIO_PAR_UART0_U0RTS_MASK (0xCF)
552 #define GPIO_PAR_UART0_U0RTS_U0RTS (0x30)
553 #define GPIO_PAR_UART0_U0RTS_U4RXD (0x20)
554 #define GPIO_PAR_UART0_U0RTS_DSPI2_PCS0 (0x10)
555 #define GPIO_PAR_UART0_U0RTS_GPIO (0x00)
556 #define GPIO_PAR_UART0_U0RXD(x) (((x)&0x03)<<2)
557 #define GPIO_PAR_UART0_U0RXD_MASK (0xF3)
558 #define GPIO_PAR_UART0_U0RXD_U0RXD (0x0C)
559 #define GPIO_PAR_UART0_U0RXD_I2C4SDA (0x08)
560 #define GPIO_PAR_UART0_U0RXD_DSPI2_SIN (0x04)
561 #define GPIO_PAR_UART0_U0RXD_GPIO (0x00)
562 #define GPIO_PAR_UART0_U0TXD(x) ((x)&0x03)
563 #define GPIO_PAR_UART0_U0TXD_MASK (0xFC)
564 #define GPIO_PAR_UART0_U0TXD_U0TXD (0x03)
565 #define GPIO_PAR_UART0_U0TXD_I2C4SCL (0x02)
566 #define GPIO_PAR_UART0_U0TXD_DSPI2_SOUT (0x01)
567 #define GPIO_PAR_UART0_U0TXD_GPIO (0x00)
569 #define GPIO_PAR_SDHCH_DAT3(x) (((x)&0x03)<<6)
570 #define GPIO_PAR_SDHCH_DAT3_MASK (0x3F)
571 #define GPIO_PAR_SDHCH_DAT3_DAT3 (0xC0)
572 #define GPIO_PAR_SDHCH_DAT3_PWM_A1 (0x80)
573 #define GPIO_PAR_SDHCH_DAT3_DSPI1_PCS0 (0x40)
574 #define GPIO_PAR_SDHCH_DAT3_GPIO (0x00)
575 #define GPIO_PAR_SDHCH_DAT2(x) (((x)&0x03)<<4)
576 #define GPIO_PAR_SDHCH_DAT2_MASK (0xCF)
577 #define GPIO_PAR_SDHCH_DAT2_DAT2 (0x30)
578 #define GPIO_PAR_SDHCH_DAT2_PWM_B1 (0x20)
579 #define GPIO_PAR_SDHCH_DAT2_DSPI1_PCS2 (0x10)
580 #define GPIO_PAR_SDHCH_DAT2_GPIO (0x00)
581 #define GPIO_PAR_SDHCH_DAT1(x) (((x)&0x03)<<2)
582 #define GPIO_PAR_SDHCH_DAT1_MASK (0xF3)
583 #define GPIO_PAR_SDHCH_DAT1_DAT1 (0x0C)
584 #define GPIO_PAR_SDHCH_DAT1_PWM_A2 (0x08)
585 #define GPIO_PAR_SDHCH_DAT1_DSPI1_PCS1 (0x04)
586 #define GPIO_PAR_SDHCH_DAT1_GPIO (0x00)
587 #define GPIO_PAR_SDHCH_DAT0(x) ((x)&0x03)
588 #define GPIO_PAR_SDHCH_DAT0_MASK (0xFC)
589 #define GPIO_PAR_SDHCH_DAT0_DAT0 (0x03)
590 #define GPIO_PAR_SDHCH_DAT0_PWM_B2 (0x02)
591 #define GPIO_PAR_SDHCH_DAT0_DSPI1_SOUT (0x01)
592 #define GPIO_PAR_SDHCH_DAT0_GPIO (0x00)
594 #define GPIO_PAR_SDHCL_CMD(x) (((x)&0x03)<<2)
595 #define GPIO_PAR_SDHCL_CMD_MASK (0xF3)
596 #define GPIO_PAR_SDHCL_CMD_CMD (0x0C)
597 #define GPIO_PAR_SDHCL_CMD_PWM_A0 (0x08)
598 #define GPIO_PAR_SDHCL_CMD_DSPI1_SIN (0x04)
599 #define GPIO_PAR_SDHCL_CMD_GPIO (0x00)
600 #define GPIO_PAR_SDHCL_CLK(x) ((x)&0x03)
601 #define GPIO_PAR_SDHCL_CLK_MASK (0xFC)
602 #define GPIO_PAR_SDHCL_CLK_CLK (0x03)
603 #define GPIO_PAR_SDHCL_CLK_PWM_B0 (0x02)
604 #define GPIO_PAR_SDHCL_CLK_DSPI1_SCK (0x01)
605 #define GPIO_PAR_SDHCL_CLK_GPIO (0x00)
607 #define GPIO_PAR_SIMP0H_DAT(x) (((x)&0x03)<<6)
608 #define GPIO_PAR_SIMP0H_DAT_MASK (0x3F)
609 #define GPIO_PAR_SIMP0H_DAT_DAT (0xC0)
610 #define GPIO_PAR_SIMP0H_DAT_PWM_FAULT2 (0x80)
611 #define GPIO_PAR_SIMP0H_DAT_SDHC_DAT7 (0x40)
612 #define GPIO_PAR_SIMP0H_DAT_GPIO (0x00)
613 #define GPIO_PAR_SIMP0H_VEN(x) (((x)&0x03)<<4)
614 #define GPIO_PAR_SIMP0H_VEN_MASK (0xCF)
615 #define GPIO_PAR_SIMP0H_VEN_VEN (0x30)
616 #define GPIO_PAR_SIMP0H_VEN_PWM_FAULT0 (0x20)
617 #define GPIO_PAR_SIMP0H_VEN_GPIO (0x00)
618 #define GPIO_PAR_SIMP0H_RST(x) (((x)&0x03)<<2)
619 #define GPIO_PAR_SIMP0H_RST_MASK (0xF3)
620 #define GPIO_PAR_SIMP0H_RST_RST (0x0C)
621 #define GPIO_PAR_SIMP0H_RST_PWM_FORCE (0x08)
622 #define GPIO_PAR_SIMP0H_RST_SDHC_DAT6 (0x04)
623 #define GPIO_PAR_SIMP0H_RST_GPIO (0x00)
624 #define GPIO_PAR_SIMP0H_PD(x) ((x)&0x03)
625 #define GPIO_PAR_SIMP0H_PD_MASK (0xFC)
626 #define GPIO_PAR_SIMP0H_PD_PD (0x03)
627 #define GPIO_PAR_SIMP0H_PD_PWM_SYNC (0x02)
628 #define GPIO_PAR_SIMP0H_PD_SDHC_DAT5 (0x01)
629 #define GPIO_PAR_SIMP0H_PD_GPIO (0x00)
631 #define GPIO_PAR_SIMP0L_CLK(x) ((x)&0x03)
632 #define GPIO_PAR_SIMP0L_CLK_MASK (0xFC)
633 #define GPIO_PAR_SIMP0L_CLK_CLK (0x03)
634 #define GPIO_PAR_SIMP0L_CLK_PWM_FAULT1 (0x02)
635 #define GPIO_PAR_SIMP0L_CLK_SDHC_DAT4 (0x01)
636 #define GPIO_PAR_SIMP0L_CLK_GPIO (0x00)
638 #define GPIO_PAR_SSI0H_RXD(x) (((x)&0x03)<<6)
639 #define GPIO_PAR_SSI0H_RXD_MASK (0x3F)
640 #define GPIO_PAR_SSI0H_RXD_RXD (0xC0)
641 #define GPIO_PAR_SSI0H_RXD_I2C2SDA (0x80)
642 #define GPIO_PAR_SSI0H_RXD_SIM1_VEN (0x40)
643 #define GPIO_PAR_SSI0H_RXD_GPIO (0x00)
644 #define GPIO_PAR_SSI0H_TXD(x) (((x)&0x03)<<4)
645 #define GPIO_PAR_SSI0H_TXD_MASK (0xCF)
646 #define GPIO_PAR_SSI0H_TXD_TXD (0x30)
647 #define GPIO_PAR_SSI0H_TXD_I2C2SCL (0x20)
648 #define GPIO_PAR_SSI0H_TXD_SIM1_DAT (0x10)
649 #define GPIO_PAR_SSI0H_TXD_GPIO (0x00)
650 #define GPIO_PAR_SSI0H_FS(x) (((x)&0x03)<<2)
651 #define GPIO_PAR_SSI0H_FS_MASK (0xF3)
652 #define GPIO_PAR_SSI0H_FS_FS (0x0C)
653 #define GPIO_PAR_SSI0H_FS_U7TXD (0x08)
654 #define GPIO_PAR_SSI0H_FS_SIM1_RST (0x04)
655 #define GPIO_PAR_SSI0H_FS_GPIO (0x00)
656 #define GPIO_PAR_SSI0H_MCLK(x) ((x)&0x03)
657 #define GPIO_PAR_SSI0H_MCLK_MASK (0xFC)
658 #define GPIO_PAR_SSI0H_MCLK_MCLK (0x03)
659 #define GPIO_PAR_SSI0H_MCLK_SSI_CLKIN (0x02)
660 #define GPIO_PAR_SSI0H_MCLK_SIM1_CLK (0x01)
661 #define GPIO_PAR_SSI0H_MCLK_GPIO (0x00)
663 #define GPIO_PAR_SSI0L_BCLK(x) ((x)&0x03)
664 #define GPIO_PAR_SSI0L_BCLK_MASK (0xFC)
665 #define GPIO_PAR_SSI0L_BCLK_BCLK (0x03)
666 #define GPIO_PAR_SSI0L_BCLK_U7RXD (0x02)
667 #define GPIO_PAR_SSI0L_BCLK_SIM1_PD (0x01)
668 #define GPIO_PAR_SSI0L_BCLK_GPIO (0x00)
670 #define GPIO_PAR_DEBUGH1_DAT3 (0x40)
671 #define GPIO_PAR_DEBUGH1_DAT2 (0x10)
672 #define GPIO_PAR_DEBUGH1_DAT1 (0x04)
673 #define GPIO_PAR_DEBUGH1_DAT0 (0x01)
675 #define GPIO_PAR_DEBUGH0_PST3 (0x40)
676 #define GPIO_PAR_DEBUGH0_PST2 (0x10)
677 #define GPIO_PAR_DEBUGH0_PST1 (0x04)
678 #define GPIO_PAR_DEBUGH0_PST0 (0x01)
680 #define GPIO_PODR_G4_VAL (0x01 << 4)
681 #define GPIO_PODR_G4_MASK (0xff & ~GPIO_PODR_G4_VAL)
682 #define GPIO_PDDR_G4_OUTPUT (0x01 << 4)
683 #define GPIO_PDDR_G4_MASK (0xff & ~GPIO_PDDR_G4_OUTPUT)
685 #define GPIO_PAR_DEBUGL_ALLPST (0x01)
687 #define GPIO_PAR_FEC_FEC(x) ((x)&0x0F)
688 #define GPIO_PAR_FEC_FEC_MASK (0xF0)
689 #define GPIO_PAR_FEC_FEC_GPIO (0x0D)
690 #define GPIO_PAR_FEC_FEC_RMII1 (0x0C)
691 #define GPIO_PAR_FEC_FEC_RMII1FUL (0x0B)
692 #define GPIO_PAR_FEC_FEC_RMII_ULPI (0x0A)
693 #define GPIO_PAR_FEC_FEC_RMII0 (0x09)
694 #define GPIO_PAR_FEC_FEC_RMII0FUL_ULPI (0x08)
695 #define GPIO_PAR_FEC_FEC_RMII0FUL (0x07)
696 #define GPIO_PAR_FEC_FEC_RMII0_1FUL (0x06)
697 #define GPIO_PAR_FEC_FEC_RMII0FUL_1 (0x05) /* 0:Full 1: */
698 /* Both 0&1: MDC, MDIO, COL & TXER - GPIO */
699 #define GPIO_PAR_FEC_FEC_RMII0_1 (0x04)
700 #define GPIO_PAR_FEC_FEC_RMII0FUL_1FUL (0x03)
701 #define GPIO_PAR_FEC_FEC_MII (0x01) /* MDC & MDIO - GPIO */
702 #define GPIO_PAR_FEC_FEC_MIIFUL (0x00)
705 /* TC: Need to edit here.... */
707 /* Mode Select Control */
708 #define GPIO_MSCR_SDRAM_MSC(x) ((x)&0x03)
709 #define GPIO_MSCR_SDRAM_MSC_MASK (0xFC)
711 /* Slew Rate Control */
713 #define GPIO_SRCR_FB3_FB3(x) ((x)&0x03)
714 #define GPIO_SRCR_FB3_FB3_MASK (0xFC)
716 #define GPIO_SRCR_FB2_FB2(x) ((x)&0x03)
717 #define GPIO_SRCR_FB2_FB2_MASK (0xFC)
719 #define GPIO_SRCR_FB1_FB1(x) ((x)&0x03)
720 #define GPIO_SRCR_FB1_FB1_MASK (0xFC)
722 #define GPIO_SRCR_FB4_FB5(x) (((x)&0x03)<<2)
723 #define GPIO_SRCR_FB4_FB5_MASK (0xF3)
724 #define GPIO_SRCR_FB4_FB4(x) ((x)&0x03)
725 #define GPIO_SRCR_FB4_FB4_MASK (0xFC)
727 #define GPIO_SRCR_DSPIOW_OWDAT(x) (((x)&0x03)<<4)
728 #define GPIO_SRCR_DSPIOW_OWDAT_MASK (0xCF)
729 #define GPIO_SRCR_DSPIOW_DSPI0(x) ((x)&0x03)
730 #define GPIO_SRCR_DSPIOW_DSPI0_MASK (0xFC)
732 #define GPIO_SRCR_CANI2C_CAN1(x) (((x)&0x03)<<2)
733 #define GPIO_SRCR_CANI2C_CAN1_MASK (0xF3)
734 #define GPIO_SRCR_CANI2C_I2C0(x) ((x)&0x03)
735 #define GPIO_SRCR_CANI2C_I2C0_MASK (0xFC)
737 #define GPIO_SRCR_IRQ0_IRQ0(x) ((x)&0x03)
738 #define GPIO_SRCR_IRQ0_IRQ0_MASK (0xFC)
740 #define GPIO_SRCR_TIMER_TMR3(x) (((x)&0x03)<<6)
741 #define GPIO_SRCR_TIMER_TMR3_MASK (0x3F)
742 #define GPIO_SRCR_TIMER_TMR2(x) (((x)&0x03)<<4)
743 #define GPIO_SRCR_TIMER_TMR2_MASK (0xCF)
744 #define GPIO_SRCR_TIMER_TMR1(x) (((x)&0x03)<<2)
745 #define GPIO_SRCR_TIMER_TMR1_MASK (0xF3)
746 #define GPIO_SRCR_TIMER_TMR0(x) ((x)&0x03)
747 #define GPIO_SRCR_TIMER_TMR0_MASK (0xFC)
749 #define GPIO_SRCR_UART_U2(x) (((x)&0x03)<<4)
750 #define GPIO_SRCR_UART_U2_MASK (0xCF)
751 #define GPIO_SRCR_UART_U1(x) (((x)&0x03)<<2)
752 #define GPIO_SRCR_UART_U1_MASK (0xF3)
753 #define GPIO_SRCR_UART_U0(x) ((x)&0x03)
754 #define GPIO_SRCR_UART_U0_MASK (0xFC)
756 #define GPIO_SRCR_FEC_RMII0(x) (((x)&0x03)<<2)
757 #define GPIO_SRCR_FEC_RMII0_MASK (0xF3)
758 #define GPIO_SRCR_FEC_RMII1(x) ((x)&0x03)
759 #define GPIO_SRCR_FEC_RMII1_MASK (0xFC)
761 #define GPIO_SRCR_SDHC_SDHC(x) ((x)&0x03)
762 #define GPIO_SRCR_SDHC_SDHC_MASK (0xFC)
764 #define GPIO_SRCR_SIM0_SIMP0(x) ((x)&0x03)
765 #define GPIO_SRCR_SIM0_SIMP0_MASK (0xFC)
767 #define GPIO_SRCR_SSI0_SSI0(x) ((x)&0x03)
768 #define GPIO_SRCR_SSI0_SSI0_MASK (0xFC)
770 #define GPIO_PCR_URTS_U2 (0x0004)
771 #define GPIO_PCR_URTS_U1 (0x0002)
772 #define GPIO_PCR_URTS_U0 (0x0001)
774 #define GPIO_PCR_UCTS_U2 (0x0004)
775 #define GPIO_PCR_UCTS_U1 (0x0002)
776 #define GPIO_PCR_UCTS_U0 (0x0001)
778 #define GPIO_UTXD_WOM_U9 (0x0200)
779 #define GPIO_UTXD_WOM_U8 (0x0100)
780 #define GPIO_UTXD_WOM_U7 (0x0080)
781 #define GPIO_UTXD_WOM_U6 (0x0040)
782 #define GPIO_UTXD_WOM_U5 (0x0020)
783 #define GPIO_UTXD_WOM_U4 (0x0010)
784 #define GPIO_UTXD_WOM_U3 (0x0008)
785 #define GPIO_UTXD_WOM_U2 (0x0004)
786 #define GPIO_UTXD_WOM_U1 (0x0002)
787 #define GPIO_UTXD_WOM_U0 (0x0001)
789 #define GPIO_URXD_WOM_U9(x) (((x)&3)<<18)
790 #define GPIO_URXD_WOM_U9_MASK (0xFFF3FFFF)
791 #define GPIO_URXD_WOM_U8(x) (((x)&3)<<16)
792 #define GPIO_URXD_WOM_U8_MASK (0xFFFCFFFF)
793 #define GPIO_URXD_WOM_U7(x) (((x)&3)<<14)
794 #define GPIO_URXD_WOM_U7_MASK (0xFFFF3FFF)
795 #define GPIO_URXD_WOM_U6(x) (((x)&3)<<12)
796 #define GPIO_URXD_WOM_U6_MASK (0xFFFFCFFF)
797 #define GPIO_URXD_WOM_U5(x) (((x)&3)<<10)
798 #define GPIO_URXD_WOM_U5_MASK (0xFFFFF3FF)
799 #define GPIO_URXD_WOM_U4(x) (((x)&3)<<8)
800 #define GPIO_URXD_WOM_U4_MASK (0xFFFFFCFF)
801 #define GPIO_URXD_WOM_U3(x) (((x)&3)<<6)
802 #define GPIO_URXD_WOM_U3_MASK (0xFFFFFF3F)
803 #define GPIO_URXD_WOM_U2(x) (((x)&3)<<4)
804 #define GPIO_URXD_WOM_U2_MASK (0xFFFFFFCF)
805 #define GPIO_URXD_WOM_U1(x) (((x)&3)<<2)
806 #define GPIO_URXD_WOM_U1_MASK (0xFFFFFFF3)
807 #define GPIO_URXD_WOM_U0(x) ((x)&3)
808 #define GPIO_URXD_WOM_U0_MASK (0xFFFFFFFC)
810 #define GPIO_HCR1_PG4_0(x) (((x)&0x1F)<<27)
811 #define GPIO_HCR1_PG4_0_MASK (0x07FFFFFF)
812 #define GPIO_HCR1_PF7_3(x) (((x)&0x1F)<<22)
813 #define GPIO_HCR1_PF7_3_MASK (0xF83FFFFF)
814 #define GPIO_HCR1_PE6_0(x) (((x)&0x7F)<<15)
815 #define GPIO_HCR1_PE6_0_MASK (0xFFC07FFF)
816 #define GPIO_HCR1_PD7_3(x) (((x)&0x1F)<<10)
817 #define GPIO_HCR1_PD7_3_MASK (0xFFFF83FF)
818 #define GPIO_HCR1_PC7_1(x) (((x)&0x7F)<<3)
819 #define GPIO_HCR1_PC7_1_MASK (0xFFFFFC07)
820 #define GPIO_HCR1_PB2_0(x) ((x)&7)
821 #define GPIO_HCR1_PB2_0_MASK (0xFFFFFFF8)
823 #define GPIO_HCR0_PK3 (0x00000400)
824 #define GPIO_HCR0_PK0 (0x00000200)
825 #define GPIO_HCR0_PD2_0(x) (((x)&7)<<6)
826 #define GPIO_HCR0_PD2_0_MASK (0xFFFFFE3F)
827 #define GPIO_HCR0_PE7 (0x00000020)
828 #define GPIO_HCR0_PH7_3(x) ((x)&0x1F)
829 #define GPIO_HCR0_PH7_3_MASK(x) (0xFFFFFFE0)
831 /* SDRAM Controller (SDRAMC) */
833 /* Phase Locked Loop (PLL) */
834 #define PLL_CR_LOCIRQ (0x00040000)
835 #define PLL_CR_LOCRE (0x00020000)
836 #define PLL_CR_LOCEN (0x00010000)
837 #define PLL_CR_LOLIRQ (0x00004000)
838 #define PLL_CR_LOLRE (0x00002000)
839 #define PLL_CR_LOLEN (0x00001000)
840 #define PLL_CR_REFDIV(x) (((x)&7)<<8)
841 #define PLL_CR_REFDIV_MASK (0xFFFFF8FF)
842 #define PLL_CR_FBKDIV(x) ((x)&0x3F)
843 #define PLL_CR_FBKDIV_MASK (0xFFFFFFC0)
844 #define PLL_CR_FBKDIV_BITS (0x3F)
846 #define PLL_DR_OUTDIV5(x) (((x)&0x1F)<<21)
847 #define PLL_DR_OUTDIV5_MASK (0xFC1FFFFF)
848 #define PLL_DR_OUTDIV5_BITS (0x03E00000)
849 #define PLL_DR_OUTDIV4(x) (((x)&0x1F)<<16)
850 #define PLL_DR_OUTDIV4_MASK (0xFFE0FFFF)
851 #define PLL_DR_OUTDIV4_BITS (0x001F0000)
852 #define PLL_DR_OUTDIV3(x) (((x)&0x1F)<<10)
853 #define PLL_DR_OUTDIV3_MASK (0xFFFF83FF)
854 #define PLL_DR_OUTDIV3_BITS (0x00007C00)
855 #define PLL_DR_OUTDIV2(x) (((x)&0x1F)<<5)
856 #define PLL_DR_OUTDIV2_MASK (0xFFFFFC1F)
857 #define PLL_DR_OUTDIV2_BITS (0x000003E0)
858 #define PLL_DR_OUTDIV1(x) ((x)&0x1F)
859 #define PLL_DR_OUTDIV1_MASK (0xFFFFFFE0)
860 #define PLL_DR_OUTDIV1_BITS (0x0000001F)
862 #define PLL_SR_LOCF (0x00000200)
863 #define PLL_SR_LOC (0x00000100)
864 #define PLL_SR_LOLF (0x00000040)
865 #define PLL_SR_LOCKS (0x00000020)
866 #define PLL_SR_LOCK (0x00000010)
867 #define PLL_PSR_LOCK PLL_SR_LOCK /* compatible with 5x */
868 #define PLL_SR_MODE(x) ((x)&7)
869 #define PLL_SR_MODE_MASK (0xFFFFFFF8)
871 #endif /* __MCF5441X__ */
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