qemu/roms/u-boot/arch/arm/include/asm/arch-at91/at91_dbu.h

   1 /*
   2  * Copyright (C) 2010
   3  * Reinhard Meyer, reinhard.meyer@emk-elektronik.de
   4  *
   5  * Debug Unit
   6  * Based on AT91SAM9XE datasheet
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef AT91_DBU_H
  12 #define AT91_DBU_H
  13
  14 #ifndef __ASSEMBLY__
  15
  16 typedef struct at91_dbu {
  17         u32     cr;     /* Control Register WO */
  18         u32     mr;     /* Mode Register  RW */
  19         u32     ier;    /* Interrupt Enable Register WO */
  20         u32     idr;    /* Interrupt Disable Register WO */
  21         u32     imr;    /* Interrupt Mask Register RO */
  22         u32     sr;     /* Status Register RO */
  23         u32     rhr;    /* Receive Holding Register RO */
  24         u32     thr;    /* Transmit Holding Register WO */
  25         u32     brgr;   /* Baud Rate Generator Register RW */
  26         u32     res1[7];/* 0x0024 - 0x003C Reserved */
  27         u32     cidr;   /* Chip ID Register RO */
  28         u32     exid;   /* Chip ID Extension Register RO */
  29         u32     fnr;    /* Force NTRST Register RW */
  30 } at91_dbu_t;
  31
  32 #endif /* __ASSEMBLY__ */
  33
  34 #define AT91_DBU_CID_ARCH_MASK          0x0ff00000
  35 #define AT91_DBU_CID_ARCH_9xx           0x01900000
  36 #define AT91_DBU_CID_ARCH_9XExx 0x02900000
  37
  38 #define AT91_DBU_CIDR_MASK              0x1f
  39 #define AT91_DBU_CIDR                   0x40
  40 #define AT91_DBU_EXID                   0x44
  41
  42 #endif