2 * Clock setup for SMDK5250 board based on EXYNOS5
4 * Copyright (C) 2012 Samsung Electronics
6 * SPDX-License-Identifier: GPL-2.0+
12 #include <asm/arch/clk.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch/spl.h>
15 #include <asm/arch/dwmmc.h>
17 #include "clock_init.h"
18 #include "common_setup.h"
19 #include "exynos5_setup.h"
21 #define FSYS1_MMC0_DIV_MASK 0xff0f
22 #define FSYS1_MMC0_DIV_VAL 0x0701
24 DECLARE_GLOBAL_DATA_PTR;
26 struct arm_clk_ratios arm_clk_ratios[] = {
27 #ifdef CONFIG_EXYNOS5420
37 .pclk_dbg_ratio = 0x6,
54 .pclk_dbg_ratio = 0x1,
69 .pclk_dbg_ratio = 0x1,
84 .pclk_dbg_ratio = 0x1,
99 .pclk_dbg_ratio = 0x1,
106 .arm_freq_mhz = 1400,
114 .pclk_dbg_ratio = 0x1,
121 .arm_freq_mhz = 1700,
129 .pclk_dbg_ratio = 0x1,
139 struct mem_timings mem_timings[] = {
140 #ifdef CONFIG_EXYNOS5420
142 .mem_manuf = MEM_MANUF_SAMSUNG,
143 .mem_type = DDR_MODE_DDR3,
144 .frequency_mhz = 800,
184 0x00020018, 0x00030000, 0x00010046, 0x00000d70,
187 .timing_ref = 0x000000bb,
188 .timing_row = 0x6836650f,
189 .timing_data = 0x3630580b,
190 .timing_power = 0x41000a26,
191 .phy0_dqs = 0x08080808,
192 .phy1_dqs = 0x08080808,
193 .phy0_dq = 0x08080808,
194 .phy1_dq = 0x08080808,
197 .phy0_pulld_dqs = 0xf,
198 .phy1_pulld_dqs = 0xf,
200 .lpddr3_ctrl_phy_reset = 0x1,
201 .ctrl_start_point = 0x10,
223 * Dynamic Clock: Always Running
224 * Memory Burst length: 8
226 * Memory Bus width: 32 bit
228 * Additional Latancy for PLL: 0 Cycle
230 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
231 DMC_MEMCONTROL_DPWRDN_DISABLE |
232 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
233 DMC_MEMCONTROL_TP_DISABLE |
234 DMC_MEMCONTROL_DSREF_DISABLE |
235 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
236 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
237 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
238 DMC_MEMCONTROL_NUM_CHIP_1 |
239 DMC_MEMCONTROL_BL_8 |
240 DMC_MEMCONTROL_PZQ_DISABLE |
241 DMC_MEMCONTROL_MRR_BYTE_7_0,
242 .memconfig = DMC_MEMCONFIG_CHIP_MAP_SPLIT |
243 DMC_MEMCONFIGX_CHIP_COL_10 |
244 DMC_MEMCONFIGX_CHIP_ROW_15 |
245 DMC_MEMCONFIGX_CHIP_BANK_8,
246 .prechconfig_tp_cnt = 0xff,
249 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
250 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
251 DMC_CONCONTROL_RD_FETCH_DISABLE |
252 DMC_CONCONTROL_EMPTY_DISABLE |
253 DMC_CONCONTROL_AREF_EN_DISABLE |
254 DMC_CONCONTROL_IO_PD_CON_DISABLE,
256 .chips_per_channel = 1,
257 .chips_to_configure = 1,
259 .gate_leveling_enable = 1,
260 .read_leveling_enable = 0,
264 .mem_manuf = MEM_MANUF_ELPIDA,
265 .mem_type = DDR_MODE_DDR3,
266 .frequency_mhz = 800,
286 .pclk_cdrex_ratio = 0x5,
288 0x00020018, 0x00030000, 0x00010042, 0x00000d70
290 .timing_ref = 0x000000bb,
291 .timing_row = 0x8c36650e,
292 .timing_data = 0x3630580b,
293 .timing_power = 0x41000a44,
294 .phy0_dqs = 0x08080808,
295 .phy1_dqs = 0x08080808,
296 .phy0_dq = 0x08080808,
297 .phy1_dq = 0x08080808,
300 .phy0_pulld_dqs = 0xf,
301 .phy1_pulld_dqs = 0xf,
303 .lpddr3_ctrl_phy_reset = 0x1,
304 .ctrl_start_point = 0x10,
326 * Dynamic Clock: Always Running
327 * Memory Burst length: 8
329 * Memory Bus width: 32 bit
331 * Additional Latancy for PLL: 0 Cycle
333 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
334 DMC_MEMCONTROL_DPWRDN_DISABLE |
335 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
336 DMC_MEMCONTROL_TP_DISABLE |
337 DMC_MEMCONTROL_DSREF_ENABLE |
338 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
339 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
340 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
341 DMC_MEMCONTROL_NUM_CHIP_1 |
342 DMC_MEMCONTROL_BL_8 |
343 DMC_MEMCONTROL_PZQ_DISABLE |
344 DMC_MEMCONTROL_MRR_BYTE_7_0,
345 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
346 DMC_MEMCONFIGX_CHIP_COL_10 |
347 DMC_MEMCONFIGX_CHIP_ROW_15 |
348 DMC_MEMCONFIGX_CHIP_BANK_8,
349 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
350 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
351 .prechconfig_tp_cnt = 0xff,
354 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
355 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
356 DMC_CONCONTROL_RD_FETCH_DISABLE |
357 DMC_CONCONTROL_EMPTY_DISABLE |
358 DMC_CONCONTROL_AREF_EN_DISABLE |
359 DMC_CONCONTROL_IO_PD_CON_DISABLE,
361 .chips_per_channel = 2,
362 .chips_to_configure = 1,
364 .impedance = IMP_OUTPUT_DRV_30_OHM,
365 .gate_leveling_enable = 0,
367 .mem_manuf = MEM_MANUF_SAMSUNG,
368 .mem_type = DDR_MODE_DDR3,
369 .frequency_mhz = 800,
389 .pclk_cdrex_ratio = 0x5,
391 0x00020018, 0x00030000, 0x00010000, 0x00000d70
393 .timing_ref = 0x000000bb,
394 .timing_row = 0x8c36650e,
395 .timing_data = 0x3630580b,
396 .timing_power = 0x41000a44,
397 .phy0_dqs = 0x08080808,
398 .phy1_dqs = 0x08080808,
399 .phy0_dq = 0x08080808,
400 .phy1_dq = 0x08080808,
403 .phy0_pulld_dqs = 0xf,
404 .phy1_pulld_dqs = 0xf,
406 .lpddr3_ctrl_phy_reset = 0x1,
407 .ctrl_start_point = 0x10,
429 * Dynamic Clock: Always Running
430 * Memory Burst length: 8
432 * Memory Bus width: 32 bit
434 * Additional Latancy for PLL: 0 Cycle
436 .memcontrol = DMC_MEMCONTROL_CLK_STOP_DISABLE |
437 DMC_MEMCONTROL_DPWRDN_DISABLE |
438 DMC_MEMCONTROL_DPWRDN_ACTIVE_PRECHARGE |
439 DMC_MEMCONTROL_TP_DISABLE |
440 DMC_MEMCONTROL_DSREF_ENABLE |
441 DMC_MEMCONTROL_ADD_LAT_PALL_CYCLE(0) |
442 DMC_MEMCONTROL_MEM_TYPE_DDR3 |
443 DMC_MEMCONTROL_MEM_WIDTH_32BIT |
444 DMC_MEMCONTROL_NUM_CHIP_1 |
445 DMC_MEMCONTROL_BL_8 |
446 DMC_MEMCONTROL_PZQ_DISABLE |
447 DMC_MEMCONTROL_MRR_BYTE_7_0,
448 .memconfig = DMC_MEMCONFIGX_CHIP_MAP_INTERLEAVED |
449 DMC_MEMCONFIGX_CHIP_COL_10 |
450 DMC_MEMCONFIGX_CHIP_ROW_15 |
451 DMC_MEMCONFIGX_CHIP_BANK_8,
452 .membaseconfig0 = DMC_MEMBASECONFIG_VAL(0x40),
453 .membaseconfig1 = DMC_MEMBASECONFIG_VAL(0x80),
454 .prechconfig_tp_cnt = 0xff,
457 .concontrol = DMC_CONCONTROL_DFI_INIT_START_DISABLE |
458 DMC_CONCONTROL_TIMEOUT_LEVEL0 |
459 DMC_CONCONTROL_RD_FETCH_DISABLE |
460 DMC_CONCONTROL_EMPTY_DISABLE |
461 DMC_CONCONTROL_AREF_EN_DISABLE |
462 DMC_CONCONTROL_IO_PD_CON_DISABLE,
464 .chips_per_channel = 2,
465 .chips_to_configure = 1,
467 .impedance = IMP_OUTPUT_DRV_40_OHM,
468 .gate_leveling_enable = 1,
474 * Get the required memory type and speed (SPL version).
476 * In SPL we have no device tree, so we use the machine parameters
478 * @param mem_type Returns memory type
479 * @param frequency_mhz Returns memory speed in MHz
480 * @param arm_freq Returns ARM clock speed in MHz
481 * @param mem_manuf Return Memory Manufacturer name
483 static void clock_get_mem_selection(enum ddr_mode *mem_type,
484 unsigned *frequency_mhz, unsigned *arm_freq,
485 enum mem_manuf *mem_manuf)
487 struct spl_machine_param *params;
489 params = spl_get_machine_params();
490 *mem_type = params->mem_type;
491 *frequency_mhz = params->frequency_mhz;
492 *arm_freq = params->arm_freq_mhz;
493 *mem_manuf = params->mem_manuf;
496 /* Get the ratios for setting ARM clock */
497 struct arm_clk_ratios *get_arm_ratios(void)
499 struct arm_clk_ratios *arm_ratio;
500 enum ddr_mode mem_type;
501 enum mem_manuf mem_manuf;
502 unsigned frequency_mhz, arm_freq;
505 clock_get_mem_selection(&mem_type, &frequency_mhz,
506 &arm_freq, &mem_manuf);
508 for (i = 0, arm_ratio = arm_clk_ratios; i < ARRAY_SIZE(arm_clk_ratios);
510 if (arm_ratio->arm_freq_mhz == arm_freq)
514 /* will hang if failed to find clock ratio */
521 struct mem_timings *clock_get_mem_timings(void)
523 struct mem_timings *mem;
524 enum ddr_mode mem_type;
525 enum mem_manuf mem_manuf;
526 unsigned frequency_mhz, arm_freq;
529 clock_get_mem_selection(&mem_type, &frequency_mhz,
530 &arm_freq, &mem_manuf);
531 for (i = 0, mem = mem_timings; i < ARRAY_SIZE(mem_timings);
533 if (mem->mem_type == mem_type &&
534 mem->frequency_mhz == frequency_mhz &&
535 mem->mem_manuf == mem_manuf)
539 /* will hang if failed to find memory timings */
546 static void exynos5250_system_clock_init(void)
548 struct exynos5_clock *clk =
549 (struct exynos5_clock *)samsung_get_base_clock();
550 struct mem_timings *mem;
551 struct arm_clk_ratios *arm_clk_ratio;
554 mem = clock_get_mem_timings();
555 arm_clk_ratio = get_arm_ratios();
557 clrbits_le32(&clk->src_cpu, MUX_APLL_SEL_MASK);
559 val = readl(&clk->mux_stat_cpu);
560 } while ((val | MUX_APLL_SEL_MASK) != val);
562 clrbits_le32(&clk->src_core1, MUX_MPLL_SEL_MASK);
564 val = readl(&clk->mux_stat_core1);
565 } while ((val | MUX_MPLL_SEL_MASK) != val);
567 clrbits_le32(&clk->src_top2, MUX_CPLL_SEL_MASK);
568 clrbits_le32(&clk->src_top2, MUX_EPLL_SEL_MASK);
569 clrbits_le32(&clk->src_top2, MUX_VPLL_SEL_MASK);
570 clrbits_le32(&clk->src_top2, MUX_GPLL_SEL_MASK);
571 tmp = MUX_CPLL_SEL_MASK | MUX_EPLL_SEL_MASK | MUX_VPLL_SEL_MASK
574 val = readl(&clk->mux_stat_top2);
575 } while ((val | tmp) != val);
577 clrbits_le32(&clk->src_cdrex, MUX_BPLL_SEL_MASK);
579 val = readl(&clk->mux_stat_cdrex);
580 } while ((val | MUX_BPLL_SEL_MASK) != val);
583 writel(mem->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
584 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
585 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
586 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
587 writel(mem->gpll_pdiv * PLL_X_LOCK_FACTOR, &clk->gpll_lock);
588 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
589 writel(mem->vpll_pdiv * PLL_X_LOCK_FACTOR, &clk->vpll_lock);
591 writel(CLK_REG_DISABLE, &clk->pll_div2_sel);
593 writel(MUX_HPM_SEL_MASK, &clk->src_cpu);
595 val = readl(&clk->mux_stat_cpu);
596 } while ((val | HPM_SEL_SCLK_MPLL) != val);
598 val = arm_clk_ratio->arm2_ratio << 28
599 | arm_clk_ratio->apll_ratio << 24
600 | arm_clk_ratio->pclk_dbg_ratio << 20
601 | arm_clk_ratio->atb_ratio << 16
602 | arm_clk_ratio->periph_ratio << 12
603 | arm_clk_ratio->acp_ratio << 8
604 | arm_clk_ratio->cpud_ratio << 4
605 | arm_clk_ratio->arm_ratio;
606 writel(val, &clk->div_cpu0);
608 val = readl(&clk->div_stat_cpu0);
611 writel(CLK_DIV_CPU1_VAL, &clk->div_cpu1);
613 val = readl(&clk->div_stat_cpu1);
617 writel(APLL_CON1_VAL, &clk->apll_con1);
618 val = set_pll(arm_clk_ratio->apll_mdiv, arm_clk_ratio->apll_pdiv,
619 arm_clk_ratio->apll_sdiv);
620 writel(val, &clk->apll_con0);
621 while ((readl(&clk->apll_con0) & APLL_CON0_LOCKED) == 0)
625 writel(MPLL_CON1_VAL, &clk->mpll_con1);
626 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
627 writel(val, &clk->mpll_con0);
628 while ((readl(&clk->mpll_con0) & MPLL_CON0_LOCKED) == 0)
632 writel(BPLL_CON1_VAL, &clk->bpll_con1);
633 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
634 writel(val, &clk->bpll_con0);
635 while ((readl(&clk->bpll_con0) & BPLL_CON0_LOCKED) == 0)
639 writel(CPLL_CON1_VAL, &clk->cpll_con1);
640 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
641 writel(val, &clk->cpll_con0);
642 while ((readl(&clk->cpll_con0) & CPLL_CON0_LOCKED) == 0)
646 writel(GPLL_CON1_VAL, &clk->gpll_con1);
647 val = set_pll(mem->gpll_mdiv, mem->gpll_pdiv, mem->gpll_sdiv);
648 writel(val, &clk->gpll_con0);
649 while ((readl(&clk->gpll_con0) & GPLL_CON0_LOCKED) == 0)
653 writel(EPLL_CON2_VAL, &clk->epll_con2);
654 writel(EPLL_CON1_VAL, &clk->epll_con1);
655 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
656 writel(val, &clk->epll_con0);
657 while ((readl(&clk->epll_con0) & EPLL_CON0_LOCKED) == 0)
661 writel(VPLL_CON2_VAL, &clk->vpll_con2);
662 writel(VPLL_CON1_VAL, &clk->vpll_con1);
663 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
664 writel(val, &clk->vpll_con0);
665 while ((readl(&clk->vpll_con0) & VPLL_CON0_LOCKED) == 0)
668 writel(CLK_SRC_CORE0_VAL, &clk->src_core0);
669 writel(CLK_DIV_CORE0_VAL, &clk->div_core0);
670 while (readl(&clk->div_stat_core0) != 0)
673 writel(CLK_DIV_CORE1_VAL, &clk->div_core1);
674 while (readl(&clk->div_stat_core1) != 0)
677 writel(CLK_DIV_SYSRGT_VAL, &clk->div_sysrgt);
678 while (readl(&clk->div_stat_sysrgt) != 0)
681 writel(CLK_DIV_ACP_VAL, &clk->div_acp);
682 while (readl(&clk->div_stat_acp) != 0)
685 writel(CLK_DIV_SYSLFT_VAL, &clk->div_syslft);
686 while (readl(&clk->div_stat_syslft) != 0)
689 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
690 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
691 writel(TOP2_VAL, &clk->src_top2);
692 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
694 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
695 while (readl(&clk->div_stat_top0))
698 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
699 while (readl(&clk->div_stat_top1))
702 writel(CLK_SRC_LEX_VAL, &clk->src_lex);
704 val = readl(&clk->mux_stat_lex);
705 if (val == (val | 1))
709 writel(CLK_DIV_LEX_VAL, &clk->div_lex);
710 while (readl(&clk->div_stat_lex))
713 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
714 while (readl(&clk->div_stat_r0x))
717 writel(CLK_DIV_R0X_VAL, &clk->div_r0x);
718 while (readl(&clk->div_stat_r0x))
721 writel(CLK_DIV_R1X_VAL, &clk->div_r1x);
722 while (readl(&clk->div_stat_r1x))
725 writel(CLK_REG_DISABLE, &clk->src_cdrex);
727 writel(CLK_DIV_CDREX_VAL, &clk->div_cdrex);
728 while (readl(&clk->div_stat_cdrex))
731 val = readl(&clk->src_cpu);
732 val |= CLK_SRC_CPU_VAL;
733 writel(val, &clk->src_cpu);
735 val = readl(&clk->src_top2);
736 val |= CLK_SRC_TOP2_VAL;
737 writel(val, &clk->src_top2);
739 val = readl(&clk->src_core1);
740 val |= CLK_SRC_CORE1_VAL;
741 writel(val, &clk->src_core1);
743 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
744 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
745 while (readl(&clk->div_stat_fsys0))
748 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cpu);
749 writel(CLK_REG_DISABLE, &clk->clkout_cmu_core);
750 writel(CLK_REG_DISABLE, &clk->clkout_cmu_acp);
751 writel(CLK_REG_DISABLE, &clk->clkout_cmu_top);
752 writel(CLK_REG_DISABLE, &clk->clkout_cmu_lex);
753 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r0x);
754 writel(CLK_REG_DISABLE, &clk->clkout_cmu_r1x);
755 writel(CLK_REG_DISABLE, &clk->clkout_cmu_cdrex);
757 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
758 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
760 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
761 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
762 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
763 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
765 writel(SCLK_SRC_ISP_VAL, &clk->sclk_src_isp);
766 writel(SCLK_DIV_ISP_VAL, &clk->sclk_div_isp);
767 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
768 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
769 writel(CLK_DIV_ISP2_VAL, &clk->div_isp2);
771 /* FIMD1 SRC CLK SELECTION */
772 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp1_0);
774 val = MMC2_PRE_RATIO_VAL << MMC2_PRE_RATIO_OFFSET
775 | MMC2_RATIO_VAL << MMC2_RATIO_OFFSET
776 | MMC3_PRE_RATIO_VAL << MMC3_PRE_RATIO_OFFSET
777 | MMC3_RATIO_VAL << MMC3_RATIO_OFFSET;
778 writel(val, &clk->div_fsys2);
781 static void exynos5420_system_clock_init(void)
783 struct exynos5420_clock *clk =
784 (struct exynos5420_clock *)samsung_get_base_clock();
785 struct mem_timings *mem;
786 struct arm_clk_ratios *arm_clk_ratio;
789 mem = clock_get_mem_timings();
790 arm_clk_ratio = get_arm_ratios();
793 writel(arm_clk_ratio->apll_pdiv * PLL_LOCK_FACTOR, &clk->apll_lock);
794 writel(mem->mpll_pdiv * PLL_LOCK_FACTOR, &clk->mpll_lock);
795 writel(mem->bpll_pdiv * PLL_LOCK_FACTOR, &clk->bpll_lock);
796 writel(mem->cpll_pdiv * PLL_LOCK_FACTOR, &clk->cpll_lock);
797 writel(mem->dpll_pdiv * PLL_LOCK_FACTOR, &clk->dpll_lock);
798 writel(mem->epll_pdiv * PLL_X_LOCK_FACTOR, &clk->epll_lock);
799 writel(mem->vpll_pdiv * PLL_LOCK_FACTOR, &clk->vpll_lock);
800 writel(mem->ipll_pdiv * PLL_LOCK_FACTOR, &clk->ipll_lock);
801 writel(mem->spll_pdiv * PLL_LOCK_FACTOR, &clk->spll_lock);
802 writel(mem->kpll_pdiv * PLL_LOCK_FACTOR, &clk->kpll_lock);
804 setbits_le32(&clk->src_cpu, MUX_HPM_SEL_MASK);
806 writel(0, &clk->src_top6);
808 writel(0, &clk->src_cdrex);
809 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
810 writel(HPM_RATIO, &clk->div_cpu1);
811 writel(CLK_DIV_CPU0_VAL, &clk->div_cpu0);
813 /* switch A15 clock source to OSC clock before changing APLL */
814 clrbits_le32(&clk->src_cpu, APLL_FOUT);
817 writel(APLL_CON1_VAL, &clk->apll_con1);
818 val = set_pll(arm_clk_ratio->apll_mdiv,
819 arm_clk_ratio->apll_pdiv,
820 arm_clk_ratio->apll_sdiv);
821 writel(val, &clk->apll_con0);
822 while ((readl(&clk->apll_con0) & PLL_LOCKED) == 0)
825 /* now it is safe to switch to APLL */
826 setbits_le32(&clk->src_cpu, APLL_FOUT);
828 writel(SRC_KFC_HPM_SEL, &clk->src_kfc);
829 writel(CLK_DIV_KFC_VAL, &clk->div_kfc0);
831 /* switch A7 clock source to OSC clock before changing KPLL */
832 clrbits_le32(&clk->src_kfc, KPLL_FOUT);
835 writel(KPLL_CON1_VAL, &clk->kpll_con1);
836 val = set_pll(mem->kpll_mdiv, mem->kpll_pdiv, mem->kpll_sdiv);
837 writel(val, &clk->kpll_con0);
838 while ((readl(&clk->kpll_con0) & PLL_LOCKED) == 0)
841 /* now it is safe to switch to KPLL */
842 setbits_le32(&clk->src_kfc, KPLL_FOUT);
845 writel(MPLL_CON1_VAL, &clk->mpll_con1);
846 val = set_pll(mem->mpll_mdiv, mem->mpll_pdiv, mem->mpll_sdiv);
847 writel(val, &clk->mpll_con0);
848 while ((readl(&clk->mpll_con0) & PLL_LOCKED) == 0)
852 writel(DPLL_CON1_VAL, &clk->dpll_con1);
853 val = set_pll(mem->dpll_mdiv, mem->dpll_pdiv, mem->dpll_sdiv);
854 writel(val, &clk->dpll_con0);
855 while ((readl(&clk->dpll_con0) & PLL_LOCKED) == 0)
859 writel(EPLL_CON2_VAL, &clk->epll_con2);
860 writel(EPLL_CON1_VAL, &clk->epll_con1);
861 val = set_pll(mem->epll_mdiv, mem->epll_pdiv, mem->epll_sdiv);
862 writel(val, &clk->epll_con0);
863 while ((readl(&clk->epll_con0) & PLL_LOCKED) == 0)
867 writel(CPLL_CON1_VAL, &clk->cpll_con1);
868 val = set_pll(mem->cpll_mdiv, mem->cpll_pdiv, mem->cpll_sdiv);
869 writel(val, &clk->cpll_con0);
870 while ((readl(&clk->cpll_con0) & PLL_LOCKED) == 0)
874 writel(IPLL_CON1_VAL, &clk->ipll_con1);
875 val = set_pll(mem->ipll_mdiv, mem->ipll_pdiv, mem->ipll_sdiv);
876 writel(val, &clk->ipll_con0);
877 while ((readl(&clk->ipll_con0) & PLL_LOCKED) == 0)
881 writel(VPLL_CON1_VAL, &clk->vpll_con1);
882 val = set_pll(mem->vpll_mdiv, mem->vpll_pdiv, mem->vpll_sdiv);
883 writel(val, &clk->vpll_con0);
884 while ((readl(&clk->vpll_con0) & PLL_LOCKED) == 0)
888 writel(BPLL_CON1_VAL, &clk->bpll_con1);
889 val = set_pll(mem->bpll_mdiv, mem->bpll_pdiv, mem->bpll_sdiv);
890 writel(val, &clk->bpll_con0);
891 while ((readl(&clk->bpll_con0) & PLL_LOCKED) == 0)
895 writel(SPLL_CON1_VAL, &clk->spll_con1);
896 val = set_pll(mem->spll_mdiv, mem->spll_pdiv, mem->spll_sdiv);
897 writel(val, &clk->spll_con0);
898 while ((readl(&clk->spll_con0) & PLL_LOCKED) == 0)
901 writel(CLK_DIV_CDREX0_VAL, &clk->div_cdrex0);
902 writel(CLK_DIV_CDREX1_VAL, &clk->div_cdrex1);
904 writel(CLK_SRC_TOP0_VAL, &clk->src_top0);
905 writel(CLK_SRC_TOP1_VAL, &clk->src_top1);
906 writel(CLK_SRC_TOP2_VAL, &clk->src_top2);
907 writel(CLK_SRC_TOP7_VAL, &clk->src_top7);
909 writel(CLK_DIV_TOP0_VAL, &clk->div_top0);
910 writel(CLK_DIV_TOP1_VAL, &clk->div_top1);
911 writel(CLK_DIV_TOP2_VAL, &clk->div_top2);
913 writel(0, &clk->src_top10);
914 writel(0, &clk->src_top11);
915 writel(0, &clk->src_top12);
917 writel(CLK_SRC_TOP3_VAL, &clk->src_top3);
918 writel(CLK_SRC_TOP4_VAL, &clk->src_top4);
919 writel(CLK_SRC_TOP5_VAL, &clk->src_top5);
921 /* DISP1 BLK CLK SELECTION */
922 writel(CLK_SRC_DISP1_0_VAL, &clk->src_disp10);
923 writel(CLK_DIV_DISP1_0_VAL, &clk->div_disp10);
926 writel(AUDIO0_SEL_EPLL, &clk->src_mau);
927 writel(DIV_MAU_VAL, &clk->div_mau);
930 writel(CLK_SRC_FSYS0_VAL, &clk->src_fsys);
931 writel(CLK_DIV_FSYS0_VAL, &clk->div_fsys0);
932 writel(CLK_DIV_FSYS1_VAL, &clk->div_fsys1);
933 writel(CLK_DIV_FSYS2_VAL, &clk->div_fsys2);
935 writel(CLK_SRC_ISP_VAL, &clk->src_isp);
936 writel(CLK_DIV_ISP0_VAL, &clk->div_isp0);
937 writel(CLK_DIV_ISP1_VAL, &clk->div_isp1);
939 writel(CLK_SRC_PERIC0_VAL, &clk->src_peric0);
940 writel(CLK_SRC_PERIC1_VAL, &clk->src_peric1);
942 writel(CLK_DIV_PERIC0_VAL, &clk->div_peric0);
943 writel(CLK_DIV_PERIC1_VAL, &clk->div_peric1);
944 writel(CLK_DIV_PERIC2_VAL, &clk->div_peric2);
945 writel(CLK_DIV_PERIC3_VAL, &clk->div_peric3);
946 writel(CLK_DIV_PERIC4_VAL, &clk->div_peric4);
948 writel(CLK_DIV_CPERI1_VAL, &clk->div_cperi1);
950 writel(CLK_DIV2_RATIO, &clk->clkdiv2_ratio);
951 writel(CLK_DIV4_RATIO, &clk->clkdiv4_ratio);
952 writel(CLK_DIV_G2D, &clk->div_g2d);
954 writel(CLK_SRC_TOP6_VAL, &clk->src_top6);
955 writel(CLK_SRC_CDREX_VAL, &clk->src_cdrex);
956 writel(CLK_SRC_KFC_VAL, &clk->src_kfc);
959 void system_clock_init(void)
961 if (proid_is_exynos5420())
962 exynos5420_system_clock_init();
964 exynos5250_system_clock_init();
967 void clock_init_dp_clock(void)
969 struct exynos5_clock *clk =
970 (struct exynos5_clock *)samsung_get_base_clock();
972 /* DP clock enable */
973 setbits_le32(&clk->gate_ip_disp1, CLK_GATE_DP1_ALLOW);
975 /* We run DP at 267 Mhz */
976 setbits_le32(&clk->div_disp1_0, CLK_DIV_DISP1_0_FIMD1);
980 * Set clock divisor value for booting from EMMC.
981 * Set DWMMC channel-0 clk div to operate mmc0 device at 50MHz.
983 void emmc_boot_clk_div_set(void)
985 struct exynos5_clock *clk =
986 (struct exynos5_clock *)samsung_get_base_clock();
987 unsigned int div_mmc;
989 div_mmc = readl((unsigned int) &clk->div_fsys1) & ~FSYS1_MMC0_DIV_MASK;
990 div_mmc |= FSYS1_MMC0_DIV_VAL;
991 writel(div_mmc, (unsigned int) &clk->div_fsys1);
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