1 // Standard VGA driver code
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2001-2008 the LGPL VGABios developers Team
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // GET_GLOBAL
9 #include "farptr.h" // SET_FARVAR
10 #include "stdvga.h" // stdvga_setup
11 #include "string.h" // memset_far
12 #include "vgabios.h" // struct vgamode_s
13 #include "x86.h" // outb
16 /****************************************************************
18 ****************************************************************/
21 stdvga_set_border_color(u8 color)
26 stdvga_attr_write(0x00, v1);
29 for (i = 1; i < 4; i++)
30 stdvga_attr_mask(i, 0x10, color & 0x10);
34 stdvga_set_overscan_border_color(u8 color)
36 stdvga_attr_write(0x11, color);
40 stdvga_get_overscan_border_color(void)
42 return stdvga_attr_read(0x11);
46 stdvga_set_palette(u8 palid)
49 for (i = 1; i < 4; i++)
50 stdvga_attr_mask(i, 0x01, palid & 0x01);
54 stdvga_set_all_palette_reg(u16 seg, u8 *data_far)
57 for (i = 0; i < 0x10; i++) {
58 stdvga_attr_write(i, GET_FARVAR(seg, *data_far));
61 stdvga_attr_write(0x11, GET_FARVAR(seg, *data_far));
65 stdvga_get_all_palette_reg(u16 seg, u8 *data_far)
68 for (i = 0; i < 0x10; i++) {
69 SET_FARVAR(seg, *data_far, stdvga_attr_read(i));
72 SET_FARVAR(seg, *data_far, stdvga_attr_read(0x11));
76 stdvga_toggle_intensity(u8 flag)
78 stdvga_attr_mask(0x10, 0x08, (flag & 0x01) << 3);
82 stdvga_select_video_dac_color_page(u8 flag, u8 data)
86 stdvga_attr_mask(0x10, 0x80, data << 7);
90 u8 val = stdvga_attr_read(0x10);
94 stdvga_attr_write(0x14, data);
98 stdvga_read_video_dac_state(u8 *pmode, u8 *curpage)
100 u8 val1 = stdvga_attr_read(0x10) >> 7;
101 u8 val2 = stdvga_attr_read(0x14) & 0x0f;
109 /****************************************************************
111 ****************************************************************/
114 stdvga_perform_gray_scale_summing(u16 start, u16 count)
116 stdvga_attrindex_write(0x00);
118 for (i = start; i < start+count; i++) {
120 stdvga_dac_read(GET_SEG(SS), rgb, i, 1);
122 // intensity = ( 0.3 * Red ) + ( 0.59 * Green ) + ( 0.11 * Blue )
123 u16 intensity = ((77 * rgb[0] + 151 * rgb[1] + 28 * rgb[2]) + 0x80) >> 8;
124 if (intensity > 0x3f)
126 rgb[0] = rgb[1] = rgb[2] = intensity;
128 stdvga_dac_write(GET_SEG(SS), rgb, i, 1);
130 stdvga_attrindex_write(0x20);
134 /****************************************************************
136 ****************************************************************/
139 stdvga_set_text_block_specifier(u8 spec)
141 stdvga_sequ_write(0x03, spec);
144 // Enable reads and writes to the given "plane" when in planar4 mode.
146 stdvga_planar4_plane(int plane)
149 // Return to default mode (read plane0, write all planes)
150 stdvga_sequ_write(0x02, 0x0f);
151 stdvga_grdc_write(0x04, 0);
153 stdvga_sequ_write(0x02, 1<<plane);
154 stdvga_grdc_write(0x04, plane);
159 /****************************************************************
161 ****************************************************************/
164 get_font_access(void)
166 stdvga_sequ_write(0x00, 0x01);
167 stdvga_sequ_write(0x02, 0x04);
168 stdvga_sequ_write(0x04, 0x07);
169 stdvga_sequ_write(0x00, 0x03);
170 stdvga_grdc_write(0x04, 0x02);
171 stdvga_grdc_write(0x05, 0x00);
172 stdvga_grdc_write(0x06, 0x04);
176 release_font_access(void)
178 stdvga_sequ_write(0x00, 0x01);
179 stdvga_sequ_write(0x02, 0x03);
180 stdvga_sequ_write(0x04, 0x03);
181 stdvga_sequ_write(0x00, 0x03);
182 u16 v = (stdvga_misc_read() & 0x01) ? 0x0e : 0x0a;
183 stdvga_grdc_write(0x06, v);
184 stdvga_grdc_write(0x04, 0x00);
185 stdvga_grdc_write(0x05, 0x10);
189 stdvga_load_font(u16 seg, void *src_far, u16 count
190 , u16 start, u8 destflags, u8 fontsize)
193 u16 blockaddr = ((destflags & 0x03) << 14) + ((destflags & 0x04) << 11);
194 void *dest_far = (void*)(blockaddr + start*32);
196 for (i = 0; i < count; i++)
197 memcpy_far(SEG_GRAPH, dest_far + i*32
198 , seg, src_far + i*fontsize, fontsize);
199 release_font_access();
203 /****************************************************************
205 ****************************************************************/
208 stdvga_get_crtc(void)
210 if (stdvga_misc_read() & 1)
211 return VGAREG_VGA_CRTC_ADDRESS;
212 return VGAREG_MDA_CRTC_ADDRESS;
215 // Ratio between system visible framebuffer ram and the actual videoram used.
217 stdvga_vram_ratio(struct vgamode_s *vmode_g)
219 switch (GET_GLOBAL(vmode_g->memmodel)) {
223 return 4 / GET_GLOBAL(vmode_g->depth);
232 stdvga_set_cursor_shape(u16 cursor_type)
234 u16 crtc_addr = stdvga_get_crtc();
235 stdvga_crtc_write(crtc_addr, 0x0a, cursor_type >> 8);
236 stdvga_crtc_write(crtc_addr, 0x0b, cursor_type);
240 stdvga_set_cursor_pos(int address)
242 u16 crtc_addr = stdvga_get_crtc();
243 address /= 2; // Assume we're in text mode.
244 stdvga_crtc_write(crtc_addr, 0x0e, address >> 8);
245 stdvga_crtc_write(crtc_addr, 0x0f, address);
249 stdvga_set_scan_lines(u8 lines)
251 stdvga_crtc_mask(stdvga_get_crtc(), 0x09, 0x1f, lines - 1);
254 // Get vertical display end
258 u16 crtc_addr = stdvga_get_crtc();
259 u16 vde = stdvga_crtc_read(crtc_addr, 0x12);
260 u8 ovl = stdvga_crtc_read(crtc_addr, 0x07);
261 vde += (((ovl & 0x02) << 7) + ((ovl & 0x40) << 3) + 1);
266 stdvga_get_window(struct vgamode_s *vmode_g, int window)
272 stdvga_set_window(struct vgamode_s *vmode_g, int window, int val)
278 stdvga_get_linelength(struct vgamode_s *vmode_g)
280 u8 val = stdvga_crtc_read(stdvga_get_crtc(), 0x13);
281 return val * 8 / stdvga_vram_ratio(vmode_g);
285 stdvga_set_linelength(struct vgamode_s *vmode_g, int val)
287 val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
288 stdvga_crtc_write(stdvga_get_crtc(), 0x13, val);
293 stdvga_get_displaystart(struct vgamode_s *vmode_g)
295 u16 crtc_addr = stdvga_get_crtc();
296 int addr = (stdvga_crtc_read(crtc_addr, 0x0c) << 8
297 | stdvga_crtc_read(crtc_addr, 0x0d));
298 return addr * 4 / stdvga_vram_ratio(vmode_g);
302 stdvga_set_displaystart(struct vgamode_s *vmode_g, int val)
304 u16 crtc_addr = stdvga_get_crtc();
305 val = val * stdvga_vram_ratio(vmode_g) / 4;
306 stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
307 stdvga_crtc_write(crtc_addr, 0x0d, val);
312 stdvga_get_dacformat(struct vgamode_s *vmode_g)
318 stdvga_set_dacformat(struct vgamode_s *vmode_g, int val)
324 /****************************************************************
326 ****************************************************************/
328 struct saveVideoHardware {
344 stdvga_save_hw_state(u16 seg, struct saveVideoHardware *info)
346 u16 crtc_addr = stdvga_get_crtc();
347 SET_FARVAR(seg, info->sequ_index, inb(VGAREG_SEQU_ADDRESS));
348 SET_FARVAR(seg, info->crtc_index, inb(crtc_addr));
349 SET_FARVAR(seg, info->grdc_index, inb(VGAREG_GRDC_ADDRESS));
350 SET_FARVAR(seg, info->actl_index, stdvga_attrindex_read());
351 SET_FARVAR(seg, info->feature, inb(VGAREG_READ_FEATURE_CTL));
355 SET_FARVAR(seg, info->sequ_regs[i], stdvga_sequ_read(i+1));
356 SET_FARVAR(seg, info->sequ0, stdvga_sequ_read(0));
359 SET_FARVAR(seg, info->crtc_regs[i], stdvga_crtc_read(crtc_addr, i));
362 SET_FARVAR(seg, info->actl_regs[i], stdvga_attr_read(i));
365 SET_FARVAR(seg, info->grdc_regs[i], stdvga_grdc_read(i));
367 SET_FARVAR(seg, info->crtc_addr, crtc_addr);
369 /* XXX: read plane latches */
371 SET_FARVAR(seg, info->plane_latch[i], 0);
375 stdvga_restore_hw_state(u16 seg, struct saveVideoHardware *info)
379 stdvga_sequ_write(i+1, GET_FARVAR(seg, info->sequ_regs[i]));
380 stdvga_sequ_write(0x00, GET_FARVAR(seg, info->sequ0));
382 // Disable CRTC write protection
383 u16 crtc_addr = GET_FARVAR(seg, info->crtc_addr);
384 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
388 stdvga_crtc_write(crtc_addr, i, GET_FARVAR(seg, info->crtc_regs[i]));
389 // select crtc base address
390 stdvga_misc_mask(0x01, crtc_addr == VGAREG_VGA_CRTC_ADDRESS ? 0x01 : 0x00);
392 // enable write protection if needed
393 stdvga_crtc_write(crtc_addr, 0x11, GET_FARVAR(seg, info->crtc_regs[0x11]));
397 stdvga_attr_write(i, GET_FARVAR(seg, info->actl_regs[i]));
398 stdvga_attrindex_write(GET_FARVAR(seg, info->actl_index));
401 stdvga_grdc_write(i, GET_FARVAR(seg, info->grdc_regs[i]));
403 outb(GET_FARVAR(seg, info->sequ_index), VGAREG_SEQU_ADDRESS);
404 outb(GET_FARVAR(seg, info->crtc_index), crtc_addr);
405 outb(GET_FARVAR(seg, info->grdc_index), VGAREG_GRDC_ADDRESS);
406 outb(GET_FARVAR(seg, info->feature), crtc_addr - 0x4 + 0xa);
409 struct saveDACcolors {
418 stdvga_save_dac_state(u16 seg, struct saveDACcolors *info)
420 /* XXX: check this */
421 SET_FARVAR(seg, info->rwmode, inb(VGAREG_DAC_STATE));
422 SET_FARVAR(seg, info->peladdr, inb(VGAREG_DAC_WRITE_ADDRESS));
423 SET_FARVAR(seg, info->pelmask, stdvga_pelmask_read());
424 stdvga_dac_read(seg, info->dac, 0, 256);
425 SET_FARVAR(seg, info->color_select, 0);
429 stdvga_restore_dac_state(u16 seg, struct saveDACcolors *info)
431 stdvga_pelmask_write(GET_FARVAR(seg, info->pelmask));
432 stdvga_dac_write(seg, info->dac, 0, 256);
433 outb(GET_FARVAR(seg, info->peladdr), VGAREG_DAC_WRITE_ADDRESS);
437 stdvga_save_restore(int cmd, u16 seg, void *data)
440 if (cmd & SR_HARDWARE) {
442 stdvga_save_hw_state(seg, pos);
443 if (cmd & SR_RESTORE)
444 stdvga_restore_hw_state(seg, pos);
445 pos += sizeof(struct saveVideoHardware);
447 pos += bda_save_restore(cmd, seg, pos);
450 stdvga_save_dac_state(seg, pos);
451 if (cmd & SR_RESTORE)
452 stdvga_restore_dac_state(seg, pos);
453 pos += sizeof(struct saveDACcolors);
459 /****************************************************************
461 ****************************************************************/
464 stdvga_enable_video_addressing(u8 disable)
466 u8 v = (disable & 1) ? 0x00 : 0x02;
467 stdvga_misc_mask(0x02, v);
473 // switch to color mode and enable CPU access 480 lines
474 stdvga_misc_write(0xc3);
475 // more than 64k 3C4/04
476 stdvga_sequ_write(0x04, 0x02);