qemu/roms/seabios/vgasrc/clext.c

   1 //  QEMU Cirrus CLGD 54xx VGABIOS Extension.
   2 //
   3 // Copyright (C) 2009  Kevin O'Connor <kevin@koconnor.net>
   4 //  Copyright (c) 2004 Makoto Suzuki (suzu)
   5 //
   6 // This file may be distributed under the terms of the GNU LGPLv3 license.
   7
   8 #include "biosvar.h" // GET_GLOBAL
   9 #include "bregs.h" // struct bregs
  10 #include "clext.h" // clext_setup
  11 #include "hw/pci.h" // pci_config_readl
  12 #include "hw/pci_regs.h" // PCI_BASE_ADDRESS_0
  13 #include "output.h" // dprintf
  14 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
  15 #include "string.h" // memset16_far
  16 #include "vgabios.h" // VBE_VENDOR_STRING
  17
  18
  19 /****************************************************************
  20  * Cirrus mode tables
  21  ****************************************************************/
  22
  23 /* VGA */
  24 static u16 cseq_vga[] VAR16 = {0x0007,0xffff};
  25 static u16 cgraph_vga[] VAR16 = {0x0009,0x000a,0x000b,0xffff};
  26 static u16 ccrtc_vga[] VAR16 = {0x001a,0x001b,0x001d,0xffff};
  27
  28 /* extensions */
  29 static u16 cgraph_svgacolor[] VAR16 = {
  30     0x0000,0x0001,0x0002,0x0003,0x0004,0x4005,0x0506,0x0f07,0xff08,
  31     0x0009,0x000a,0x000b,
  32     0xffff
  33 };
  34 /* 640x480x8 */
  35 static u16 cseq_640x480x8[] VAR16 = {
  36     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  37     0x580b,0x580c,0x580d,0x580e,
  38     0x0412,0x0013,0x2017,
  39     0x331b,0x331c,0x331d,0x331e,
  40     0xffff
  41 };
  42 static u16 ccrtc_640x480x8[] VAR16 = {
  43     0x2c11,
  44     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  45     0x4009,0x000c,0x000d,
  46     0xea10,0xdf12,0x5013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  47     0x001a,0x221b,0x001d,
  48     0xffff
  49 };
  50 /* 640x480x16 */
  51 static u16 cseq_640x480x16[] VAR16 = {
  52     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
  53     0x580b,0x580c,0x580d,0x580e,
  54     0x0412,0x0013,0x2017,
  55     0x331b,0x331c,0x331d,0x331e,
  56     0xffff
  57 };
  58 static u16 ccrtc_640x480x16[] VAR16 = {
  59     0x2c11,
  60     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  61     0x4009,0x000c,0x000d,
  62     0xea10,0xdf12,0xa013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  63     0x001a,0x221b,0x001d,
  64     0xffff
  65 };
  66 /* 640x480x24 */
  67 static u16 cseq_640x480x24[] VAR16 = {
  68     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
  69     0x580b,0x580c,0x580d,0x580e,
  70     0x0412,0x0013,0x2017,
  71     0x331b,0x331c,0x331d,0x331e,
  72     0xffff
  73 };
  74 static u16 ccrtc_640x480x24[] VAR16 = {
  75     0x2c11,
  76     0x5f00,0x4f01,0x4f02,0x8003,0x5204,0x1e05,0x0b06,0x3e07,
  77     0x4009,0x000c,0x000d,
  78     0xea10,0xdf12,0xf013,0x4014,0xdf15,0x0b16,0xc317,0xff18,
  79     0x001a,0x221b,0x001d,
  80     0xffff
  81 };
  82 /* 800x600x8 */
  83 static u16 cseq_800x600x8[] VAR16 = {
  84     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
  85     0x230b,0x230c,0x230d,0x230e,
  86     0x0412,0x0013,0x2017,
  87     0x141b,0x141c,0x141d,0x141e,
  88     0xffff
  89 };
  90 static u16 ccrtc_800x600x8[] VAR16 = {
  91     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
  92     0x6009,0x000c,0x000d,
  93     0x7d10,0x5712,0x6413,0x4014,0x5715,0x9816,0xc317,0xff18,
  94     0x001a,0x221b,0x001d,
  95     0xffff
  96 };
  97 /* 800x600x16 */
  98 static u16 cseq_800x600x16[] VAR16 = {
  99     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 100     0x230b,0x230c,0x230d,0x230e,
 101     0x0412,0x0013,0x2017,
 102     0x141b,0x141c,0x141d,0x141e,
 103     0xffff
 104 };
 105 static u16 ccrtc_800x600x16[] VAR16 = {
 106     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 107     0x6009,0x000c,0x000d,
 108     0x7d10,0x5712,0xc813,0x4014,0x5715,0x9816,0xc317,0xff18,
 109     0x001a,0x221b,0x001d,
 110     0xffff
 111 };
 112 /* 800x600x24 */
 113 static u16 cseq_800x600x24[] VAR16 = {
 114     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 115     0x230b,0x230c,0x230d,0x230e,
 116     0x0412,0x0013,0x2017,
 117     0x141b,0x141c,0x141d,0x141e,
 118     0xffff
 119 };
 120 static u16 ccrtc_800x600x24[] VAR16 = {
 121     0x2311,0x7d00,0x6301,0x6302,0x8003,0x6b04,0x1a05,0x9806,0xf007,
 122     0x6009,0x000c,0x000d,
 123     0x7d10,0x5712,0x2c13,0x4014,0x5715,0x9816,0xc317,0xff18,
 124     0x001a,0x321b,0x001d,
 125     0xffff
 126 };
 127 /* 1024x768x8 */
 128 static u16 cseq_1024x768x8[] VAR16 = {
 129     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 130     0x760b,0x760c,0x760d,0x760e,
 131     0x0412,0x0013,0x2017,
 132     0x341b,0x341c,0x341d,0x341e,
 133     0xffff
 134 };
 135 static u16 ccrtc_1024x768x8[] VAR16 = {
 136     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 137     0x6009,0x000c,0x000d,
 138     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 139     0x001a,0x221b,0x001d,
 140     0xffff
 141 };
 142 /* 1024x768x16 */
 143 static u16 cseq_1024x768x16[] VAR16 = {
 144     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 145     0x760b,0x760c,0x760d,0x760e,
 146     0x0412,0x0013,0x2017,
 147     0x341b,0x341c,0x341d,0x341e,
 148     0xffff
 149 };
 150 static u16 ccrtc_1024x768x16[] VAR16 = {
 151     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 152     0x6009,0x000c,0x000d,
 153     0x0310,0xff12,0x0013,0x4014,0xff15,0x2416,0xc317,0xff18,
 154     0x001a,0x321b,0x001d,
 155     0xffff
 156 };
 157 /* 1024x768x24 */
 158 static u16 cseq_1024x768x24[] VAR16 = {
 159     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1507,
 160     0x760b,0x760c,0x760d,0x760e,
 161     0x0412,0x0013,0x2017,
 162     0x341b,0x341c,0x341d,0x341e,
 163     0xffff
 164 };
 165 static u16 ccrtc_1024x768x24[] VAR16 = {
 166     0x2911,0xa300,0x7f01,0x7f02,0x8603,0x8304,0x9405,0x2406,0xf507,
 167     0x6009,0x000c,0x000d,
 168     0x0310,0xff12,0x8013,0x4014,0xff15,0x2416,0xc317,0xff18,
 169     0x001a,0x321b,0x001d,
 170     0xffff
 171 };
 172 /* 1280x1024x8 */
 173 static u16 cseq_1280x1024x8[] VAR16 = {
 174     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 175     0x760b,0x760c,0x760d,0x760e,
 176     0x0412,0x0013,0x2017,
 177     0x341b,0x341c,0x341d,0x341e,
 178     0xffff
 179 };
 180 static u16 ccrtc_1280x1024x8[] VAR16 = {
 181     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 182     0x6009,0x000c,0x000d,
 183     0x0310,0xff12,0xa013,0x4014,0xff15,0x2416,0xc317,0xff18,
 184     0x001a,0x221b,0x001d,
 185     0xffff
 186 };
 187 /* 1280x1024x16 */
 188 static u16 cseq_1280x1024x16[] VAR16 = {
 189     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1707,
 190     0x760b,0x760c,0x760d,0x760e,
 191     0x0412,0x0013,0x2017,
 192     0x341b,0x341c,0x341d,0x341e,
 193     0xffff
 194 };
 195 static u16 ccrtc_1280x1024x16[] VAR16 = {
 196     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 197     0x6009,0x000c,0x000d,
 198     0x0310,0xff12,0x4013,0x4014,0xff15,0x2416,0xc317,0xff18,
 199     0x001a,0x321b,0x001d,
 200     0xffff
 201 };
 202
 203 /* 1600x1200x8 */
 204 static u16 cseq_1600x1200x8[] VAR16 = {
 205     0x0300,0x2101,0x0f02,0x0003,0x0e04,0x1107,
 206     0x760b,0x760c,0x760d,0x760e,
 207     0x0412,0x0013,0x2017,
 208     0x341b,0x341c,0x341d,0x341e,
 209     0xffff
 210 };
 211 static u16 ccrtc_1600x1200x8[] VAR16 = {
 212     0x2911,0xc300,0x9f01,0x9f02,0x8603,0x8304,0x9405,0x2406,0xf707,
 213     0x6009,0x000c,0x000d,
 214     0x0310,0xff12,0xc813,0x4014,0xff15,0x2416,0xc317,0xff18,
 215     0x001a,0x221b,0x001d,
 216     0xffff
 217 };
 218
 219 struct cirrus_mode_s {
 220     u16 mode, vesamode;
 221     struct vgamode_s info;
 222
 223     u16 hidden_dac; /* 0x3c6 */
 224     u16 *seq; /* 0x3c4 */
 225     u16 *graph; /* 0x3ce */
 226     u16 *crtc; /* 0x3d4 */
 227 };
 228
 229 static struct cirrus_mode_s cirrus_modes[] VAR16 = {
 230     {0x5f,0x101,{MM_PACKED,640,480,8,8,16,SEG_GRAPH},0x00,
 231      cseq_640x480x8,cgraph_svgacolor,ccrtc_640x480x8},
 232     {0x64,0x111,{MM_DIRECT,640,480,16,8,16,SEG_GRAPH},0xe1,
 233      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 234     {0x66,0x110,{MM_DIRECT,640,480,15,8,16,SEG_GRAPH},0xf0,
 235      cseq_640x480x16,cgraph_svgacolor,ccrtc_640x480x16},
 236     {0x71,0x112,{MM_DIRECT,640,480,24,8,16,SEG_GRAPH},0xe5,
 237      cseq_640x480x24,cgraph_svgacolor,ccrtc_640x480x24},
 238
 239     {0x5c,0x103,{MM_PACKED,800,600,8,8,16,SEG_GRAPH},0x00,
 240      cseq_800x600x8,cgraph_svgacolor,ccrtc_800x600x8},
 241     {0x65,0x114,{MM_DIRECT,800,600,16,8,16,SEG_GRAPH},0xe1,
 242      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 243     {0x67,0x113,{MM_DIRECT,800,600,15,8,16,SEG_GRAPH},0xf0,
 244      cseq_800x600x16,cgraph_svgacolor,ccrtc_800x600x16},
 245
 246     {0x60,0x105,{MM_PACKED,1024,768,8,8,16,SEG_GRAPH},0x00,
 247      cseq_1024x768x8,cgraph_svgacolor,ccrtc_1024x768x8},
 248     {0x74,0x117,{MM_DIRECT,1024,768,16,8,16,SEG_GRAPH},0xe1,
 249      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 250     {0x68,0x116,{MM_DIRECT,1024,768,15,8,16,SEG_GRAPH},0xf0,
 251      cseq_1024x768x16,cgraph_svgacolor,ccrtc_1024x768x16},
 252
 253     {0x78,0x115,{MM_DIRECT,800,600,24,8,16,SEG_GRAPH},0xe5,
 254      cseq_800x600x24,cgraph_svgacolor,ccrtc_800x600x24},
 255     {0x79,0x118,{MM_DIRECT,1024,768,24,8,16,SEG_GRAPH},0xe5,
 256      cseq_1024x768x24,cgraph_svgacolor,ccrtc_1024x768x24},
 257
 258     {0x6d,0x107,{MM_PACKED,1280,1024,8,8,16,SEG_GRAPH},0x00,
 259      cseq_1280x1024x8,cgraph_svgacolor,ccrtc_1280x1024x8},
 260     {0x69,0x119,{MM_DIRECT,1280,1024,15,8,16,SEG_GRAPH},0xf0,
 261      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 262     {0x75,0x11a,{MM_DIRECT,1280,1024,16,8,16,SEG_GRAPH},0xe1,
 263      cseq_1280x1024x16,cgraph_svgacolor,ccrtc_1280x1024x16},
 264
 265     {0x7b,0xffff,{MM_PACKED,1600,1200,8,8,16,SEG_GRAPH},0x00,
 266      cseq_1600x1200x8,cgraph_svgacolor,ccrtc_1600x1200x8},
 267 };
 268
 269 static struct cirrus_mode_s mode_switchback VAR16 =
 270     {0xfe,0xffff,{0xff},0,cseq_vga,cgraph_vga,ccrtc_vga};
 271
 272 int
 273 is_cirrus_mode(struct vgamode_s *vmode_g)
 274 {
 275     return (vmode_g >= &cirrus_modes[0].info
 276             && vmode_g <= &cirrus_modes[ARRAY_SIZE(cirrus_modes)-1].info);
 277 }
 278
 279 struct vgamode_s *
 280 clext_find_mode(int mode)
 281 {
 282     struct cirrus_mode_s *table_g = cirrus_modes;
 283     while (table_g < &cirrus_modes[ARRAY_SIZE(cirrus_modes)]) {
 284         if (GET_GLOBAL(table_g->mode) == mode
 285             || GET_GLOBAL(table_g->vesamode) == mode)
 286             return &table_g->info;
 287         table_g++;
 288     }
 289     return stdvga_find_mode(mode);
 290 }
 291
 292 void
 293 clext_list_modes(u16 seg, u16 *dest, u16 *last)
 294 {
 295     int i;
 296     for (i=0; i<ARRAY_SIZE(cirrus_modes) && dest<last; i++) {
 297         u16 mode = GET_GLOBAL(cirrus_modes[i].vesamode);
 298         if (mode == 0xffff)
 299             continue;
 300         SET_FARVAR(seg, *dest, mode);
 301         dest++;
 302     }
 303     stdvga_list_modes(seg, dest, last);
 304 }
 305
 306
 307 /****************************************************************
 308  * helper functions
 309  ****************************************************************/
 310
 311 int
 312 clext_get_window(struct vgamode_s *vmode_g, int window)
 313 {
 314     return stdvga_grdc_read(window + 9);
 315 }
 316
 317 int
 318 clext_set_window(struct vgamode_s *vmode_g, int window, int val)
 319 {
 320     if (val >= 0x100)
 321         return -1;
 322     stdvga_grdc_write(window + 9, val);
 323     return 0;
 324 }
 325
 326 int
 327 clext_get_linelength(struct vgamode_s *vmode_g)
 328 {
 329     u16 crtc_addr = stdvga_get_crtc();
 330     u8 reg13 = stdvga_crtc_read(crtc_addr, 0x13);
 331     u8 reg1b = stdvga_crtc_read(crtc_addr, 0x1b);
 332     return (((reg1b & 0x10) << 4) + reg13) * 8 / stdvga_vram_ratio(vmode_g);
 333 }
 334
 335 int
 336 clext_set_linelength(struct vgamode_s *vmode_g, int val)
 337 {
 338     u16 crtc_addr = stdvga_get_crtc();
 339     val = DIV_ROUND_UP(val * stdvga_vram_ratio(vmode_g), 8);
 340     stdvga_crtc_write(crtc_addr, 0x13, val);
 341     stdvga_crtc_mask(crtc_addr, 0x1b, 0x10, (val & 0x100) >> 4);
 342     return 0;
 343 }
 344
 345 int
 346 clext_get_displaystart(struct vgamode_s *vmode_g)
 347 {
 348     u16 crtc_addr = stdvga_get_crtc();
 349     u8 b2 = stdvga_crtc_read(crtc_addr, 0x0c);
 350     u8 b1 = stdvga_crtc_read(crtc_addr, 0x0d);
 351     u8 b3 = stdvga_crtc_read(crtc_addr, 0x1b);
 352     u8 b4 = stdvga_crtc_read(crtc_addr, 0x1d);
 353     int val = (b1 | (b2<<8) | ((b3 & 0x01) << 16) | ((b3 & 0x0c) << 15)
 354                | ((b4 & 0x80) << 12));
 355     return val * 4 / stdvga_vram_ratio(vmode_g);
 356 }
 357
 358 int
 359 clext_set_displaystart(struct vgamode_s *vmode_g, int val)
 360 {
 361     u16 crtc_addr = stdvga_get_crtc();
 362     val = val * stdvga_vram_ratio(vmode_g) / 4;
 363     stdvga_crtc_write(crtc_addr, 0x0d, val);
 364     stdvga_crtc_write(crtc_addr, 0x0c, val >> 8);
 365     stdvga_crtc_mask(crtc_addr, 0x1d, 0x80, (val & 0x0800) >> 4);
 366     stdvga_crtc_mask(crtc_addr, 0x1b, 0x0d
 367                      , ((val & 0x0100) >> 8) | ((val & 0x0600) >> 7));
 368     return 0;
 369 }
 370
 371 int
 372 clext_save_restore(int cmd, u16 seg, void *data)
 373 {
 374     if (cmd & SR_REGISTERS)
 375         return -1;
 376     return stdvga_save_restore(cmd, seg, data);
 377 }
 378
 379
 380 /****************************************************************
 381  * Mode setting
 382  ****************************************************************/
 383
 384 static void
 385 cirrus_switch_mode_setregs(u16 *data, u16 port)
 386 {
 387     for (;;) {
 388         u16 val = GET_GLOBAL(*data);
 389         if (val == 0xffff)
 390             return;
 391         outw(val, port);
 392         data++;
 393     }
 394 }
 395
 396 static void
 397 cirrus_switch_mode(struct cirrus_mode_s *table)
 398 {
 399     // Unlock cirrus special
 400     stdvga_sequ_write(0x06, 0x12);
 401     cirrus_switch_mode_setregs(GET_GLOBAL(table->seq), VGAREG_SEQU_ADDRESS);
 402     cirrus_switch_mode_setregs(GET_GLOBAL(table->graph), VGAREG_GRDC_ADDRESS);
 403     cirrus_switch_mode_setregs(GET_GLOBAL(table->crtc), stdvga_get_crtc());
 404
 405     stdvga_pelmask_write(0x00);
 406     stdvga_pelmask_read();
 407     stdvga_pelmask_read();
 408     stdvga_pelmask_read();
 409     stdvga_pelmask_read();
 410     stdvga_pelmask_write(GET_GLOBAL(table->hidden_dac));
 411     stdvga_pelmask_write(0xff);
 412
 413     u8 memmodel = GET_GLOBAL(table->info.memmodel);
 414     u8 on = 0;
 415     if (memmodel == MM_PLANAR)
 416         on = 0x41;
 417     else if (memmodel != MM_TEXT)
 418         on = 0x01;
 419     stdvga_attr_mask(0x10, 0x01, on);
 420     stdvga_attrindex_write(0x20);
 421 }
 422
 423 static void
 424 cirrus_enable_16k_granularity(void)
 425 {
 426     stdvga_grdc_mask(0x0b, 0x00, 0x20);
 427 }
 428
 429 static void
 430 cirrus_clear_vram(u16 fill)
 431 {
 432     cirrus_enable_16k_granularity();
 433     int count = GET_GLOBAL(VBE_total_memory) / (16 * 1024);
 434     int i;
 435     for (i=0; i<count; i++) {
 436         stdvga_grdc_write(0x09, i);
 437         memset16_far(SEG_GRAPH, 0, fill, 16 * 1024);
 438     }
 439     stdvga_grdc_write(0x09, 0x00);
 440 }
 441
 442 int
 443 clext_set_mode(struct vgamode_s *vmode_g, int flags)
 444 {
 445     if (!is_cirrus_mode(vmode_g)) {
 446         cirrus_switch_mode(&mode_switchback);
 447         dprintf(1, "cirrus mode switch regular\n");
 448         return stdvga_set_mode(vmode_g, flags);
 449     }
 450     struct cirrus_mode_s *table_g = container_of(
 451         vmode_g, struct cirrus_mode_s, info);
 452     cirrus_switch_mode(table_g);
 453     if (GET_GLOBAL(vmode_g->memmodel) == MM_PACKED && !(flags & MF_NOPALETTE))
 454         stdvga_set_packed_palette();
 455     if (!(flags & MF_LINEARFB))
 456         cirrus_enable_16k_granularity();
 457     if (!(flags & MF_NOCLEARMEM))
 458         // fill with 0xff to keep win 2K happy
 459         cirrus_clear_vram(flags & MF_LEGACY ? 0xffff : 0x0000);
 460     return 0;
 461 }
 462
 463
 464 /****************************************************************
 465  * extbios
 466  ****************************************************************/
 467
 468 static void
 469 clext_101280(struct bregs *regs)
 470 {
 471     u8 v = stdvga_crtc_read(stdvga_get_crtc(), 0x27);
 472     if (v == 0xa0)
 473         // 5430
 474         regs->ax = 0x0032;
 475     else if (v == 0xb8)
 476         // 5446
 477         regs->ax = 0x0039;
 478     else
 479         regs->ax = 0x00ff;
 480     regs->bx = 0x00;
 481     return;
 482 }
 483
 484 static void
 485 clext_101281(struct bregs *regs)
 486 {
 487     // XXX
 488     regs->ax = 0x0100;
 489 }
 490
 491 static void
 492 clext_101282(struct bregs *regs)
 493 {
 494     regs->al = stdvga_crtc_read(stdvga_get_crtc(), 0x27) & 0x03;
 495     regs->ah = 0xAF;
 496 }
 497
 498 static void
 499 clext_101285(struct bregs *regs)
 500 {
 501     regs->al = GET_GLOBAL(VBE_total_memory) / (64*1024);
 502 }
 503
 504 static void
 505 clext_10129a(struct bregs *regs)
 506 {
 507     regs->ax = 0x4060;
 508     regs->cx = 0x1132;
 509 }
 510
 511 extern void a0h_callback(void);
 512 ASM16(
 513     // fatal: not implemented yet
 514     "a0h_callback:"
 515     "cli\n"
 516     "hlt\n"
 517     "lretw");
 518
 519 static void
 520 clext_1012a0(struct bregs *regs)
 521 {
 522     struct vgamode_s *table_g = clext_find_mode(regs->al & 0x7f);
 523     regs->ah = (table_g ? 1 : 0);
 524     regs->bx = (u32)a0h_callback;
 525     regs->ds = regs->si = regs->es = regs->di = 0xffff;
 526 }
 527
 528 static void
 529 clext_1012a1(struct bregs *regs)
 530 {
 531     regs->bx = 0x0e00; // IBM 8512/8513, color
 532 }
 533
 534 static void
 535 clext_1012a2(struct bregs *regs)
 536 {
 537     regs->al = 0x07; // HSync 31.5 - 64.0 kHz
 538 }
 539
 540 static void
 541 clext_1012ae(struct bregs *regs)
 542 {
 543     regs->al = 0x01; // High Refresh 75Hz
 544 }
 545
 546 static void
 547 clext_1012XX(struct bregs *regs)
 548 {
 549     debug_stub(regs);
 550 }
 551
 552 void
 553 clext_1012(struct bregs *regs)
 554 {
 555     switch (regs->bl) {
 556     case 0x80: clext_101280(regs); break;
 557     case 0x81: clext_101281(regs); break;
 558     case 0x82: clext_101282(regs); break;
 559     case 0x85: clext_101285(regs); break;
 560     case 0x9a: clext_10129a(regs); break;
 561     case 0xa0: clext_1012a0(regs); break;
 562     case 0xa1: clext_1012a1(regs); break;
 563     case 0xa2: clext_1012a2(regs); break;
 564     case 0xae: clext_1012ae(regs); break;
 565     default:   clext_1012XX(regs); break;
 566     }
 567 }
 568
 569
 570 /****************************************************************
 571  * init
 572  ****************************************************************/
 573
 574 static int
 575 cirrus_check(void)
 576 {
 577     stdvga_sequ_write(0x06, 0x92);
 578     return stdvga_sequ_read(0x06) == 0x12;
 579 }
 580
 581 static u8
 582 cirrus_get_memsize(void)
 583 {
 584     // get DRAM band width
 585     u8 v = stdvga_sequ_read(0x0f);
 586     u8 x = (v >> 3) & 0x03;
 587     if (x == 0x03 && v & 0x80)
 588         // 4MB
 589         return 0x40;
 590     return 0x04 << x;
 591 }
 592
 593 int
 594 clext_setup(void)
 595 {
 596     int ret = stdvga_setup();
 597     if (ret)
 598         return ret;
 599
 600     dprintf(1, "cirrus init\n");
 601     if (! cirrus_check())
 602         return -1;
 603     dprintf(1, "cirrus init 2\n");
 604
 605     // memory setup
 606     stdvga_sequ_write(0x0a, stdvga_sequ_read(0x0f) & 0x18);
 607     // set vga mode
 608     stdvga_sequ_write(0x07, 0x00);
 609     // reset bitblt
 610     stdvga_grdc_write(0x31, 0x04);
 611     stdvga_grdc_write(0x31, 0x00);
 612
 613     if (GET_GLOBAL(HaveRunInit))
 614         return 0;
 615
 616     u32 lfb_addr = 0;
 617     int bdf = GET_GLOBAL(VgaBDF);
 618     if (CONFIG_VGA_PCI && bdf >= 0)
 619         lfb_addr = (pci_config_readl(bdf, PCI_BASE_ADDRESS_0)
 620                     & PCI_BASE_ADDRESS_MEM_MASK);
 621     SET_VGA(VBE_framebuffer, lfb_addr);
 622     u16 totalmem = cirrus_get_memsize();
 623     SET_VGA(VBE_total_memory, totalmem * 64 * 1024);
 624     SET_VGA(VBE_win_granularity, 16);
 625
 626     return 0;
 627 }