1 // Bochs VGA interface to extended "VBE" modes
3 // Copyright (C) 2012 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2011 Julian Pidancet <julian.pidancet@citrix.com>
5 // Copyright (C) 2002 Jeroen Janssen
7 // This file may be distributed under the terms of the GNU LGPLv3 license.
9 #include "biosvar.h" // GET_GLOBAL
10 #include "bochsvga.h" // bochsvga_set_mode
11 #include "config.h" // CONFIG_*
12 #include "hw/pci.h" // pci_config_readl
13 #include "hw/pci_regs.h" // PCI_BASE_ADDRESS_0
14 #include "output.h" // dprintf
15 #include "std/vbe.h" // VBE_CAPABILITY_8BIT_DAC
16 #include "stdvga.h" // VGAREG_SEQU_ADDRESS
17 #include "vgabios.h" // struct vbe_modeinfo
18 #include "x86.h" // outw
21 /****************************************************************
23 ****************************************************************/
25 static struct bochsvga_mode
28 struct vgamode_s info;
29 } bochsvga_modes[] VAR16 = {
31 { 0x100, { MM_PACKED, 640, 400, 8, 8, 16, SEG_GRAPH } },
32 { 0x101, { MM_PACKED, 640, 480, 8, 8, 16, SEG_GRAPH } },
33 { 0x102, { MM_PLANAR, 800, 600, 4, 8, 16, SEG_GRAPH } },
34 { 0x103, { MM_PACKED, 800, 600, 8, 8, 16, SEG_GRAPH } },
35 { 0x104, { MM_PLANAR, 1024, 768, 4, 8, 16, SEG_GRAPH } },
36 { 0x105, { MM_PACKED, 1024, 768, 8, 8, 16, SEG_GRAPH } },
37 { 0x106, { MM_PLANAR, 1280, 1024, 4, 8, 16, SEG_GRAPH } },
38 { 0x107, { MM_PACKED, 1280, 1024, 8, 8, 16, SEG_GRAPH } },
39 { 0x10D, { MM_DIRECT, 320, 200, 15, 8, 16, SEG_GRAPH } },
40 { 0x10E, { MM_DIRECT, 320, 200, 16, 8, 16, SEG_GRAPH } },
41 { 0x10F, { MM_DIRECT, 320, 200, 24, 8, 16, SEG_GRAPH } },
42 { 0x110, { MM_DIRECT, 640, 480, 15, 8, 16, SEG_GRAPH } },
43 { 0x111, { MM_DIRECT, 640, 480, 16, 8, 16, SEG_GRAPH } },
44 { 0x112, { MM_DIRECT, 640, 480, 24, 8, 16, SEG_GRAPH } },
45 { 0x113, { MM_DIRECT, 800, 600, 15, 8, 16, SEG_GRAPH } },
46 { 0x114, { MM_DIRECT, 800, 600, 16, 8, 16, SEG_GRAPH } },
47 { 0x115, { MM_DIRECT, 800, 600, 24, 8, 16, SEG_GRAPH } },
48 { 0x116, { MM_DIRECT, 1024, 768, 15, 8, 16, SEG_GRAPH } },
49 { 0x117, { MM_DIRECT, 1024, 768, 16, 8, 16, SEG_GRAPH } },
50 { 0x118, { MM_DIRECT, 1024, 768, 24, 8, 16, SEG_GRAPH } },
51 { 0x119, { MM_DIRECT, 1280, 1024, 15, 8, 16, SEG_GRAPH } },
52 { 0x11A, { MM_DIRECT, 1280, 1024, 16, 8, 16, SEG_GRAPH } },
53 { 0x11B, { MM_DIRECT, 1280, 1024, 24, 8, 16, SEG_GRAPH } },
54 { 0x11C, { MM_PACKED, 1600, 1200, 8, 8, 16, SEG_GRAPH } },
55 { 0x11D, { MM_DIRECT, 1600, 1200, 15, 8, 16, SEG_GRAPH } },
56 { 0x11E, { MM_DIRECT, 1600, 1200, 16, 8, 16, SEG_GRAPH } },
57 { 0x11F, { MM_DIRECT, 1600, 1200, 24, 8, 16, SEG_GRAPH } },
59 { 0x140, { MM_DIRECT, 320, 200, 32, 8, 16, SEG_GRAPH } },
60 { 0x141, { MM_DIRECT, 640, 400, 32, 8, 16, SEG_GRAPH } },
61 { 0x142, { MM_DIRECT, 640, 480, 32, 8, 16, SEG_GRAPH } },
62 { 0x143, { MM_DIRECT, 800, 600, 32, 8, 16, SEG_GRAPH } },
63 { 0x144, { MM_DIRECT, 1024, 768, 32, 8, 16, SEG_GRAPH } },
64 { 0x145, { MM_DIRECT, 1280, 1024, 32, 8, 16, SEG_GRAPH } },
65 { 0x146, { MM_PACKED, 320, 200, 8, 8, 16, SEG_GRAPH } },
66 { 0x147, { MM_DIRECT, 1600, 1200, 32, 8, 16, SEG_GRAPH } },
67 { 0x148, { MM_PACKED, 1152, 864, 8, 8, 16, SEG_GRAPH } },
68 { 0x149, { MM_DIRECT, 1152, 864, 15, 8, 16, SEG_GRAPH } },
69 { 0x14a, { MM_DIRECT, 1152, 864, 16, 8, 16, SEG_GRAPH } },
70 { 0x14b, { MM_DIRECT, 1152, 864, 24, 8, 16, SEG_GRAPH } },
71 { 0x14c, { MM_DIRECT, 1152, 864, 32, 8, 16, SEG_GRAPH } },
72 { 0x175, { MM_DIRECT, 1280, 768, 16, 8, 16, SEG_GRAPH } },
73 { 0x176, { MM_DIRECT, 1280, 768, 24, 8, 16, SEG_GRAPH } },
74 { 0x177, { MM_DIRECT, 1280, 768, 32, 8, 16, SEG_GRAPH } },
75 { 0x178, { MM_DIRECT, 1280, 800, 16, 8, 16, SEG_GRAPH } },
76 { 0x179, { MM_DIRECT, 1280, 800, 24, 8, 16, SEG_GRAPH } },
77 { 0x17a, { MM_DIRECT, 1280, 800, 32, 8, 16, SEG_GRAPH } },
78 { 0x17b, { MM_DIRECT, 1280, 960, 16, 8, 16, SEG_GRAPH } },
79 { 0x17c, { MM_DIRECT, 1280, 960, 24, 8, 16, SEG_GRAPH } },
80 { 0x17d, { MM_DIRECT, 1280, 960, 32, 8, 16, SEG_GRAPH } },
81 { 0x17e, { MM_DIRECT, 1440, 900, 16, 8, 16, SEG_GRAPH } },
82 { 0x17f, { MM_DIRECT, 1440, 900, 24, 8, 16, SEG_GRAPH } },
83 { 0x180, { MM_DIRECT, 1440, 900, 32, 8, 16, SEG_GRAPH } },
84 { 0x181, { MM_DIRECT, 1400, 1050, 16, 8, 16, SEG_GRAPH } },
85 { 0x182, { MM_DIRECT, 1400, 1050, 24, 8, 16, SEG_GRAPH } },
86 { 0x183, { MM_DIRECT, 1400, 1050, 32, 8, 16, SEG_GRAPH } },
87 { 0x184, { MM_DIRECT, 1680, 1050, 16, 8, 16, SEG_GRAPH } },
88 { 0x185, { MM_DIRECT, 1680, 1050, 24, 8, 16, SEG_GRAPH } },
89 { 0x186, { MM_DIRECT, 1680, 1050, 32, 8, 16, SEG_GRAPH } },
90 { 0x187, { MM_DIRECT, 1920, 1200, 16, 8, 16, SEG_GRAPH } },
91 { 0x188, { MM_DIRECT, 1920, 1200, 24, 8, 16, SEG_GRAPH } },
92 { 0x189, { MM_DIRECT, 1920, 1200, 32, 8, 16, SEG_GRAPH } },
93 { 0x18a, { MM_DIRECT, 2560, 1600, 16, 8, 16, SEG_GRAPH } },
94 { 0x18b, { MM_DIRECT, 2560, 1600, 24, 8, 16, SEG_GRAPH } },
95 { 0x18c, { MM_DIRECT, 2560, 1600, 32, 8, 16, SEG_GRAPH } },
96 { 0x18d, { MM_DIRECT, 1280, 720, 16, 8, 16, SEG_GRAPH } },
97 { 0x18e, { MM_DIRECT, 1280, 720, 24, 8, 16, SEG_GRAPH } },
98 { 0x18f, { MM_DIRECT, 1280, 720, 32, 8, 16, SEG_GRAPH } },
99 { 0x190, { MM_DIRECT, 1920, 1080, 16, 8, 16, SEG_GRAPH } },
100 { 0x191, { MM_DIRECT, 1920, 1080, 24, 8, 16, SEG_GRAPH } },
101 { 0x192, { MM_DIRECT, 1920, 1080, 32, 8, 16, SEG_GRAPH } },
104 static int dispi_found VAR16 = 0;
106 static int is_bochsvga_mode(struct vgamode_s *vmode_g)
108 return (vmode_g >= &bochsvga_modes[0].info
109 && vmode_g <= &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)-1].info);
112 struct vgamode_s *bochsvga_find_mode(int mode)
114 struct bochsvga_mode *m = bochsvga_modes;
115 if (GET_GLOBAL(dispi_found))
116 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++)
117 if (GET_GLOBAL(m->mode) == mode)
119 return stdvga_find_mode(mode);
123 bochsvga_list_modes(u16 seg, u16 *dest, u16 *last)
125 struct bochsvga_mode *m = bochsvga_modes;
126 if (GET_GLOBAL(dispi_found)) {
127 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)] && dest<last; m++) {
128 u16 mode = GET_GLOBAL(m->mode);
131 SET_FARVAR(seg, *dest, mode);
135 stdvga_list_modes(seg, dest, last);
139 /****************************************************************
141 ****************************************************************/
143 static inline u16 dispi_read(u16 reg)
145 outw(reg, VBE_DISPI_IOPORT_INDEX);
146 return inw(VBE_DISPI_IOPORT_DATA);
148 static inline void dispi_write(u16 reg, u16 val)
150 outw(reg, VBE_DISPI_IOPORT_INDEX);
151 outw(val, VBE_DISPI_IOPORT_DATA);
155 bochsvga_dispi_enabled(void)
157 if (!GET_GLOBAL(dispi_found))
159 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
160 if (!(en & VBE_DISPI_ENABLED))
166 bochsvga_get_window(struct vgamode_s *vmode_g, int window)
168 if (!bochsvga_dispi_enabled())
169 return stdvga_get_window(vmode_g, window);
172 return dispi_read(VBE_DISPI_INDEX_BANK);
176 bochsvga_set_window(struct vgamode_s *vmode_g, int window, int val)
178 if (!bochsvga_dispi_enabled())
179 return stdvga_set_window(vmode_g, window, val);
182 dispi_write(VBE_DISPI_INDEX_BANK, val);
183 if (dispi_read(VBE_DISPI_INDEX_BANK) != val)
189 bochsvga_get_linelength(struct vgamode_s *vmode_g)
191 if (!bochsvga_dispi_enabled())
192 return stdvga_get_linelength(vmode_g);
193 return dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * vga_bpp(vmode_g) / 8;
197 bochsvga_set_linelength(struct vgamode_s *vmode_g, int val)
199 stdvga_set_linelength(vmode_g, val);
200 if (bochsvga_dispi_enabled()) {
201 int pixels = (val * 8) / vga_bpp(vmode_g);
202 dispi_write(VBE_DISPI_INDEX_VIRT_WIDTH, pixels);
208 bochsvga_get_displaystart(struct vgamode_s *vmode_g)
210 if (!bochsvga_dispi_enabled())
211 return stdvga_get_displaystart(vmode_g);
212 int bpp = vga_bpp(vmode_g);
213 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
214 int x = dispi_read(VBE_DISPI_INDEX_X_OFFSET);
215 int y = dispi_read(VBE_DISPI_INDEX_Y_OFFSET);
216 return x * bpp / 8 + linelength * y;
220 bochsvga_set_displaystart(struct vgamode_s *vmode_g, int val)
222 stdvga_set_displaystart(vmode_g, val);
223 if (bochsvga_dispi_enabled()) {
224 int bpp = vga_bpp(vmode_g);
225 int linelength = dispi_read(VBE_DISPI_INDEX_VIRT_WIDTH) * bpp / 8;
228 dispi_write(VBE_DISPI_INDEX_X_OFFSET, (val % linelength) * 8 / bpp);
229 dispi_write(VBE_DISPI_INDEX_Y_OFFSET, val / linelength);
235 bochsvga_get_dacformat(struct vgamode_s *vmode_g)
237 if (!bochsvga_dispi_enabled())
238 return stdvga_get_dacformat(vmode_g);
239 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
240 return (en & VBE_DISPI_8BIT_DAC) ? 8 : 6;
244 bochsvga_set_dacformat(struct vgamode_s *vmode_g, int val)
246 if (!bochsvga_dispi_enabled())
247 return stdvga_set_dacformat(vmode_g, val);
248 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
250 en &= ~VBE_DISPI_8BIT_DAC;
252 en |= VBE_DISPI_8BIT_DAC;
255 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
260 bochsvga_save_state(u16 seg, u16 *info)
262 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
263 SET_FARVAR(seg, *info, en);
265 if (!(en & VBE_DISPI_ENABLED))
268 for (i = VBE_DISPI_INDEX_XRES; i <= VBE_DISPI_INDEX_Y_OFFSET; i++)
269 if (i != VBE_DISPI_INDEX_ENABLE) {
270 u16 v = dispi_read(i);
271 SET_FARVAR(seg, *info, v);
278 bochsvga_restore_state(u16 seg, u16 *info)
280 u16 en = GET_FARVAR(seg, *info);
282 if (!(en & VBE_DISPI_ENABLED)) {
283 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
287 for (i = VBE_DISPI_INDEX_XRES; i <= VBE_DISPI_INDEX_Y_OFFSET; i++)
288 if (i == VBE_DISPI_INDEX_ENABLE) {
291 dispi_write(i, GET_FARVAR(seg, *info));
298 bochsvga_save_restore(int cmd, u16 seg, void *data)
300 int ret = stdvga_save_restore(cmd, seg, data);
301 if (ret < 0 || !(cmd & SR_REGISTERS) || !GET_GLOBAL(dispi_found))
304 u16 *info = (data + ret);
306 bochsvga_save_state(seg, info);
307 if (cmd & SR_RESTORE)
308 bochsvga_restore_state(seg, info);
309 return ret + (VBE_DISPI_INDEX_Y_OFFSET-VBE_DISPI_INDEX_XRES+1)*sizeof(u16);
313 /****************************************************************
315 ****************************************************************/
318 bochsvga_set_mode(struct vgamode_s *vmode_g, int flags)
320 if (GET_GLOBAL(dispi_found))
321 dispi_write(VBE_DISPI_INDEX_ENABLE, VBE_DISPI_DISABLED);
322 if (! is_bochsvga_mode(vmode_g))
323 return stdvga_set_mode(vmode_g, flags);
324 if (!GET_GLOBAL(dispi_found))
327 u8 memmodel = GET_GLOBAL(vmode_g->memmodel);
328 if (memmodel == MM_PLANAR)
329 stdvga_set_mode(stdvga_find_mode(0x6a), 0);
330 if (memmodel == MM_PACKED && !(flags & MF_NOPALETTE))
331 stdvga_set_packed_palette();
333 dispi_write(VBE_DISPI_INDEX_BPP, GET_GLOBAL(vmode_g->depth));
334 u16 width = GET_GLOBAL(vmode_g->width);
335 u16 height = GET_GLOBAL(vmode_g->height);
336 dispi_write(VBE_DISPI_INDEX_XRES, width);
337 dispi_write(VBE_DISPI_INDEX_YRES, height);
338 dispi_write(VBE_DISPI_INDEX_BANK, 0);
339 u16 bf = ((flags & MF_NOCLEARMEM ? VBE_DISPI_NOCLEARMEM : 0)
340 | (flags & MF_LINEARFB ? VBE_DISPI_LFB_ENABLED : 0));
341 dispi_write(VBE_DISPI_INDEX_ENABLE, VBE_DISPI_ENABLED | bf);
343 /* VGA compat setup */
344 u16 crtc_addr = VGAREG_VGA_CRTC_ADDRESS;
345 stdvga_crtc_write(crtc_addr, 0x11, 0x00);
346 stdvga_crtc_write(crtc_addr, 0x01, width / 8 - 1);
347 stdvga_set_linelength(vmode_g, width);
348 stdvga_crtc_write(crtc_addr, 0x12, height - 1);
350 if ((height - 1) & 0x0100)
352 if ((height - 1) & 0x0200)
354 stdvga_crtc_mask(crtc_addr, 0x07, 0x42, v);
356 stdvga_crtc_write(crtc_addr, 0x09, 0x00);
357 stdvga_crtc_mask(crtc_addr, 0x17, 0x00, 0x03);
358 stdvga_attr_mask(0x10, 0x00, 0x01);
359 stdvga_grdc_write(0x06, 0x05);
360 stdvga_sequ_write(0x02, 0x0f);
361 if (memmodel != MM_PLANAR) {
362 stdvga_crtc_mask(crtc_addr, 0x14, 0x00, 0x40);
363 stdvga_attr_mask(0x10, 0x00, 0x40);
364 stdvga_sequ_mask(0x04, 0x00, 0x08);
365 stdvga_grdc_mask(0x05, 0x20, 0x40);
367 stdvga_attrindex_write(0x20);
373 /****************************************************************
375 ****************************************************************/
380 int ret = stdvga_setup();
385 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID0);
386 if (dispi_read(VBE_DISPI_INDEX_ID) != VBE_DISPI_ID0) {
387 dprintf(1, "No VBE DISPI interface detected, falling back to stdvga\n");
391 dispi_write(VBE_DISPI_INDEX_ID, VBE_DISPI_ID5);
392 SET_VGA(dispi_found, 1);
394 if (GET_GLOBAL(HaveRunInit))
397 u32 lfb_addr = VBE_DISPI_LFB_PHYSICAL_ADDRESS;
398 int bdf = GET_GLOBAL(VgaBDF);
399 if (CONFIG_VGA_PCI && bdf >= 0) {
400 u16 vendor = pci_config_readw(bdf, PCI_VENDOR_ID);
403 case 0x15ad: /* qemu vmware vga */
406 default: /* stdvga, qxl, virtio */
410 u32 bar = pci_config_readl(bdf, PCI_BASE_ADDRESS_0 + barid * 4);
411 lfb_addr = bar & PCI_BASE_ADDRESS_MEM_MASK;
412 dprintf(1, "VBE DISPI: bdf %02x:%02x.%x, bar %d\n", pci_bdf_to_bus(bdf)
413 , pci_bdf_to_dev(bdf), pci_bdf_to_fn(bdf), barid);
416 SET_VGA(VBE_framebuffer, lfb_addr);
417 u32 totalmem = dispi_read(VBE_DISPI_INDEX_VIDEO_MEMORY_64K) * 64 * 1024;
418 SET_VGA(VBE_total_memory, totalmem);
419 SET_VGA(VBE_win_granularity, 64);
420 SET_VGA(VBE_capabilities, VBE_CAPABILITY_8BIT_DAC);
422 dprintf(1, "VBE DISPI: lfb_addr=%x, size %d MB\n",
423 lfb_addr, totalmem >> 20);
426 u16 en = dispi_read(VBE_DISPI_INDEX_ENABLE);
427 dispi_write(VBE_DISPI_INDEX_ENABLE, en | VBE_DISPI_GETCAPS);
428 u16 max_xres = dispi_read(VBE_DISPI_INDEX_XRES);
429 u16 max_bpp = dispi_read(VBE_DISPI_INDEX_BPP);
430 dispi_write(VBE_DISPI_INDEX_ENABLE, en);
431 struct bochsvga_mode *m = bochsvga_modes;
432 for (; m < &bochsvga_modes[ARRAY_SIZE(bochsvga_modes)]; m++) {
433 u16 width = GET_GLOBAL(m->info.width);
434 u16 height = GET_GLOBAL(m->info.height);
435 u8 depth = GET_GLOBAL(m->info.depth);
436 u32 mem = (height * DIV_ROUND_UP(width * vga_bpp(&m->info), 8)
437 * stdvga_vram_ratio(&m->info));
439 if (width > max_xres || depth > max_bpp || mem > totalmem) {
440 dprintf(1, "Removing mode %x\n", GET_GLOBAL(m->mode));
441 SET_VGA(m->mode, 0xffff);