1 // Code for handling OHCI USB controllers.
3 // Copyright (C) 2009 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "biosvar.h" // GET_LOWFLAT
8 #include "config.h" // CONFIG_*
9 #include "malloc.h" // free
10 #include "memmap.h" // PAGE_SIZE
11 #include "output.h" // dprintf
12 #include "pci.h" // pci_bdf_to_bus
13 #include "pci_ids.h" // PCI_CLASS_SERIAL_USB_OHCI
14 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
15 #include "string.h" // memset
16 #include "usb.h" // struct usb_s
17 #include "usb-ohci.h" // struct ohci_hcca
18 #include "util.h" // msleep
19 #include "x86.h" // readl
25 struct ohci_regs *regs;
31 struct ohci_regs *regs;
38 /****************************************************************
40 ****************************************************************/
42 // Check if device attached to port
44 ohci_hub_detect(struct usbhub_s *hub, u32 port)
46 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
47 u32 sts = readl(&cntl->regs->roothub_portstatus[port]);
48 return (sts & RH_PS_CCS) ? 1 : 0;
53 ohci_hub_disconnect(struct usbhub_s *hub, u32 port)
55 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
56 writel(&cntl->regs->roothub_portstatus[port], RH_PS_CCS|RH_PS_LSDA);
59 // Reset device on port
61 ohci_hub_reset(struct usbhub_s *hub, u32 port)
63 struct usb_ohci_s *cntl = container_of(hub->cntl, struct usb_ohci_s, usb);
64 writel(&cntl->regs->roothub_portstatus[port], RH_PS_PRS);
66 u32 end = timer_calc(USB_TIME_DRSTR * 2);
68 sts = readl(&cntl->regs->roothub_portstatus[port]);
69 if (!(sts & RH_PS_PRS))
70 // XXX - need to ensure USB_TIME_DRSTR time in reset?
72 if (timer_check(end)) {
75 ohci_hub_disconnect(hub, port);
81 if ((sts & (RH_PS_CCS|RH_PS_PES)) != (RH_PS_CCS|RH_PS_PES))
82 // Device no longer present
85 return !!(sts & RH_PS_LSDA);
88 static struct usbhub_op_s ohci_HubOp = {
89 .detect = ohci_hub_detect,
90 .reset = ohci_hub_reset,
91 .disconnect = ohci_hub_disconnect,
94 // Find any devices connected to the root hub.
96 check_ohci_ports(struct usb_ohci_s *cntl)
99 // Turn on power for all devices on roothub.
100 u32 rha = readl(&cntl->regs->roothub_a);
101 rha &= ~(RH_A_PSM | RH_A_OCPM);
102 writel(&cntl->regs->roothub_status, RH_HS_LPSC);
103 writel(&cntl->regs->roothub_b, RH_B_PPCM);
104 msleep((rha >> 24) * 2);
105 // XXX - need to sleep for USB_TIME_SIGATT if just powered up?
108 memset(&hub, 0, sizeof(hub));
109 hub.cntl = &cntl->usb;
110 hub.portcount = rha & RH_A_NDP;
111 hub.op = &ohci_HubOp;
117 /****************************************************************
119 ****************************************************************/
121 // Wait for next USB frame to start - for ensuring safe memory release.
123 ohci_waittick(struct ohci_regs *regs)
126 struct ohci_hcca *hcca = (void*)regs->hcca;
127 u32 startframe = hcca->frame_no;
128 u32 end = timer_calc(1000 * 5);
130 if (hcca->frame_no != startframe)
132 if (timer_check(end)) {
141 ohci_free_pipes(struct usb_ohci_s *cntl)
143 dprintf(7, "ohci_free_pipes %p\n", cntl);
145 u32 creg = readl(&cntl->regs->control);
146 if (creg & (OHCI_CTRL_CLE|OHCI_CTRL_BLE)) {
147 writel(&cntl->regs->control, creg & ~(OHCI_CTRL_CLE|OHCI_CTRL_BLE));
148 ohci_waittick(cntl->regs);
151 u32 *pos = &cntl->regs->ed_controlhead;
153 struct ohci_ed *next = (void*)*pos;
156 struct ohci_pipe *pipe = container_of(next, struct ohci_pipe, ed);
157 if (usb_is_freelist(&cntl->usb, &pipe->pipe)) {
158 *pos = next->hwNextED;
161 pos = &next->hwNextED;
165 writel(&cntl->regs->ed_controlcurrent, 0);
166 writel(&cntl->regs->ed_bulkcurrent, 0);
167 writel(&cntl->regs->control, creg);
168 cntl->usb.freelist = NULL;
172 start_ohci(struct usb_ohci_s *cntl, struct ohci_hcca *hcca)
174 u32 oldfminterval = readl(&cntl->regs->fminterval);
175 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
177 // XXX - check if already running?
180 writel(&cntl->regs->control, OHCI_USB_RESET | oldrwc);
181 readl(&cntl->regs->control); // flush writes
182 msleep(USB_TIME_DRSTR);
184 // Do software init (min 10us, max 2ms)
185 u32 end = timer_calc_usec(10);
186 writel(&cntl->regs->cmdstatus, OHCI_HCR);
188 u32 status = readl(&cntl->regs->cmdstatus);
189 if (! status & OHCI_HCR)
191 if (timer_check(end)) {
198 writel(&cntl->regs->ed_controlhead, 0);
199 writel(&cntl->regs->ed_bulkhead, 0);
200 writel(&cntl->regs->hcca, (u32)hcca);
203 u32 fi = oldfminterval & 0x3fff;
204 writel(&cntl->regs->fminterval
205 , (((oldfminterval & FIT) ^ FIT)
206 | fi | (((6 * (fi - 210)) / 7) << 16)));
207 writel(&cntl->regs->periodicstart, ((9 * fi) / 10) & 0x3fff);
208 readl(&cntl->regs->control); // flush writes
210 // XXX - verify that fminterval was setup correctly.
212 // Go into operational state
213 writel(&cntl->regs->control
214 , (OHCI_CTRL_CBSR | OHCI_CTRL_CLE | OHCI_CTRL_BLE | OHCI_CTRL_PLE
215 | OHCI_USB_OPER | oldrwc));
216 readl(&cntl->regs->control); // flush writes
222 stop_ohci(struct usb_ohci_s *cntl)
224 u32 oldrwc = readl(&cntl->regs->control) & OHCI_CTRL_RWC;
225 writel(&cntl->regs->control, oldrwc);
226 readl(&cntl->regs->control); // flush writes
230 configure_ohci(void *data)
232 struct usb_ohci_s *cntl = data;
235 struct ohci_hcca *hcca = memalign_high(256, sizeof(*hcca));
236 struct ohci_ed *intr_ed = malloc_high(sizeof(*intr_ed));
237 if (!hcca || !intr_ed) {
241 memset(hcca, 0, sizeof(*hcca));
242 memset(intr_ed, 0, sizeof(*intr_ed));
243 intr_ed->hwINFO = ED_SKIP;
245 for (i=0; i<ARRAY_SIZE(hcca->int_table); i++)
246 hcca->int_table[i] = (u32)intr_ed;
248 int ret = start_ohci(cntl, hcca);
252 int count = check_ohci_ports(cntl);
253 ohci_free_pipes(cntl);
266 ohci_controller_setup(struct pci_device *pci)
268 struct usb_ohci_s *cntl = malloc_tmphigh(sizeof(*cntl));
273 memset(cntl, 0, sizeof(*cntl));
275 cntl->usb.type = USB_TYPE_OHCI;
277 wait_preempt(); // Avoid pci_config_readl when preempting
279 u32 baseaddr = pci_config_readl(bdf, PCI_BASE_ADDRESS_0);
280 cntl->regs = (void*)(baseaddr & PCI_BASE_ADDRESS_MEM_MASK);
282 dprintf(1, "OHCI init on dev %02x:%02x.%x (regs=%p)\n"
283 , pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf)
284 , pci_bdf_to_fn(bdf), cntl->regs);
286 // Enable bus mastering and memory access.
287 pci_config_maskw(bdf, PCI_COMMAND
288 , 0, PCI_COMMAND_MASTER|PCI_COMMAND_MEMORY);
290 // XXX - check for and disable SMM control?
292 // Disable interrupts
293 writel(&cntl->regs->intrdisable, ~0);
294 writel(&cntl->regs->intrstatus, ~0);
296 run_thread(configure_ohci, cntl);
302 if (! CONFIG_USB_OHCI)
304 struct pci_device *pci;
306 if (pci_classprog(pci) == PCI_CLASS_SERIAL_USB_OHCI)
307 ohci_controller_setup(pci);
312 /****************************************************************
313 * End point communication
314 ****************************************************************/
316 // Setup fields in ed
318 ohci_desc2pipe(struct ohci_pipe *pipe, struct usbdevice_s *usbdev
319 , struct usb_endpoint_descriptor *epdesc)
321 usb_desc2pipe(&pipe->pipe, usbdev, epdesc);
322 pipe->ed.hwINFO = (ED_SKIP | usbdev->devaddr | (pipe->pipe.ep << 7)
323 | (epdesc->wMaxPacketSize << 16)
324 | (usbdev->speed ? ED_LOWSPEED : 0));
325 struct usb_ohci_s *cntl = container_of(
326 usbdev->hub->cntl, struct usb_ohci_s, usb);
327 pipe->regs = cntl->regs;
330 static struct usb_pipe *
331 ohci_alloc_intr_pipe(struct usbdevice_s *usbdev
332 , struct usb_endpoint_descriptor *epdesc)
334 struct usb_ohci_s *cntl = container_of(
335 usbdev->hub->cntl, struct usb_ohci_s, usb);
336 int frameexp = usb_get_period(usbdev, epdesc);
337 dprintf(7, "ohci_alloc_intr_pipe %p %d\n", &cntl->usb, frameexp);
341 int maxpacket = epdesc->wMaxPacketSize;
342 // Determine number of entries needed for 2 timer ticks.
343 int ms = 1<<frameexp;
344 int count = DIV_ROUND_UP(ticks_to_ms(2), ms) + 1;
345 struct ohci_pipe *pipe = malloc_low(sizeof(*pipe));
346 struct ohci_td *tds = malloc_low(sizeof(*tds) * count);
347 void *data = malloc_low(maxpacket * count);
348 if (!pipe || !tds || !data)
350 memset(pipe, 0, sizeof(*pipe));
351 ohci_desc2pipe(pipe, usbdev, epdesc);
352 pipe->ed.hwINFO &= ~ED_SKIP;
357 struct ohci_ed *ed = &pipe->ed;
358 ed->hwHeadP = (u32)&tds[0];
359 ed->hwTailP = (u32)&tds[count-1];
362 for (i=0; i<count-1; i++) {
363 tds[i].hwINFO = TD_DP_IN | TD_T_TOGGLE | TD_CC;
364 tds[i].hwCBP = (u32)data + maxpacket * i;
365 tds[i].hwNextTD = (u32)&tds[i+1];
366 tds[i].hwBE = tds[i].hwCBP + maxpacket - 1;
369 // Add to interrupt schedule.
370 struct ohci_hcca *hcca = (void*)cntl->regs->hcca;
372 // Add to existing interrupt entry.
373 struct ohci_ed *intr_ed = (void*)hcca->int_table[0];
374 ed->hwNextED = intr_ed->hwNextED;
376 intr_ed->hwNextED = (u32)ed;
378 int startpos = 1<<(frameexp-1);
379 ed->hwNextED = hcca->int_table[startpos];
381 for (i=startpos; i<ARRAY_SIZE(hcca->int_table); i+=ms)
382 hcca->int_table[i] = (u32)ed;
395 ohci_realloc_pipe(struct usbdevice_s *usbdev, struct usb_pipe *upipe
396 , struct usb_endpoint_descriptor *epdesc)
398 if (! CONFIG_USB_OHCI)
400 usb_add_freelist(upipe);
403 u8 eptype = epdesc->bmAttributes & USB_ENDPOINT_XFERTYPE_MASK;
404 if (eptype == USB_ENDPOINT_XFER_INT)
405 return ohci_alloc_intr_pipe(usbdev, epdesc);
406 struct usb_ohci_s *cntl = container_of(
407 usbdev->hub->cntl, struct usb_ohci_s, usb);
408 dprintf(7, "ohci_alloc_async_pipe %p\n", &cntl->usb);
410 struct usb_pipe *usbpipe = usb_get_freelist(&cntl->usb, eptype);
412 // Use previously allocated pipe.
413 struct ohci_pipe *pipe = container_of(usbpipe, struct ohci_pipe, pipe);
414 ohci_desc2pipe(pipe, usbdev, epdesc);
418 // Allocate a new queue head.
419 struct ohci_pipe *pipe;
420 if (eptype == USB_ENDPOINT_XFER_CONTROL)
421 pipe = malloc_tmphigh(sizeof(*pipe));
423 pipe = malloc_low(sizeof(*pipe));
428 memset(pipe, 0, sizeof(*pipe));
429 ohci_desc2pipe(pipe, usbdev, epdesc);
431 // Add queue head to controller list.
432 u32 *head = &cntl->regs->ed_controlhead;
433 if (eptype != USB_ENDPOINT_XFER_CONTROL)
434 head = &cntl->regs->ed_bulkhead;
435 pipe->ed.hwNextED = *head;
437 *head = (u32)&pipe->ed;
442 wait_ed(struct ohci_ed *ed, int timeout)
444 u32 end = timer_calc(timeout);
446 if ((ed->hwHeadP & ~(ED_C|ED_H)) == ed->hwTailP)
448 if (timer_check(end)) {
450 dprintf(1, "ohci ed info=%x tail=%x head=%x next=%x\n"
451 , ed->hwINFO, ed->hwTailP, ed->hwHeadP, ed->hwNextED);
459 #define OHCI_TD_ALIGN 16
462 ohci_send_pipe(struct usb_pipe *p, int dir, const void *cmd
463 , void *data, int datasize)
466 if (! CONFIG_USB_OHCI)
468 dprintf(7, "ohci_send_pipe %p\n", p);
469 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
471 // Allocate tds on stack (with required alignment)
472 u8 tdsbuf[sizeof(struct ohci_td) * STACKOTDS + OHCI_TD_ALIGN - 1];
473 struct ohci_td *tds = (void*)ALIGN((u32)tdsbuf, OHCI_TD_ALIGN), *td = tds;
474 memset(tds, 0, sizeof(*tds) * STACKOTDS);
476 // Setup transfer descriptors
477 u16 maxpacket = pipe->pipe.maxpacket;
478 u32 toggle = 0, statuscmd = OHCI_BLF;
480 // Send setup pid on control transfers
481 td->hwINFO = TD_DP_SETUP | TD_T_DATA0 | TD_CC;
482 td->hwCBP = (u32)cmd;
483 td->hwNextTD = (u32)&td[1];
484 td->hwBE = (u32)cmd + USB_CONTROL_SETUP_SIZE - 1;
487 statuscmd = OHCI_CLF;
489 u32 dest = (u32)data, dataend = dest + datasize;
490 while (dest < dataend) {
492 if (td >= &tds[STACKOTDS]) {
496 int maxtransfer = 2*PAGE_SIZE - (dest & (PAGE_SIZE-1));
497 int transfer = dataend - dest;
498 if (transfer > maxtransfer)
499 transfer = ALIGN_DOWN(maxtransfer, maxpacket);
500 td->hwINFO = (dir ? TD_DP_IN : TD_DP_OUT) | toggle | TD_CC;
502 td->hwNextTD = (u32)&td[1];
503 td->hwBE = dest + transfer - 1;
508 // Send status pid on control transfers
509 if (td >= &tds[STACKOTDS]) {
513 td->hwINFO = (dir ? TD_DP_OUT : TD_DP_IN) | TD_T_DATA1 | TD_CC;
515 td->hwNextTD = (u32)&td[1];
521 pipe->ed.hwHeadP = (u32)tds | (pipe->ed.hwHeadP & ED_C);
522 pipe->ed.hwTailP = (u32)td;
524 pipe->ed.hwINFO &= ~ED_SKIP;
525 writel(&pipe->regs->cmdstatus, statuscmd);
527 int ret = wait_ed(&pipe->ed, usb_xfer_time(p, datasize));
528 pipe->ed.hwINFO |= ED_SKIP;
530 ohci_waittick(pipe->regs);
535 ohci_poll_intr(struct usb_pipe *p, void *data)
538 if (! CONFIG_USB_OHCI)
541 struct ohci_pipe *pipe = container_of(p, struct ohci_pipe, pipe);
542 struct ohci_td *tds = GET_LOWFLAT(pipe->tds);
543 struct ohci_td *head = (void*)(GET_LOWFLAT(pipe->ed.hwHeadP) & ~(ED_C|ED_H));
544 struct ohci_td *tail = (void*)GET_LOWFLAT(pipe->ed.hwTailP);
545 int count = GET_LOWFLAT(pipe->count);
546 int pos = (tail - tds + 1) % count;
547 struct ohci_td *next = &tds[pos];
551 // XXX - check for errors.
554 int maxpacket = GET_LOWFLAT(pipe->pipe.maxpacket);
555 void *pipedata = GET_LOWFLAT((pipe->data));
556 void *intrdata = pipedata + maxpacket * pos;
557 memcpy_far(GET_SEG(SS), data, SEG_LOW, LOWFLAT2LOW(intrdata), maxpacket);
560 SET_LOWFLAT(tail->hwINFO, TD_DP_IN | TD_T_TOGGLE | TD_CC);
561 intrdata = pipedata + maxpacket * (tail-tds);
562 SET_LOWFLAT(tail->hwCBP, (u32)intrdata);
563 SET_LOWFLAT(tail->hwNextTD, (u32)next);
564 SET_LOWFLAT(tail->hwBE, (u32)intrdata + maxpacket - 1);
566 SET_LOWFLAT(pipe->ed.hwTailP, (u32)next);