1 // PCI SD Host Controller Interface
3 // Copyright (C) 2014 Kevin O'Connor <kevin@koconnor.net>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "block.h" // struct drive_s
8 #include "malloc.h" // malloc_fseg
9 #include "output.h" // znprintf
10 #include "pci.h" // pci_config_readl
11 #include "pci_ids.h" // PCI_CLASS_SYSTEM_SDHCI
12 #include "pci_regs.h" // PCI_BASE_ADDRESS_0
13 #include "romfile.h" // romfile_findprefix
14 #include "stacks.h" // wait_preempt
15 #include "std/disk.h" // DISK_RET_SUCCESS
16 #include "string.h" // memset
17 #include "util.h" // boot_add_hd
18 #include "x86.h" // writel
20 // SDHCI MMIO registers
55 u16 controller_version;
59 #define SCB_R0 0x00 // No response
60 #define SCB_R48 0x1a // Response R1 (no data), R5, R6, R7
61 #define SCB_R48d 0x3a // Response R1 (with data)
62 #define SCB_R48b 0x1b // Response R1b, R5b
63 #define SCB_R48o 0x02 // Response R3, R4
64 #define SCB_R136 0x09 // Response R2
65 #define SC_GO_IDLE_STATE ((0<<8) | SCB_R0)
66 #define SC_SEND_OP_COND ((1<<8) | SCB_R48o)
67 #define SC_ALL_SEND_CID ((2<<8) | SCB_R136)
68 #define SC_SEND_RELATIVE_ADDR ((3<<8) | SCB_R48)
69 #define SC_SELECT_DESELECT_CARD ((7<<8) | SCB_R48b)
70 #define SC_SEND_IF_COND ((8<<8) | SCB_R48)
71 #define SC_SEND_EXT_CSD ((8<<8) | SCB_R48d)
72 #define SC_SEND_CSD ((9<<8) | SCB_R136)
73 #define SC_READ_SINGLE ((17<<8) | SCB_R48d)
74 #define SC_READ_MULTIPLE ((18<<8) | SCB_R48d)
75 #define SC_WRITE_SINGLE ((24<<8) | SCB_R48d)
76 #define SC_WRITE_MULTIPLE ((25<<8) | SCB_R48d)
77 #define SC_APP_CMD ((55<<8) | SCB_R48)
78 #define SC_APP_SEND_OP_COND ((41<<8) | SCB_R48o)
81 #define SI_CMD_COMPLETE (1<<0)
82 #define SI_TRANS_DONE (1<<1)
83 #define SI_WRITE_READY (1<<4)
84 #define SI_READ_READY (1<<5)
85 #define SI_ERROR (1<<15)
87 // SDHCI present_state flags
88 #define SP_CMD_INHIBIT (1<<0)
89 #define SP_DAT_INHIBIT (1<<1)
90 #define SP_CARD_INSERTED (1<<16)
92 // SDHCI transfer_mode flags
93 #define ST_BLOCKCOUNT (1<<1)
94 #define ST_AUTO_CMD12 (1<<2)
95 #define ST_READ (1<<4)
96 #define ST_MULTIPLE (1<<5)
98 // SDHCI capabilities flags
99 #define SD_CAPLO_V33 (1<<24)
100 #define SD_CAPLO_V30 (1<<25)
101 #define SD_CAPLO_V18 (1<<26)
102 #define SD_CAPLO_BASECLOCK_SHIFT 8
103 #define SD_CAPLO_BASECLOCK_MASK 0xff
105 // SDHCI clock control flags
106 #define SCC_INTERNAL_ENABLE (1<<0)
107 #define SCC_STABLE (1<<1)
108 #define SCC_CLOCK_ENABLE (1<<2)
109 #define SCC_SDCLK_MASK 0xff
110 #define SCC_SDCLK_SHIFT 8
111 #define SCC_SDCLK_HI_MASK 0x300
112 #define SCC_SDCLK_HI_RSHIFT 2
114 // SDHCI power control flags
115 #define SPC_POWER_ON (1<<0)
120 // SDHCI software reset flags
123 #define SRF_DATA 0x04
125 // SDHCI result flags
126 #define SR_OCR_CCS (1<<30)
127 #define SR_OCR_NOTBUSY (1<<31)
130 #define SDHCI_POWER_OFF_TIME 1
131 #define SDHCI_POWER_ON_TIME 1
132 #define SDHCI_CLOCK_ON_TIME 1 // 74 clock cycles
133 #define SDHCI_POWERUP_TIMEOUT 1000
134 #define SDHCI_PIO_TIMEOUT 1000 // XXX - this is just made up
136 // Internal 'struct drive_s' storage for a detected card
138 struct drive_s drive;
139 struct sdhci_s *regs;
144 #define SF_MMC (1<<0)
145 #define SF_HIGHCAPACITY (1<<1)
147 // Repeatedly read a u16 register until any bit in a given mask is set
149 sdcard_waitw(u16 *reg, u16 mask)
151 u32 end = timer_calc(SDHCI_PIO_TIMEOUT);
156 if (timer_check(end)) {
164 // Send an sdhci reset
166 sdcard_reset(struct sdhci_s *regs, int flags)
168 writeb(®s->software_reset, flags);
169 u32 end = timer_calc(SDHCI_PIO_TIMEOUT);
170 while (readb(®s->software_reset))
171 if (timer_check(end)) {
178 // Send a command to the card.
180 sdcard_pio(struct sdhci_s *regs, int cmd, u32 *param)
182 u32 state = readl(®s->present_state);
183 dprintf(9, "sdcard_pio cmd %x %x %x\n", cmd, *param, state);
184 if ((state & SP_CMD_INHIBIT)
185 || ((cmd & 0x03) == 0x03 && state & SP_DAT_INHIBIT)) {
186 dprintf(1, "sdcard_pio not ready %x\n", state);
190 writel(®s->arg, *param);
191 writew(®s->cmd, cmd);
192 int ret = sdcard_waitw(®s->irq_status, SI_ERROR|SI_CMD_COMPLETE);
195 if (ret & SI_ERROR) {
196 u16 err = readw(®s->error_irq_status);
197 dprintf(3, "sdcard_pio command stop (code=%x)\n", err);
198 sdcard_reset(regs, SRF_CMD|SRF_DATA);
199 writew(®s->error_irq_status, err);
202 writew(®s->irq_status, SI_CMD_COMPLETE);
204 memcpy(param, regs->response, sizeof(regs->response));
205 dprintf(9, "sdcard cmd %x response %x %x %x %x\n"
206 , cmd, param[0], param[1], param[2], param[3]);
210 // Send an "app specific" command to the card.
212 sdcard_pio_app(struct sdhci_s *regs, int cmd, u32 *param)
215 int ret = sdcard_pio(regs, SC_APP_CMD, aparam);
218 return sdcard_pio(regs, cmd, param);
221 // Send a command to the card which transfers data.
223 sdcard_pio_transfer(struct sddrive_s *drive, int cmd, u32 addr
224 , void *data, int count)
227 writew(&drive->regs->block_size, DISK_SECTOR_SIZE);
228 writew(&drive->regs->block_count, count);
229 int isread = cmd != SC_WRITE_SINGLE && cmd != SC_WRITE_MULTIPLE;
230 u16 tmode = ((count > 1 ? ST_MULTIPLE|ST_AUTO_CMD12|ST_BLOCKCOUNT : 0)
231 | (isread ? ST_READ : 0));
232 writew(&drive->regs->transfer_mode, tmode);
233 if (!(drive->card_type & SF_HIGHCAPACITY))
234 addr *= DISK_SECTOR_SIZE;
235 u32 param[4] = { addr };
236 int ret = sdcard_pio(drive->regs, cmd, param);
240 u16 cbit = isread ? SI_READ_READY : SI_WRITE_READY;
242 ret = sdcard_waitw(&drive->regs->irq_status, cbit);
245 writew(&drive->regs->irq_status, cbit);
247 for (i=0; i<DISK_SECTOR_SIZE/4; i++) {
249 *(u32*)data = readl(&drive->regs->data);
251 writel(&drive->regs->data, *(u32*)data);
256 ret = sdcard_waitw(&drive->regs->irq_status, SI_TRANS_DONE);
259 writew(&drive->regs->irq_status, SI_TRANS_DONE);
263 // Read/write a block of data to/from the card.
265 sdcard_readwrite(struct disk_op_s *op, int iswrite)
267 struct sddrive_s *drive = container_of(
268 op->drive_gf, struct sddrive_s, drive);
269 int cmd = iswrite ? SC_WRITE_SINGLE : SC_READ_SINGLE;
271 cmd = iswrite ? SC_WRITE_MULTIPLE : SC_READ_MULTIPLE;
272 int ret = sdcard_pio_transfer(drive, cmd, op->lba, op->buf_fl, op->count);
274 return DISK_RET_EBADTRACK;
275 return DISK_RET_SUCCESS;
279 sdcard_process_op(struct disk_op_s *op)
283 switch (op->command) {
285 return sdcard_readwrite(op, 0);
287 return sdcard_readwrite(op, 1);
289 return default_process_op(op);
294 /****************************************************************
296 ****************************************************************/
299 sdcard_set_power(struct sdhci_s *regs)
301 u32 cap = readl(®s->cap_lo);
303 if (cap & SD_CAPLO_V33) {
306 } else if (cap & SD_CAPLO_V30) {
309 } else if (cap & SD_CAPLO_V18) {
313 dprintf(1, "SD controller unsupported volt range (%x)\n", cap);
316 writeb(®s->power_control, 0);
317 msleep(SDHCI_POWER_OFF_TIME);
318 writeb(®s->power_control, vbits | SPC_POWER_ON);
319 msleep(SDHCI_POWER_ON_TIME);
324 sdcard_set_frequency(struct sdhci_s *regs, u32 khz)
326 u16 ver = readw(®s->controller_version);
327 u32 cap = readl(®s->cap_lo);
328 u32 base_freq = (cap >> SD_CAPLO_BASECLOCK_SHIFT) & SD_CAPLO_BASECLOCK_MASK;
330 dprintf(1, "Unknown base frequency for SD controller\n");
334 u32 divisor = DIV_ROUND_UP(base_freq * 1000, khz);
336 if ((ver & 0xff) <= 0x01) {
337 divisor = divisor > 1 ? 1 << __fls(divisor-1) : 0;
338 creg = (divisor & SCC_SDCLK_MASK) << SCC_SDCLK_SHIFT;
340 divisor = DIV_ROUND_UP(divisor, 2);
341 creg = (divisor & SCC_SDCLK_MASK) << SCC_SDCLK_SHIFT;
342 creg |= (divisor & SCC_SDCLK_HI_MASK) >> SCC_SDCLK_HI_RSHIFT;
344 dprintf(3, "sdcard_set_frequency %d %d %x\n", base_freq, khz, creg);
345 writew(®s->clock_control, 0);
346 writew(®s->clock_control, creg | SCC_INTERNAL_ENABLE);
347 // Wait for frequency to become active
348 int ret = sdcard_waitw(®s->clock_control, SCC_STABLE);
352 writew(®s->clock_control, creg | SCC_INTERNAL_ENABLE | SCC_CLOCK_ENABLE);
356 // Obtain the disk size of an SD card
358 sdcard_get_capacity(struct sddrive_s *drive, u8 *csd)
360 // Original MMC/SD card capacity formula
361 u16 C_SIZE = (csd[6] >> 6) | (csd[7] << 2) | ((csd[8] & 0x03) << 10);
362 u8 C_SIZE_MULT = (csd[4] >> 7) | ((csd[5] & 0x03) << 1);
363 u8 READ_BL_LEN = csd[9] & 0x0f;
364 u32 count = (C_SIZE+1) << (C_SIZE_MULT + 2 + READ_BL_LEN - 9);
365 // Check for newer encoding formats.
366 u8 CSD_STRUCTURE = csd[14] >> 6;
367 if ((drive->card_type & SF_MMC) && CSD_STRUCTURE >= 2) {
368 // Get capacity from EXT_CSD register
370 int ret = sdcard_pio_transfer(drive, SC_SEND_EXT_CSD, 0, ext_csd, 1);
373 count = *(u32*)&ext_csd[212];
374 } else if (!(drive->card_type & SF_MMC) && CSD_STRUCTURE >= 1) {
375 // High capacity SD card
376 u32 C_SIZE2 = csd[5] | (csd[6] << 8) | ((csd[7] & 0x3f) << 16);
377 count = (C_SIZE2+1) << (19-9);
379 // Fill drive struct and return
380 drive->drive.blksize = DISK_SECTOR_SIZE;
381 drive->drive.sectors = count;
385 // Initialize an SD card
387 sdcard_card_setup(struct sddrive_s *drive, int volt, int prio)
389 struct sdhci_s *regs = drive->regs;
390 // Set controller to initialization clock rate
391 int ret = sdcard_set_frequency(regs, 400);
394 msleep(SDHCI_CLOCK_ON_TIME);
397 ret = sdcard_pio(regs, SC_GO_IDLE_STATE, param);
400 // Let card know SDHC/SDXC is supported and confirm voltage
401 u32 hcs = 0, vrange = (volt >= (1<<15) ? 0x100 : 0x200) | 0xaa;
403 ret = sdcard_pio(regs, SC_SEND_IF_COND, param);
404 if (!ret && param[0] == vrange)
406 // Verify SD card (instead of MMC or SDIO)
408 ret = sdcard_pio_app(regs, SC_APP_SEND_OP_COND, param);
410 // Check for MMC card
412 ret = sdcard_pio(regs, SC_SEND_OP_COND, param);
415 drive->card_type |= SF_MMC;
419 u32 end = timer_calc(SDHCI_POWERUP_TIMEOUT);
421 param[0] = hcs | volt; // high-capacity support and voltage level
422 if (drive->card_type & SF_MMC)
423 ret = sdcard_pio(regs, SC_SEND_OP_COND, param);
425 ret = sdcard_pio_app(regs, SC_APP_SEND_OP_COND, param);
428 if (param[0] & SR_OCR_NOTBUSY)
430 if (timer_check(end)) {
434 msleep(5); // Avoid flooding log when debugging
436 drive->card_type |= (param[0] & SR_OCR_CCS) ? SF_HIGHCAPACITY : 0;
437 // Select card (get cid, set rca, get csd, select card)
439 ret = sdcard_pio(regs, SC_ALL_SEND_CID, param);
443 memcpy(cid, param, sizeof(cid));
444 param[0] = drive->card_type & SF_MMC ? 0x0001 << 16 : 0x00;
445 ret = sdcard_pio(regs, SC_SEND_RELATIVE_ADDR, param);
448 u16 rca = drive->card_type & SF_MMC ? 0x0001 : param[0] >> 16;
449 param[0] = rca << 16;
450 ret = sdcard_pio(regs, SC_SEND_CSD, param);
454 memcpy(csd, param, sizeof(csd));
455 param[0] = rca << 16;
456 ret = sdcard_pio(regs, SC_SELECT_DESELECT_CARD, param);
459 // Set controller to data transfer clock rate
460 ret = sdcard_set_frequency(regs, 25000);
464 ret = sdcard_get_capacity(drive, csd);
469 for (i=0; i < (drive->card_type & SF_MMC ? 6 : 5); i++)
471 char *desc = znprintf(MAXDESCSIZE, "%s %s %dMiB"
472 , drive->card_type & SF_MMC ? "MMC drive" : "SD card"
473 , pnm, (u32)(drive->drive.sectors >> 11));
474 dprintf(1, "Found sdcard at %p: %s\n", regs, desc);
475 boot_add_hd(&drive->drive, desc, prio);
479 // Setup and configure an SD card controller
481 sdcard_controller_setup(struct sdhci_s *regs, int prio)
483 // Initialize controller
484 u32 present_state = readl(®s->present_state);
485 if (!(present_state & SP_CARD_INSERTED))
488 dprintf(3, "sdhci@%p ver=%x cap=%x %x\n", regs
489 , readw(®s->controller_version)
490 , readl(®s->cap_lo), readl(®s->cap_hi));
491 sdcard_reset(regs, SRF_ALL);
492 writew(®s->irq_signal, 0);
493 writew(®s->irq_enable, 0x01ff);
494 writew(®s->irq_status, readw(®s->irq_status));
495 writew(®s->error_signal, 0);
496 writew(®s->error_irq_enable, 0x01ff);
497 writew(®s->error_irq_status, readw(®s->error_irq_status));
498 writeb(®s->timeout_control, 0x0e); // Set to max timeout
499 int volt = sdcard_set_power(regs);
504 struct sddrive_s *drive = malloc_fseg(sizeof(*drive));
509 memset(drive, 0, sizeof(*drive));
510 drive->drive.type = DTYPE_SDCARD;
512 int ret = sdcard_card_setup(drive, volt, prio);
519 writeb(®s->power_control, 0);
520 writew(®s->clock_control, 0);
524 sdcard_pci_setup(void *data)
526 struct pci_device *pci = data;
527 wait_preempt(); // Avoid pci_config_readl when preempting
528 // XXX - bars dependent on slot index register in pci config space
529 u32 regs = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0);
530 regs &= PCI_BASE_ADDRESS_MEM_MASK;
531 pci_config_maskw(pci->bdf, PCI_COMMAND, 0,
532 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
533 int prio = bootprio_find_pci_device(pci);
534 sdcard_controller_setup((void*)regs, prio);
538 sdcard_romfile_setup(void *data)
540 struct romfile_s *file = data;
541 int prio = bootprio_find_named_rom(file->name, 0);
542 u32 addr = romfile_loadint(file->name, 0);
543 dprintf(1, "Starting sdcard controller check at addr %x\n", addr);
544 sdcard_controller_setup((void*)addr, prio);
553 struct romfile_s *file = NULL;
555 file = romfile_findprefix("etc/sdcard", file);
558 run_thread(sdcard_romfile_setup, file);
561 struct pci_device *pci;
563 if (pci->class != PCI_CLASS_SYSTEM_SDHCI || pci->prog_if >= 2)
564 // Not an SDHCI controller following SDHCI spec
566 run_thread(sdcard_pci_setup, pci);