1 // AMD PCscsi boot support.
3 // Copyright (C) 2012 Red Hat Inc.
6 // Paolo Bonzini <pbonzini@redhat.com>
8 // based on lsi-scsi.c which is written by:
9 // Gerd Hoffman <kraxel@redhat.com>
11 // This file may be distributed under the terms of the GNU LGPLv3 license.
13 #include "biosvar.h" // GET_GLOBALFLAT
14 #include "block.h" // struct drive_s
15 #include "blockcmd.h" // scsi_drive_setup
16 #include "config.h" // CONFIG_*
17 #include "fw/paravirt.h" // runningOnQEMU
18 #include "malloc.h" // free
19 #include "output.h" // dprintf
20 #include "pci.h" // foreachpci
21 #include "pci_ids.h" // PCI_DEVICE_ID
22 #include "pci_regs.h" // PCI_VENDOR_ID
23 #include "std/disk.h" // DISK_RET_SUCCESS
24 #include "string.h" // memset
25 #include "util.h" // usleep
28 #define ESP_TCMID 0x04
31 #define ESP_WBUSID 0x10
34 #define ESP_RSTAT 0x10
35 #define ESP_RINTR 0x14
36 #define ESP_RFLAGS 0x1c
38 #define ESP_DMA_CMD 0x40
39 #define ESP_DMA_STC 0x44
40 #define ESP_DMA_SPA 0x48
41 #define ESP_DMA_WBC 0x4c
42 #define ESP_DMA_WAC 0x50
43 #define ESP_DMA_STAT 0x54
44 #define ESP_DMA_SMDLA 0x58
45 #define ESP_DMA_WMAC 0x58c
47 #define ESP_CMD_DMA 0x80
48 #define ESP_CMD_RESET 0x02
49 #define ESP_CMD_TI 0x10
50 #define ESP_CMD_ICCS 0x11
51 #define ESP_CMD_SELATN 0x42
53 #define ESP_STAT_DI 0x01
54 #define ESP_STAT_CD 0x02
55 #define ESP_STAT_MSG 0x04
56 #define ESP_STAT_TC 0x10
58 #define ESP_INTR_DC 0x20
62 struct pci_device *pci;
69 esp_scsi_dma(u32 iobase, u32 buf, u32 len, int read)
71 outb(len & 0xff, iobase + ESP_TCLO);
72 outb((len >> 8) & 0xff, iobase + ESP_TCMID);
73 outb((len >> 16) & 0xff, iobase + ESP_TCHI);
74 outl(buf, iobase + ESP_DMA_SPA);
75 outl(len, iobase + ESP_DMA_STC);
76 outb(read ? 0x83 : 0x03, iobase + ESP_DMA_CMD);
80 esp_scsi_process_op(struct disk_op_s *op)
83 return DISK_RET_EBADTRACK;
84 struct esp_lun_s *llun_gf =
85 container_of(op->drive_gf, struct esp_lun_s, drive);
86 u16 target = GET_GLOBALFLAT(llun_gf->target);
87 u16 lun = GET_GLOBALFLAT(llun_gf->lun);
89 int blocksize = scsi_fill_cmd(op, cdbcmd, sizeof(cdbcmd));
91 return default_process_op(op);
92 u32 iobase = GET_GLOBALFLAT(llun_gf->iobase);
96 outb(target, iobase + ESP_WBUSID);
99 * We need to pass the LUN at the beginning of the command, and the FIFO
100 * is only 16 bytes, so we cannot support 16-byte CDBs. The alternative
101 * would be to use DMA for the 17-byte command too, which is quite
104 outb(lun, iobase + ESP_FIFO);
106 cdbcmd[1] |= lun << 5;
107 for (i = 0; i < 12; i++)
108 outb(cdbcmd[i], iobase + ESP_FIFO);
109 outb(ESP_CMD_SELATN, iobase + ESP_CMD);
112 u8 stat = inb(iobase + ESP_RSTAT);
114 /* Detect disconnected device. */
115 if (state == 0 && (inb(iobase + ESP_RINTR) & ESP_INTR_DC)) {
116 return DISK_RET_ENOTREADY;
119 /* HBA reads command, clears CD, sets TC -> do DMA if needed. */
120 if (state == 0 && (stat & ESP_STAT_TC)) {
122 if (op->count && blocksize) {
124 u32 count = (u32)op->count * blocksize;
125 esp_scsi_dma(iobase, (u32)op->buf_fl, count, scsi_is_read(op));
126 outb(ESP_CMD_TI | ESP_CMD_DMA, iobase + ESP_CMD);
131 /* At end of DMA TC is set again -> complete command. */
132 if (state == 1 && (stat & ESP_STAT_TC)) {
134 outb(ESP_CMD_ICCS, iobase + ESP_CMD);
138 /* Finally read data from the message in phase. */
139 if (state == 2 && (stat & ESP_STAT_MSG)) {
141 status = inb(iobase + ESP_FIFO);
142 inb(iobase + ESP_FIFO);
149 return DISK_RET_SUCCESS;
152 return DISK_RET_EBADTRACK;
156 esp_scsi_add_lun(struct pci_device *pci, u32 iobase, u8 target, u8 lun)
158 struct esp_lun_s *llun = malloc_fseg(sizeof(*llun));
163 memset(llun, 0, sizeof(*llun));
164 llun->drive.type = DTYPE_ESP_SCSI;
165 llun->drive.cntl_id = pci->bdf;
167 llun->target = target;
169 llun->iobase = iobase;
171 char *name = znprintf(16, "esp %02x:%02x.%x %d:%d",
172 pci_bdf_to_bus(pci->bdf), pci_bdf_to_dev(pci->bdf),
173 pci_bdf_to_fn(pci->bdf), target, lun);
174 int prio = bootprio_find_scsi_device(pci, target, lun);
175 int ret = scsi_drive_setup(&llun->drive, name, prio);
187 esp_scsi_scan_target(struct pci_device *pci, u32 iobase, u8 target)
189 esp_scsi_add_lun(pci, iobase, target, 0);
193 init_esp_scsi(struct pci_device *pci)
196 u32 iobase = pci_config_readl(pci->bdf, PCI_BASE_ADDRESS_0)
197 & PCI_BASE_ADDRESS_IO_MASK;
199 dprintf(1, "found esp at %02x:%02x.%x, io @ %x\n",
200 pci_bdf_to_bus(bdf), pci_bdf_to_dev(bdf),
201 pci_bdf_to_fn(bdf), iobase);
203 pci_config_maskw(bdf, PCI_COMMAND, 0, PCI_COMMAND_MASTER);
206 outb(ESP_CMD_RESET, iobase + ESP_CMD);
209 for (i = 0; i <= 7; i++)
210 esp_scsi_scan_target(pci, iobase, i);
219 if (!CONFIG_ESP_SCSI || !runningOnQEMU())
222 dprintf(3, "init esp\n");
224 struct pci_device *pci;
226 if (pci->vendor != PCI_VENDOR_ID_AMD
227 || pci->device != PCI_DEVICE_ID_AMD_SCSI)