1 // Low level AHCI disk access
3 // Copyright (C) 2010 Gerd Hoffmann <kraxel@redhat.com>
5 // This file may be distributed under the terms of the GNU LGPLv3 license.
7 #include "ahci.h" // CDB_CMD_READ_10
8 #include "ata.h" // ATA_CB_STAT
9 #include "biosvar.h" // GET_GLOBAL
10 #include "blockcmd.h" // CDB_CMD_READ_10
11 #include "malloc.h" // free
12 #include "output.h" // dprintf
13 #include "pci.h" // foreachpci
14 #include "pci_ids.h" // PCI_CLASS_STORAGE_OTHER
15 #include "pci_regs.h" // PCI_INTERRUPT_LINE
16 #include "stacks.h" // yield
17 #include "std/disk.h" // DISK_RET_SUCCESS
18 #include "string.h" // memset
19 #include "util.h" // timer_calc
20 #include "x86.h" // inb
22 #define AHCI_REQUEST_TIMEOUT 32000 // 32 seconds max for IDE ops
23 #define AHCI_RESET_TIMEOUT 500 // 500 miliseconds
24 #define AHCI_LINK_TIMEOUT 10 // 10 miliseconds
26 // prepare sata command fis
27 static void sata_prep_simple(struct sata_cmd_fis *fis, u8 command)
29 memset_fl(fis, 0, sizeof(*fis));
30 fis->command = command;
33 static void sata_prep_readwrite(struct sata_cmd_fis *fis,
34 struct disk_op_s *op, int iswrite)
39 memset_fl(fis, 0, sizeof(*fis));
41 if (op->count >= (1<<8) || lba + op->count >= (1<<28)) {
42 fis->sector_count2 = op->count >> 8;
43 fis->lba_low2 = lba >> 24;
44 fis->lba_mid2 = lba >> 32;
45 fis->lba_high2 = lba >> 40;
47 command = (iswrite ? ATA_CMD_WRITE_DMA_EXT
48 : ATA_CMD_READ_DMA_EXT);
50 command = (iswrite ? ATA_CMD_WRITE_DMA
53 fis->feature = 1; /* dma */
54 fis->command = command;
55 fis->sector_count = op->count;
57 fis->lba_mid = lba >> 8;
58 fis->lba_high = lba >> 16;
59 fis->device = ((lba >> 24) & 0xf) | ATA_CB_DH_LBA;
62 static void sata_prep_atapi(struct sata_cmd_fis *fis, u16 blocksize)
64 memset_fl(fis, 0, sizeof(*fis));
65 fis->command = ATA_CMD_PACKET;
66 fis->feature = 1; /* dma */
67 fis->lba_mid = blocksize;
68 fis->lba_high = blocksize >> 8;
71 // ahci register access helpers
72 static u32 ahci_ctrl_readl(struct ahci_ctrl_s *ctrl, u32 reg)
74 u32 addr = ctrl->iobase + reg;
75 return readl((void*)addr);
78 static void ahci_ctrl_writel(struct ahci_ctrl_s *ctrl, u32 reg, u32 val)
80 u32 addr = ctrl->iobase + reg;
81 writel((void*)addr, val);
84 static u32 ahci_port_to_ctrl(u32 pnr, u32 port_reg)
87 ctrl_reg += pnr * 0x80;
92 static u32 ahci_port_readl(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg)
94 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
95 return ahci_ctrl_readl(ctrl, ctrl_reg);
98 static void ahci_port_writel(struct ahci_ctrl_s *ctrl, u32 pnr, u32 reg, u32 val)
100 u32 ctrl_reg = ahci_port_to_ctrl(pnr, reg);
101 ahci_ctrl_writel(ctrl, ctrl_reg, val);
104 // submit ahci command + wait for result
105 static int ahci_command(struct ahci_port_s *port_gf, int iswrite, int isatapi,
106 void *buffer, u32 bsize)
108 u32 val, status, success, flags, intbits, error;
109 struct ahci_ctrl_s *ctrl = port_gf->ctrl;
110 struct ahci_cmd_s *cmd = port_gf->cmd;
111 struct ahci_fis_s *fis = port_gf->fis;
112 struct ahci_list_s *list = port_gf->list;
113 u32 pnr = port_gf->pnr;
116 cmd->fis.pmp_type = 1 << 7; /* cmd fis */
117 cmd->prdt[0].base = (u32)buffer;
118 cmd->prdt[0].baseu = 0;
119 cmd->prdt[0].flags = bsize-1;
121 flags = ((1 << 16) | /* one prd entry */
122 (iswrite ? (1 << 6) : 0) |
123 (isatapi ? (1 << 5) : 0) |
124 (5 << 0)); /* fis length (dwords) */
125 list[0].flags = flags;
127 list[0].base = (u32)(cmd);
130 dprintf(8, "AHCI/%d: send cmd ...\n", pnr);
131 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
133 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
134 ahci_port_writel(ctrl, pnr, PORT_SCR_ACT, 1);
135 ahci_port_writel(ctrl, pnr, PORT_CMD_ISSUE, 1);
137 u32 end = timer_calc(AHCI_REQUEST_TIMEOUT);
140 intbits = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
142 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, intbits);
143 if (intbits & 0x02) {
144 status = GET_LOWFLAT(fis->psfis[2]);
145 error = GET_LOWFLAT(fis->psfis[3]);
148 if (intbits & 0x01) {
149 status = GET_LOWFLAT(fis->rfis[2]);
150 error = GET_LOWFLAT(fis->rfis[3]);
154 if (timer_check(end)) {
160 dprintf(8, "AHCI/%d: ... intbits 0x%x, status 0x%x ...\n",
161 pnr, intbits, status);
162 } while (status & ATA_CB_STAT_BSY);
164 success = (0x00 == (status & (ATA_CB_STAT_BSY | ATA_CB_STAT_DF |
166 ATA_CB_STAT_RDY == (status & (ATA_CB_STAT_RDY)));
168 dprintf(8, "AHCI/%d: ... finished, status 0x%x, OK\n", pnr,
171 dprintf(2, "AHCI/%d: ... finished, status 0x%x, ERROR 0x%x\n", pnr,
174 // non-queued error recovery (AHCI 1.3 section 6.2.2.1)
175 // Clears PxCMD.ST to 0 to reset the PxCI register
176 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
177 ahci_port_writel(ctrl, pnr, PORT_CMD, val & ~PORT_CMD_START);
179 // waits for PxCMD.CR to clear to 0
181 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
182 if ((val & PORT_CMD_LIST_ON) == 0)
187 // Clears any error bits in PxSERR to enable capturing new errors
188 val = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
189 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, val);
191 // Clears status bits in PxIS as appropriate
192 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
193 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
195 // If PxTFD.STS.BSY or PxTFD.STS.DRQ is set to 1, issue
196 // a COMRESET to the device to put it in an idle state
197 val = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
198 if (val & (ATA_CB_STAT_BSY | ATA_CB_STAT_DRQ)) {
199 dprintf(2, "AHCI/%d: issue comreset\n", pnr);
200 val = ahci_port_readl(ctrl, pnr, PORT_SCR_CTL);
201 // set Device Detection Initialization (DET) to 1 for 1 ms for comreset
202 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val | 1);
204 ahci_port_writel(ctrl, pnr, PORT_SCR_CTL, val);
207 // Sets PxCMD.ST to 1 to enable issuing new commands
208 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
209 ahci_port_writel(ctrl, pnr, PORT_CMD, val | PORT_CMD_START);
211 return success ? 0 : -1;
214 #define CDROM_CDB_SIZE 12
216 int ahci_cmd_data(struct disk_op_s *op, void *cdbcmd, u16 blocksize)
221 struct ahci_port_s *port_gf = container_of(
222 op->drive_gf, struct ahci_port_s, drive);
223 struct ahci_cmd_s *cmd = port_gf->cmd;
227 sata_prep_atapi(&cmd->fis, blocksize);
228 for (i = 0; i < CDROM_CDB_SIZE; i++) {
229 cmd->atapi[i] = atapi[i];
231 rc = ahci_command(port_gf, 0, 1, op->buf_fl,
232 op->count * blocksize);
234 return DISK_RET_EBADTRACK;
235 return DISK_RET_SUCCESS;
238 // read/write count blocks from a harddrive, op->buf_fl must be word aligned
240 ahci_disk_readwrite_aligned(struct disk_op_s *op, int iswrite)
242 struct ahci_port_s *port_gf = container_of(
243 op->drive_gf, struct ahci_port_s, drive);
244 struct ahci_cmd_s *cmd = port_gf->cmd;
247 sata_prep_readwrite(&cmd->fis, op, iswrite);
248 rc = ahci_command(port_gf, iswrite, 0, op->buf_fl,
249 op->count * DISK_SECTOR_SIZE);
250 dprintf(8, "ahci disk %s, lba %6x, count %3x, buf %p, rc %d\n",
251 iswrite ? "write" : "read", (u32)op->lba, op->count, op->buf_fl, rc);
253 return DISK_RET_EBADTRACK;
254 return DISK_RET_SUCCESS;
257 // read/write count blocks from a harddrive.
259 ahci_disk_readwrite(struct disk_op_s *op, int iswrite)
261 // if caller's buffer is word aligned, use it directly
262 if (((u32) op->buf_fl & 1) == 0)
263 return ahci_disk_readwrite_aligned(op, iswrite);
265 // Use a word aligned buffer for AHCI I/O
267 struct disk_op_s localop = *op;
268 u8 *alignedbuf_fl = bounce_buf_fl;
269 u8 *position = op->buf_fl;
271 localop.buf_fl = alignedbuf_fl;
276 for (block = 0; block < op->count; block++) {
277 memcpy_fl (alignedbuf_fl, position, DISK_SECTOR_SIZE);
278 rc = ahci_disk_readwrite_aligned (&localop, 1);
281 position += DISK_SECTOR_SIZE;
286 for (block = 0; block < op->count; block++) {
287 rc = ahci_disk_readwrite_aligned (&localop, 0);
290 memcpy_fl (position, alignedbuf_fl, DISK_SECTOR_SIZE);
291 position += DISK_SECTOR_SIZE;
295 return DISK_RET_SUCCESS;
300 process_ahci_op(struct disk_op_s *op)
304 switch (op->command) {
306 return ahci_disk_readwrite(op, 0);
308 return ahci_disk_readwrite(op, 1);
314 return DISK_RET_SUCCESS;
316 dprintf(1, "AHCI: unknown disk command %d\n", op->command);
317 return DISK_RET_EPARAM;
322 ahci_port_reset(struct ahci_ctrl_s *ctrl, u32 pnr)
326 /* disable FIS + CMD */
327 u32 end = timer_calc(AHCI_RESET_TIMEOUT);
329 val = ahci_port_readl(ctrl, pnr, PORT_CMD);
330 if (!(val & (PORT_CMD_FIS_RX | PORT_CMD_START |
331 PORT_CMD_FIS_ON | PORT_CMD_LIST_ON)))
333 val &= ~(PORT_CMD_FIS_RX | PORT_CMD_START);
334 ahci_port_writel(ctrl, pnr, PORT_CMD, val);
335 if (timer_check(end)) {
342 /* disable + clear IRQs */
343 ahci_port_writel(ctrl, pnr, PORT_IRQ_MASK, 0);
344 val = ahci_port_readl(ctrl, pnr, PORT_IRQ_STAT);
346 ahci_port_writel(ctrl, pnr, PORT_IRQ_STAT, val);
349 static struct ahci_port_s*
350 ahci_port_alloc(struct ahci_ctrl_s *ctrl, u32 pnr)
352 struct ahci_port_s *port = malloc_tmp(sizeof(*port));
360 port->list = memalign_tmp(1024, 1024);
361 port->fis = memalign_tmp(256, 256);
362 port->cmd = memalign_tmp(256, 256);
363 if (port->list == NULL || port->fis == NULL || port->cmd == NULL) {
367 memset(port->list, 0, 1024);
368 memset(port->fis, 0, 256);
369 memset(port->cmd, 0, 256);
371 ahci_port_writel(ctrl, pnr, PORT_LST_ADDR, (u32)port->list);
372 ahci_port_writel(ctrl, pnr, PORT_FIS_ADDR, (u32)port->fis);
376 static void ahci_port_release(struct ahci_port_s *port)
378 ahci_port_reset(port->ctrl, port->pnr);
385 static struct ahci_port_s* ahci_port_realloc(struct ahci_port_s *port)
387 struct ahci_port_s *tmp;
390 tmp = malloc_fseg(sizeof(*port));
393 ahci_port_release(port);
400 ahci_port_reset(port->ctrl, port->pnr);
405 port->list = memalign_high(1024, 1024);
406 port->fis = memalign_high(256, 256);
407 port->cmd = memalign_high(256, 256);
409 ahci_port_writel(port->ctrl, port->pnr, PORT_LST_ADDR, (u32)port->list);
410 ahci_port_writel(port->ctrl, port->pnr, PORT_FIS_ADDR, (u32)port->fis);
412 cmd = ahci_port_readl(port->ctrl, port->pnr, PORT_CMD);
413 cmd |= (PORT_CMD_FIS_RX|PORT_CMD_START);
414 ahci_port_writel(port->ctrl, port->pnr, PORT_CMD, cmd);
421 /* See ahci spec chapter 10.1 "Software Initialization of HBA" */
422 static int ahci_port_setup(struct ahci_port_s *port)
424 struct ahci_ctrl_s *ctrl = port->ctrl;
426 char model[MAXMODEL+1];
428 u32 cmd, stat, err, tf;
431 /* enable FIS recv */
432 cmd = ahci_port_readl(ctrl, pnr, PORT_CMD);
433 cmd |= PORT_CMD_FIS_RX;
434 ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
437 cmd |= PORT_CMD_SPIN_UP;
438 ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
439 u32 end = timer_calc(AHCI_LINK_TIMEOUT);
441 stat = ahci_port_readl(ctrl, pnr, PORT_SCR_STAT);
442 if ((stat & 0x07) == 0x03) {
443 dprintf(2, "AHCI/%d: link up\n", port->pnr);
446 if (timer_check(end)) {
447 dprintf(2, "AHCI/%d: link down\n", port->pnr);
453 /* clear error status */
454 err = ahci_port_readl(ctrl, pnr, PORT_SCR_ERR);
456 ahci_port_writel(ctrl, pnr, PORT_SCR_ERR, err);
458 /* wait for device becoming ready */
459 end = timer_calc(AHCI_REQUEST_TIMEOUT);
461 tf = ahci_port_readl(ctrl, pnr, PORT_TFDATA);
462 if (!(tf & (ATA_CB_STAT_BSY |
465 if (timer_check(end)) {
467 dprintf(1, "AHCI/%d: device not ready (tf 0x%x)\n", port->pnr, tf);
474 cmd |= PORT_CMD_START;
475 ahci_port_writel(ctrl, pnr, PORT_CMD, cmd);
477 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_PACKET_DEVICE);
478 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
483 sata_prep_simple(&port->cmd->fis, ATA_CMD_IDENTIFY_DEVICE);
484 rc = ahci_command(port, 0, 0, buffer, sizeof(buffer));
489 port->drive.cntl_id = pnr;
490 port->drive.removable = (buffer[0] & 0x80) ? 1 : 0;
494 port->drive.type = DTYPE_AHCI;
495 port->drive.blksize = DISK_SECTOR_SIZE;
496 port->drive.pchs.cylinder = buffer[1];
497 port->drive.pchs.head = buffer[3];
498 port->drive.pchs.sector = buffer[6];
501 if (buffer[83] & (1 << 10)) // word 83 - lba48 support
502 sectors = *(u64*)&buffer[100]; // word 100-103
504 sectors = *(u32*)&buffer[60]; // word 60 and word 61
505 port->drive.sectors = sectors;
506 u64 adjsize = sectors >> 11;
507 char adjprefix = 'M';
508 if (adjsize >= (1 << 16)) {
512 port->desc = znprintf(MAXDESCSIZE
513 , "AHCI/%d: %s ATA-%d Hard-Disk (%u %ciBytes)"
515 , ata_extract_model(model, MAXMODEL, buffer)
516 , ata_extract_version(buffer)
517 , (u32)adjsize, adjprefix);
518 port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0);
520 // found cdrom (atapi)
521 port->drive.type = DTYPE_AHCI_ATAPI;
522 port->drive.blksize = CDROM_SECTOR_SIZE;
523 port->drive.sectors = (u64)-1;
524 u8 iscd = ((buffer[0] >> 8) & 0x1f) == 0x05;
526 dprintf(1, "AHCI/%d: atapi device isn't a cdrom\n", port->pnr);
529 port->desc = znprintf(MAXDESCSIZE
530 , "DVD/CD [AHCI/%d: %s ATAPI-%d DVD/CD]"
532 , ata_extract_model(model, MAXMODEL, buffer)
533 , ata_extract_version(buffer));
534 port->prio = bootprio_find_ata_device(ctrl->pci_tmp, pnr, 0);
539 // Detect any drives attached to a given controller.
541 ahci_port_detect(void *data)
543 struct ahci_port_s *port = data;
546 dprintf(2, "AHCI/%d: probing\n", port->pnr);
547 ahci_port_reset(port->ctrl, port->pnr);
548 rc = ahci_port_setup(port);
550 ahci_port_release(port);
552 port = ahci_port_realloc(port);
555 dprintf(1, "AHCI/%d: registering: \"%s\"\n", port->pnr, port->desc);
557 // Register with bcv system.
558 boot_add_hd(&port->drive, port->desc, port->prio);
561 boot_add_cd(&port->drive, port->desc, port->prio);
566 // Initialize an ata controller and detect its drives.
568 ahci_controller_setup(struct pci_device *pci)
570 struct ahci_ctrl_s *ctrl = malloc_fseg(sizeof(*ctrl));
571 struct ahci_port_s *port;
580 if (create_bounce_buf() < 0) {
588 ctrl->iobase = pci_config_readl(bdf, PCI_BASE_ADDRESS_5);
589 ctrl->irq = pci_config_readb(bdf, PCI_INTERRUPT_LINE);
590 dprintf(1, "AHCI controller at %02x.%x, iobase %x, irq %d\n",
591 bdf >> 3, bdf & 7, ctrl->iobase, ctrl->irq);
593 pci_config_maskw(bdf, PCI_COMMAND, 0,
594 PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER);
596 val = ahci_ctrl_readl(ctrl, HOST_CTL);
597 ahci_ctrl_writel(ctrl, HOST_CTL, val | HOST_CTL_AHCI_EN);
599 ctrl->caps = ahci_ctrl_readl(ctrl, HOST_CAP);
600 ctrl->ports = ahci_ctrl_readl(ctrl, HOST_PORTS_IMPL);
601 dprintf(2, "AHCI: cap 0x%x, ports_impl 0x%x\n",
602 ctrl->caps, ctrl->ports);
605 for (pnr = 0; pnr <= max; pnr++) {
606 if (!(ctrl->ports & (1 << pnr)))
608 port = ahci_port_alloc(ctrl, pnr);
611 run_thread(ahci_port_detect, port);
615 // Locate and init ahci controllers.
619 // Scan PCI bus for ATA adapters
620 struct pci_device *pci;
622 if (pci->class != PCI_CLASS_STORAGE_SATA)
624 if (pci->prog_if != 1 /* AHCI rev 1 */)
626 ahci_controller_setup(pci);
637 dprintf(3, "init ahci\n");