1 // System Management Mode support (on emulators)
3 // Copyright (C) 2008-2014 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2006 Fabrice Bellard
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "config.h" // CONFIG_*
11 #include "hw/pci.h" // pci_config_writel
12 #include "hw/pci_ids.h" // PCI_VENDOR_ID_INTEL
13 #include "hw/pci_regs.h" // PCI_DEVICE_ID
14 #include "output.h" // dprintf
15 #include "paravirt.h" // PORT_SMI_STATUS
16 #include "stacks.h" // HaveSmmCall32
17 #include "string.h" // memcpy
18 #include "util.h" // smm_setup
19 #include "x86.h" // wbinvd
22 * Check SMM state save area format (bits 0-15) and require support
23 * for SMBASE relocation.
25 #define SMM_REV_MASK 0x0002ffff
27 #define SMM_REV_I32 0x00020000
28 #define SMM_REV_I64 0x00020064
37 u32 eax, ecx, edx, ebx, esp, ebp, esi, edi, eip, eflags;
45 u64 rflags, rip, r15, r14, r13, r12, r11, r10, r9, r8;
46 u64 rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax;
52 struct smm_state backup1;
53 struct smm_state backup2;
65 u8 cmd = inb(PORT_SMI_CMD);
66 struct smm_layout *smm = MAKE_FLATPTR(cs, 0);
67 dprintf(DEBUG_HDL_smi, "handle_smi cmd=%x smbase=%p\n", cmd, smm);
69 if (smm == (void*)BUILD_SMM_INIT_ADDR) {
70 // relocate SMBASE to 0xa0000
71 u32 rev = smm->cpu.i32.smm_rev & SMM_REV_MASK;
72 if (rev == SMM_REV_I32) {
73 smm->cpu.i32.smm_base = BUILD_SMM_ADDR;
74 } else if (rev == SMM_REV_I64) {
75 smm->cpu.i64.smm_base = BUILD_SMM_ADDR;
80 // indicate to smm_relocate_and_restore() that the SMM code was executed
81 outb(0x00, PORT_SMI_STATUS);
83 if (CONFIG_CALL32_SMM) {
84 // Backup current cpu state for SMM trampolining
85 struct smm_layout *newsmm = (void*)BUILD_SMM_ADDR;
86 memcpy(&newsmm->backup1, &smm->cpu, sizeof(newsmm->backup1));
87 memcpy(&newsmm->backup2, &smm->cpu, sizeof(newsmm->backup2));
94 if (CONFIG_CALL32_SMM && cmd == CALL32SMM_CMDID) {
95 if (smm->cpu.i32.smm_rev == SMM_REV_I32) {
97 memcpy(regs, &smm->cpu.i32.eax, sizeof(regs));
98 if (smm->cpu.i32.ecx == CALL32SMM_ENTERID) {
99 dprintf(9, "smm cpu call pc=%x esp=%x\n", regs[3], regs[4]);
100 memcpy(&smm->backup2, &smm->cpu, sizeof(smm->backup2));
101 memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu));
102 memcpy(&smm->cpu.i32.eax, regs, sizeof(regs));
103 smm->cpu.i32.eip = regs[3];
104 } else if (smm->cpu.i32.ecx == CALL32SMM_RETURNID) {
105 dprintf(9, "smm cpu ret %x esp=%x\n", regs[3], regs[4]);
106 memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu));
107 memcpy(&smm->cpu.i32.eax, regs, sizeof(regs));
108 smm->cpu.i32.eip = regs[3];
110 } else if (smm->cpu.i64.smm_rev == SMM_REV_I64) {
112 memcpy(regs, &smm->cpu.i64.rdi, sizeof(regs));
113 if ((u32)smm->cpu.i64.rcx == CALL32SMM_ENTERID) {
114 memcpy(&smm->backup2, &smm->cpu, sizeof(smm->backup2));
115 memcpy(&smm->cpu, &smm->backup1, sizeof(smm->cpu));
116 memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs));
117 smm->cpu.i64.rip = (u32)regs[4];
118 } else if ((u32)smm->cpu.i64.rcx == CALL32SMM_RETURNID) {
119 memcpy(&smm->cpu, &smm->backup2, sizeof(smm->cpu));
120 memcpy(&smm->cpu.i64.rdi, regs, sizeof(regs));
121 smm->cpu.i64.rip = (u32)regs[4];
127 extern void entry_smi(void);
128 // movw %cs, %ax; ljmpw $SEG_BIOS, $(entry_smi - BUILD_BIOS_ADDR)
129 #define SMI_INSN (0xeac88c | ((u64)SEG_BIOS<<40) \
130 | ((u64)((u32)entry_smi - BUILD_BIOS_ADDR) << 24))
133 smm_save_and_copy(void)
135 // save original memory content
136 struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR;
137 struct smm_layout *smm = (void*)BUILD_SMM_ADDR;
138 memcpy(&smm->cpu, &initsmm->cpu, sizeof(smm->cpu));
139 memcpy(&smm->codeentry, &initsmm->codeentry, sizeof(smm->codeentry));
141 // Setup code entry point.
142 initsmm->codeentry = SMI_INSN;
146 smm_relocate_and_restore(void)
148 /* init APM status port */
149 outb(0x01, PORT_SMI_STATUS);
151 /* raise an SMI interrupt */
152 outb(0x00, PORT_SMI_CMD);
154 /* wait until SMM code executed */
155 while (inb(PORT_SMI_STATUS) != 0x00)
158 /* restore original memory content */
159 struct smm_layout *initsmm = (void*)BUILD_SMM_INIT_ADDR;
160 struct smm_layout *smm = (void*)BUILD_SMM_ADDR;
161 memcpy(&initsmm->cpu, &smm->cpu, sizeof(initsmm->cpu));
162 memcpy(&initsmm->codeentry, &smm->codeentry, sizeof(initsmm->codeentry));
164 // Setup code entry point.
165 smm->codeentry = SMI_INSN;
169 // This code is hardcoded for PIIX4 Power Management device.
170 static void piix4_apmc_smm_setup(int isabdf, int i440_bdf)
172 /* check if SMM init is already done */
173 u32 value = pci_config_readl(isabdf, PIIX_DEVACTB);
174 if (value & PIIX_DEVACTB_APMC_EN)
177 /* enable the SMM memory window */
178 pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x48);
182 /* enable SMI generation when writing to the APMC register */
183 pci_config_writel(isabdf, PIIX_DEVACTB, value | PIIX_DEVACTB_APMC_EN);
185 /* enable SMI generation */
186 value = inl(acpi_pm_base + PIIX_PMIO_GLBCTL);
187 outl(acpi_pm_base + PIIX_PMIO_GLBCTL, value | PIIX_PMIO_GLBCTL_SMI_EN);
189 smm_relocate_and_restore();
191 /* close the SMM memory window and enable normal SMM */
192 pci_config_writeb(i440_bdf, I440FX_SMRAM, 0x02 | 0x08);
195 /* PCI_VENDOR_ID_INTEL && PCI_DEVICE_ID_INTEL_ICH9_LPC */
196 void ich9_lpc_apmc_smm_setup(int isabdf, int mch_bdf)
198 /* check if SMM init is already done */
199 u32 value = inl(acpi_pm_base + ICH9_PMIO_SMI_EN);
200 if (value & ICH9_PMIO_SMI_EN_APMC_EN)
203 /* enable the SMM memory window */
204 pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x48);
208 /* enable SMI generation when writing to the APMC register */
209 outl(value | ICH9_PMIO_SMI_EN_APMC_EN | ICH9_PMIO_SMI_EN_GLB_SMI_EN,
210 acpi_pm_base + ICH9_PMIO_SMI_EN);
212 /* lock SMI generation */
213 value = pci_config_readw(isabdf, ICH9_LPC_GEN_PMCON_1);
214 pci_config_writel(isabdf, ICH9_LPC_GEN_PMCON_1,
215 value | ICH9_LPC_GEN_PMCON_1_SMI_LOCK);
217 smm_relocate_and_restore();
219 /* close the SMM memory window and enable normal SMM */
220 pci_config_writeb(mch_bdf, Q35_HOST_BRIDGE_SMRAM, 0x02 | 0x08);
223 static int SMMISADeviceBDF = -1, SMMPMDeviceBDF = -1;
226 smm_device_setup(void)
231 struct pci_device *isapci, *pmpci;
232 isapci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3);
233 pmpci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82441);
234 if (isapci && pmpci) {
235 SMMISADeviceBDF = isapci->bdf;
236 SMMPMDeviceBDF = pmpci->bdf;
239 isapci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9_LPC);
240 pmpci = pci_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q35_MCH);
241 if (isapci && pmpci) {
242 SMMISADeviceBDF = isapci->bdf;
243 SMMPMDeviceBDF = pmpci->bdf;
250 if (!CONFIG_USE_SMM || SMMISADeviceBDF < 0)
253 dprintf(3, "init smm\n");
254 u16 device = pci_config_readw(SMMISADeviceBDF, PCI_DEVICE_ID);
255 if (device == PCI_DEVICE_ID_INTEL_82371AB_3)
256 piix4_apmc_smm_setup(SMMISADeviceBDF, SMMPMDeviceBDF);
258 ich9_lpc_apmc_smm_setup(SMMISADeviceBDF, SMMPMDeviceBDF);