4 #include "types.h" // u16
6 #define PCI_DEVICE_ID_INTEL_Q35_MCH 0x29c0
7 #define Q35_HOST_BRIDGE_PAM0 0x90
8 #define Q35_HOST_BRIDGE_SMRAM 0x9d
9 #define Q35_HOST_BRIDGE_PCIEXBAR 0x60
10 #define Q35_HOST_BRIDGE_PCIEXBAR_SIZE (256 * 1024 * 1024)
11 #define Q35_HOST_BRIDGE_PCIEXBAR_ADDR 0xb0000000
12 #define Q35_HOST_BRIDGE_PCIEXBAREN ((u64)1)
13 #define Q35_HOST_PCIE_PCI_SEGMENT 0
14 #define Q35_HOST_PCIE_START_BUS_NUMBER 0
15 #define Q35_HOST_PCIE_END_BUS_NUMBER 255
17 #define PCI_DEVICE_ID_INTEL_ICH9_LPC 0x2918
18 #define ICH9_LPC_PMBASE 0x40
19 #define ICH9_LPC_PMBASE_RTE 0x1
21 #define ICH9_LPC_ACPI_CTRL 0x44
22 #define ICH9_LPC_ACPI_CTRL_ACPI_EN 0x80
23 #define ICH9_LPC_PIRQA_ROUT 0x60
24 #define ICH9_LPC_PIRQE_ROUT 0x68
25 #define ICH9_LPC_PIRQ_ROUT_IRQEN 0x80
26 #define ICH9_LPC_GEN_PMCON_1 0xa0
27 #define ICH9_LPC_GEN_PMCON_1_SMI_LOCK (1 << 4)
28 #define ICH9_LPC_PORT_ELCR1 0x4d0
29 #define ICH9_LPC_PORT_ELCR2 0x4d1
30 #define PCI_DEVICE_ID_INTEL_ICH9_SMBUS 0x2930
31 #define ICH9_SMB_SMB_BASE 0x20
32 #define ICH9_SMB_HOSTC 0x40
33 #define ICH9_SMB_HOSTC_HST_EN 0x01
35 #define ICH9_ACPI_ENABLE 0x2
36 #define ICH9_ACPI_DISABLE 0x3
38 /* ICH9 LPC PM I/O registers are 128 ports and 128-aligned */
39 #define ICH9_PMIO_GPE0_STS 0x20
40 #define ICH9_PMIO_GPE0_BLK_LEN 0x10
41 #define ICH9_PMIO_SMI_EN 0x30
42 #define ICH9_PMIO_SMI_EN_APMC_EN (1 << 5)
43 #define ICH9_PMIO_SMI_EN_GLB_SMI_EN (1 << 0)
45 /* FADT ACPI_ENABLE/ACPI_DISABLE */
46 #define ICH9_APM_ACPI_ENABLE 0x2
47 #define ICH9_APM_ACPI_DISABLE 0x3