6 // Configuration definitions.
8 //#define BUILD_APPNAME "QEMU"
9 //#define BUILD_CPUNAME8 "QEMUCPU "
10 //#define BUILD_APPNAME6 "QEMU "
11 //#define BUILD_APPNAME4 "QEMU"
12 #define BUILD_APPNAME "Bochs"
13 #define BUILD_CPUNAME8 "BOCHSCPU"
14 #define BUILD_APPNAME6 "BOCHS "
15 #define BUILD_APPNAME4 "BXPC"
17 // Maximum number of map entries in the e820 map
18 #define BUILD_MAX_E820 32
19 // Space to reserve in high-memory for tables
20 #define BUILD_MAX_HIGHTABLE (256*1024)
21 // Largest supported externaly facing drive id
22 #define BUILD_MAX_EXTDRIVE 16
23 // Number of bytes the smbios may be and still live in the f-segment
24 #define BUILD_MAX_SMBIOS_FSEG 600
26 #define BUILD_MODEL_ID 0xFC
27 #define BUILD_SUBMODEL_ID 0x00
28 #define BUILD_BIOS_REVISION 0x01
30 // Various memory addresses used by the code.
31 #define BUILD_STACK_ADDR 0x7000
32 #define BUILD_S3RESUME_STACK_ADDR 0x1000
33 #define BUILD_AP_BOOT_ADDR 0x10000
34 #define BUILD_EBDA_MINIMUM 0x90000
35 #define BUILD_LOWRAM_END 0xa0000
36 #define BUILD_ROM_START 0xc0000
37 #define BUILD_BIOS_ADDR 0xf0000
38 #define BUILD_BIOS_SIZE 0x10000
39 #define BUILD_EXTRA_STACK_SIZE 0x800
40 // 32KB for shadow ram copying (works around emulator deficiencies)
41 #define BUILD_BIOS_TMP_ADDR 0x30000
42 #define BUILD_SMM_INIT_ADDR 0x30000
43 #define BUILD_SMM_ADDR 0xa0000
45 #define BUILD_PCIMEM_START 0xe0000000
46 #define BUILD_PCIMEM_END 0xfec00000 /* IOAPIC is mapped at */
47 #define BUILD_PCIMEM64_START 0x8000000000ULL
48 #define BUILD_PCIMEM64_END 0x10000000000ULL
50 #define BUILD_IOAPIC_ADDR 0xfec00000
51 #define BUILD_IOAPIC_ID 0
52 #define BUILD_HPET_ADDRESS 0xfed00000
53 #define BUILD_APIC_ADDR 0xfee00000
56 #define BUILD_PCI_IRQS ((1<<5) | (1<<9) | (1<<10) | (1<<11))
58 // Important real-mode segments
59 #define SEG_IVT 0x0000
60 #define SEG_BDA 0x0040
61 #define SEG_BIOS 0xf000
63 // Segment definitions in protected mode (see rombios32_gdt in misc.c)
64 #define SEG32_MODE32_CS (1 << 3)
65 #define SEG32_MODE32_DS (2 << 3)
66 #define SEG32_MODE16_CS (3 << 3)
67 #define SEG32_MODE16_DS (4 << 3)
68 #define SEG32_MODE16BIG_CS (5 << 3)
69 #define SEG32_MODE16BIG_DS (6 << 3)
71 // Debugging levels. If non-zero and CONFIG_DEBUG_LEVEL is greater
72 // than the specified value, then the corresponding irq handler will
73 // report every enter event.
74 #define DEBUG_ISR_02 1
75 #define DEBUG_HDL_05 1
76 #define DEBUG_ISR_08 20
77 #define DEBUG_ISR_09 9
78 #define DEBUG_ISR_0e 9
79 #define DEBUG_HDL_10 20
80 #define DEBUG_HDL_11 2
81 #define DEBUG_HDL_12 2
82 #define DEBUG_HDL_13 10
83 #define DEBUG_HDL_14 2
84 #define DEBUG_HDL_15 9
85 #define DEBUG_HDL_16 9
86 #define DEBUG_HDL_17 2
87 #define DEBUG_HDL_18 1
88 #define DEBUG_HDL_19 1
89 #define DEBUG_HDL_1a 9
90 #define DEBUG_HDL_40 1
91 #define DEBUG_ISR_70 9
92 #define DEBUG_ISR_74 9
93 #define DEBUG_ISR_75 1
94 #define DEBUG_ISR_76 10
95 #define DEBUG_ISR_hwpic1 5
96 #define DEBUG_ISR_hwpic2 5
97 #define DEBUG_HDL_smi 9
98 #define DEBUG_HDL_smp 1
99 #define DEBUG_HDL_pnp 1
100 #define DEBUG_HDL_pmm 1
101 #define DEBUG_HDL_pcibios 9
102 #define DEBUG_HDL_apm 9
104 #define DEBUG_unimplemented 2
105 #define DEBUG_invalid 3
106 #define DEBUG_thread 2