1 // 16bit code to handle system clocks.
3 // Copyright (C) 2008-2010 Kevin O'Connor <kevin@koconnor.net>
4 // Copyright (C) 2002 MandrakeSoft S.A.
6 // This file may be distributed under the terms of the GNU LGPLv3 license.
8 #include "biosvar.h" // SET_BDA
9 #include "bregs.h" // struct bregs
10 #include "hw/pic.h" // pic_eoi1
11 #include "hw/rtc.h" // rtc_read
12 #include "hw/usb-hid.h" // usb_check_event
13 #include "output.h" // debug_enter
14 #include "stacks.h" // yield
15 #include "string.h" // memset
16 #include "util.h" // clock_setup
19 /****************************************************************
21 ****************************************************************/
26 return (val & 0xf) + ((val >> 4) * 10);
34 dprintf(3, "init timer\n");
39 u32 seconds = bcd2bin(rtc_read(CMOS_RTC_SECONDS));
40 u32 minutes = bcd2bin(rtc_read(CMOS_RTC_MINUTES));
41 u32 hours = bcd2bin(rtc_read(CMOS_RTC_HOURS));
42 u32 ticks = ticks_from_ms(((hours * 60 + minutes) * 60 + seconds) * 1000);
43 SET_BDA(timer_counter, ticks % TICKS_PER_DAY);
45 // Setup Century storage
47 Century = rtc_read(CMOS_CENTURY);
49 // Infer current century from the year.
50 u8 year = rtc_read(CMOS_RTC_YEAR);
57 enable_hwirq(0, FUNC16(entry_08));
58 enable_hwirq(8, FUNC16(entry_70));
62 /****************************************************************
63 * Standard clock functions
64 ****************************************************************/
66 // get current clock count
68 handle_1a00(struct bregs *regs)
71 u32 ticks = GET_BDA(timer_counter);
72 regs->cx = ticks >> 16;
74 regs->al = GET_BDA(timer_rollover);
75 SET_BDA(timer_rollover, 0); // reset flag
79 // Set Current Clock Count
81 handle_1a01(struct bregs *regs)
83 u32 ticks = (regs->cx << 16) | regs->dx;
84 SET_BDA(timer_counter, ticks);
85 SET_BDA(timer_rollover, 0); // reset flag
86 // XXX - should use set_code_success()?
93 handle_1a02(struct bregs *regs)
100 regs->dh = rtc_read(CMOS_RTC_SECONDS);
101 regs->cl = rtc_read(CMOS_RTC_MINUTES);
102 regs->ch = rtc_read(CMOS_RTC_HOURS);
103 regs->dl = rtc_read(CMOS_STATUS_B) & RTC_B_DSE;
111 handle_1a03(struct bregs *regs)
113 // Using a debugger, I notice the following masking/setting
114 // of bits in Status Register B, by setting Reg B to
115 // a few values and getting its value after INT 1A was called.
118 // before 1111 1101 0111 1101 0000 0000
119 // after 0110 0010 0110 0010 0000 0010
121 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
122 // My assumption: RegB = ((RegB & 01100000b) | 00000010b)
123 if (rtc_updating()) {
125 // fall through as if an update were not in progress
127 rtc_write(CMOS_RTC_SECONDS, regs->dh);
128 rtc_write(CMOS_RTC_MINUTES, regs->cl);
129 rtc_write(CMOS_RTC_HOURS, regs->ch);
130 // Set Daylight Savings time enabled bit to requested value
131 u8 val8 = ((rtc_read(CMOS_STATUS_B) & (RTC_B_PIE|RTC_B_AIE))
132 | RTC_B_24HR | (regs->dl & RTC_B_DSE));
133 rtc_write(CMOS_STATUS_B, val8);
135 regs->al = val8; // val last written to Reg B
141 handle_1a04(struct bregs *regs)
144 if (rtc_updating()) {
148 regs->cl = rtc_read(CMOS_RTC_YEAR);
149 regs->dh = rtc_read(CMOS_RTC_MONTH);
150 regs->dl = rtc_read(CMOS_RTC_DAY_MONTH);
151 regs->ch = GET_LOW(Century);
158 handle_1a05(struct bregs *regs)
160 // Using a debugger, I notice the following masking/setting
161 // of bits in Status Register B, by setting Reg B to
162 // a few values and getting its value after INT 1A was called.
164 // try#1 try#2 try#3 try#4
165 // before 1111 1101 0111 1101 0000 0010 0000 0000
166 // after 0110 1101 0111 1101 0000 0010 0000 0000
168 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
169 // My assumption: RegB = (RegB & 01111111b)
170 if (rtc_updating()) {
175 rtc_write(CMOS_RTC_YEAR, regs->cl);
176 rtc_write(CMOS_RTC_MONTH, regs->dh);
177 rtc_write(CMOS_RTC_DAY_MONTH, regs->dl);
178 SET_LOW(Century, regs->ch);
179 // clear halt-clock bit
180 u8 val8 = rtc_read(CMOS_STATUS_B) & ~RTC_B_SET;
181 rtc_write(CMOS_STATUS_B, val8);
183 regs->al = val8; // AL = val last written to Reg B
187 // Set Alarm Time in CMOS
189 handle_1a06(struct bregs *regs)
191 // Using a debugger, I notice the following masking/setting
192 // of bits in Status Register B, by setting Reg B to
193 // a few values and getting its value after INT 1A was called.
196 // before 1101 1111 0101 1111 0000 0000
197 // after 0110 1111 0111 1111 0010 0000
199 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
200 // My assumption: RegB = ((RegB & 01111111b) | 00100000b)
201 u8 val8 = rtc_read(CMOS_STATUS_B); // Get Status Reg B
203 if (val8 & RTC_B_AIE) {
204 // Alarm interrupt enabled already
208 if (rtc_updating()) {
210 // fall through as if an update were not in progress
212 rtc_write(CMOS_RTC_SECONDS_ALARM, regs->dh);
213 rtc_write(CMOS_RTC_MINUTES_ALARM, regs->cl);
214 rtc_write(CMOS_RTC_HOURS_ALARM, regs->ch);
215 // enable Status Reg B alarm bit, clear halt clock bit
216 rtc_write(CMOS_STATUS_B, (val8 & ~RTC_B_SET) | RTC_B_AIE);
222 handle_1a07(struct bregs *regs)
224 // Using a debugger, I notice the following masking/setting
225 // of bits in Status Register B, by setting Reg B to
226 // a few values and getting its value after INT 1A was called.
228 // try#1 try#2 try#3 try#4
229 // before 1111 1101 0111 1101 0010 0000 0010 0010
230 // after 0100 0101 0101 0101 0000 0000 0000 0010
232 // Bit4 in try#1 flipped in hardware (forced low) due to bit7=1
233 // My assumption: RegB = (RegB & 01010111b)
234 u8 val8 = rtc_read(CMOS_STATUS_B); // Get Status Reg B
235 // clear clock-halt bit, disable alarm bit
236 rtc_write(CMOS_STATUS_B, val8 & ~(RTC_B_SET|RTC_B_AIE));
238 regs->al = val8; // val last written to Reg B
244 handle_1aXX(struct bregs *regs)
246 set_unimplemented(regs);
249 // INT 1Ah Time-of-day Service Entry Point
251 handle_1a(struct bregs *regs)
253 debug_enter(regs, DEBUG_HDL_1a);
255 case 0x00: handle_1a00(regs); break;
256 case 0x01: handle_1a01(regs); break;
257 case 0x02: handle_1a02(regs); break;
258 case 0x03: handle_1a03(regs); break;
259 case 0x04: handle_1a04(regs); break;
260 case 0x05: handle_1a05(regs); break;
261 case 0x06: handle_1a06(regs); break;
262 case 0x07: handle_1a07(regs); break;
263 default: handle_1aXX(regs); break;
267 // INT 08h System Timer ISR Entry Point
271 debug_isr(DEBUG_ISR_08);
274 u32 counter = GET_BDA(timer_counter);
276 // compare to one days worth of timer ticks at 18.2 hz
277 if (counter >= TICKS_PER_DAY) {
278 // there has been a midnight rollover at this point
280 SET_BDA(timer_rollover, GET_BDA(timer_rollover) + 1);
282 SET_BDA(timer_counter, counter);
284 // Check for internal events.
288 // chain to user timer tick INT #0x1c
290 memset(&br, 0, sizeof(br));
292 call16_int(0x1c, &br);
298 /****************************************************************
300 ****************************************************************/
302 // Calculate the timer value at 'count' number of full timer ticks in
305 irqtimer_calc_ticks(u32 count)
307 return (GET_BDA(timer_counter) + count + 1) % TICKS_PER_DAY;
310 // Return the timer value that is 'msecs' time in the future.
312 irqtimer_calc(u32 msecs)
315 return GET_BDA(timer_counter);
316 return irqtimer_calc_ticks(ticks_from_ms(msecs));
319 // Check if the given timer value has passed.
321 irqtimer_check(u32 end)
323 return (((GET_BDA(timer_counter) + TICKS_PER_DAY - end) % TICKS_PER_DAY)
324 < (TICKS_PER_DAY/2));
328 /****************************************************************
330 ****************************************************************/
333 set_usertimer(u32 usecs, u16 seg, u16 offset)
335 if (GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING)
338 // Interval not already set.
339 SET_BDA(rtc_wait_flag, RWS_WAIT_PENDING); // Set status byte.
340 SET_BDA(user_wait_complete_flag, SEGOFF(seg, offset));
341 SET_BDA(user_wait_timeout, usecs);
347 clear_usertimer(void)
349 if (!(GET_BDA(rtc_wait_flag) & RWS_WAIT_PENDING))
351 // Turn off status byte.
352 SET_BDA(rtc_wait_flag, 0);
356 #define RET_ECLOCKINUSE 0x83
358 // Wait for CX:DX microseconds
360 handle_1586(struct bregs *regs)
362 // Use the rtc to wait for the specified time.
364 u32 count = (regs->cx << 16) | regs->dx;
365 int ret = set_usertimer(count, GET_SEG(SS), (u32)&statusflag);
367 set_code_invalid(regs, RET_ECLOCKINUSE);
375 // Set Interval requested.
377 handle_158300(struct bregs *regs)
379 int ret = set_usertimer((regs->cx << 16) | regs->dx, regs->es, regs->bx);
381 // Interval already set.
382 set_code_invalid(regs, RET_EUNSUPPORTED);
387 // Clear interval requested
389 handle_158301(struct bregs *regs)
396 handle_1583XX(struct bregs *regs)
398 set_code_unimplemented(regs, RET_EUNSUPPORTED);
403 handle_1583(struct bregs *regs)
406 case 0x00: handle_158300(regs); break;
407 case 0x01: handle_158301(regs); break;
408 default: handle_1583XX(regs); break;
412 #define USEC_PER_RTC DIV_ROUND_CLOSEST(1000000, 1024)
414 // int70h: IRQ8 - CMOS RTC
418 debug_isr(DEBUG_ISR_70);
420 // Check which modes are enabled and have occurred.
421 u8 registerB = rtc_read(CMOS_STATUS_B);
422 u8 registerC = rtc_read(CMOS_STATUS_C);
424 if (!(registerB & (RTC_B_PIE|RTC_B_AIE)))
426 if (registerC & RTC_B_AIE) {
427 // Handle Alarm Interrupt.
429 memset(&br, 0, sizeof(br));
431 call16_int(0x4a, &br);
433 if (!(registerC & RTC_B_PIE))
436 // Handle Periodic Interrupt.
440 if (!GET_BDA(rtc_wait_flag))
443 // Wait Interval (Int 15, AH=83) active.
444 u32 time = GET_BDA(user_wait_timeout); // Time left in microseconds.
445 if (time < USEC_PER_RTC) {
446 // Done waiting - write to specified flag byte.
447 struct segoff_s segoff = GET_BDA(user_wait_complete_flag);
448 u16 ptr_seg = segoff.seg;
449 u8 *ptr_far = (u8*)(segoff.offset+0);
450 u8 oldval = GET_FARVAR(ptr_seg, *ptr_far);
451 SET_FARVAR(ptr_seg, *ptr_far, oldval | 0x80);
456 time -= USEC_PER_RTC;
457 SET_BDA(user_wait_timeout, time);