10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
13 #include <ipxe/device.h>
14 #include <ipxe/tables.h>
15 #include <ipxe/pci_io.h>
18 #define PCI_VENDOR_ID 0x00
21 #define PCI_DEVICE_ID 0x02
24 #define PCI_COMMAND 0x04
25 #define PCI_COMMAND_IO 0x0001 /**< I/O space */
26 #define PCI_COMMAND_MEM 0x0002 /**< Memory space */
27 #define PCI_COMMAND_MASTER 0x0004 /**< Bus master */
28 #define PCI_COMMAND_INVALIDATE 0x0010 /**< Mem. write & invalidate */
29 #define PCI_COMMAND_PARITY 0x0040 /**< Parity error response */
30 #define PCI_COMMAND_SERR 0x0100 /**< SERR# enable */
31 #define PCI_COMMAND_INTX_DISABLE 0x0400 /**< Interrupt disable */
34 #define PCI_STATUS 0x06
35 #define PCI_STATUS_CAP_LIST 0x0010 /**< Capabilities list */
36 #define PCI_STATUS_PARITY 0x0100 /**< Master data parity error */
37 #define PCI_STATUS_REC_TARGET_ABORT 0x1000 /**< Received target abort */
38 #define PCI_STATUS_REC_MASTER_ABORT 0x2000 /**< Received master abort */
39 #define PCI_STATUS_SIG_SYSTEM_ERROR 0x4000 /**< Signalled system error */
40 #define PCI_STATUS_DETECTED_PARITY 0x8000 /**< Detected parity error */
43 #define PCI_REVISION 0x08
45 /** PCI cache line size */
46 #define PCI_CACHE_LINE_SIZE 0x0c
48 /** PCI latency timer */
49 #define PCI_LATENCY_TIMER 0x0d
51 /** PCI header type */
52 #define PCI_HEADER_TYPE 0x0e
53 #define PCI_HEADER_TYPE_NORMAL 0x00 /**< Normal header */
54 #define PCI_HEADER_TYPE_BRIDGE 0x01 /**< PCI-to-PCI bridge header */
55 #define PCI_HEADER_TYPE_CARDBUS 0x02 /**< CardBus header */
56 #define PCI_HEADER_TYPE_MASK 0x7f /**< Header type mask */
57 #define PCI_HEADER_TYPE_MULTI 0x80 /**< Multi-function device */
59 /** PCI base address registers */
60 #define PCI_BASE_ADDRESS(n) ( 0x10 + ( 4 * (n) ) )
61 #define PCI_BASE_ADDRESS_0 PCI_BASE_ADDRESS ( 0 )
62 #define PCI_BASE_ADDRESS_1 PCI_BASE_ADDRESS ( 1 )
63 #define PCI_BASE_ADDRESS_2 PCI_BASE_ADDRESS ( 2 )
64 #define PCI_BASE_ADDRESS_3 PCI_BASE_ADDRESS ( 3 )
65 #define PCI_BASE_ADDRESS_4 PCI_BASE_ADDRESS ( 4 )
66 #define PCI_BASE_ADDRESS_5 PCI_BASE_ADDRESS ( 5 )
67 #define PCI_BASE_ADDRESS_SPACE_IO 0x00000001UL /**< I/O BAR */
68 #define PCI_BASE_ADDRESS_IO_MASK 0x00000003UL /**< I/O BAR mask */
69 #define PCI_BASE_ADDRESS_MEM_TYPE_64 0x00000004UL /**< 64-bit memory */
70 #define PCI_BASE_ADDRESS_MEM_TYPE_MASK 0x00000006UL /**< Memory type mask */
71 #define PCI_BASE_ADDRESS_MEM_MASK 0x0000000fUL /**< Memory BAR mask */
73 /** PCI subsystem vendor ID */
74 #define PCI_SUBSYSTEM_VENDOR_ID 0x2c
76 /** PCI subsystem ID */
77 #define PCI_SUBSYSTEM_ID 0x2e
79 /** PCI expansion ROM base address */
80 #define PCI_ROM_ADDRESS 0x30
82 /** PCI capabilities pointer */
83 #define PCI_CAPABILITY_LIST 0x34
85 /** CardBus capabilities pointer */
86 #define PCI_CB_CAPABILITY_LIST 0x14
88 /** PCI interrupt line */
89 #define PCI_INTERRUPT_LINE 0x3c
92 #define PCI_CAP_ID 0x00
93 #define PCI_CAP_ID_PM 0x01 /**< Power management */
94 #define PCI_CAP_ID_VPD 0x03 /**< Vital product data */
95 #define PCI_CAP_ID_VNDR 0x09 /**< Vendor-specific */
96 #define PCI_CAP_ID_EXP 0x10 /**< PCI Express */
98 /** Next capability */
99 #define PCI_CAP_NEXT 0x01
101 /** Power management control and status */
102 #define PCI_PM_CTRL 0x04
103 #define PCI_PM_CTRL_STATE_MASK 0x0003 /**< Current power state */
104 #define PCI_PM_CTRL_PME_ENABLE 0x0100 /**< PME pin enable */
105 #define PCI_PM_CTRL_PME_STATUS 0x8000 /**< PME pin status */
107 /** Uncorrectable error status */
108 #define PCI_ERR_UNCOR_STATUS 0x04
110 /** Network controller */
111 #define PCI_CLASS_NETWORK 0x02
113 /** Serial bus controller */
114 #define PCI_CLASS_SERIAL 0x0c
115 #define PCI_CLASS_SERIAL_USB 0x03 /**< USB controller */
116 #define PCI_CLASS_SERIAL_USB_UHCI 0x00 /**< UHCI USB controller */
117 #define PCI_CLASS_SERIAL_USB_OHCI 0x10 /**< OHCI USB controller */
118 #define PCI_CLASS_SERIAL_USB_EHCI 0x20 /**< ECHI USB controller */
119 #define PCI_CLASS_SERIAL_USB_XHCI 0x30 /**< xHCI USB controller */
121 /** Construct PCI class
123 * @v base Base class (or PCI_ANY_ID)
124 * @v sub Subclass (or PCI_ANY_ID)
125 * @v progif Programming interface (or PCI_ANY_ID)
127 #define PCI_CLASS( base, sub, progif ) \
128 ( ( ( (base) & 0xff ) << 16 ) | ( ( (sub) & 0xff ) << 8 ) | \
129 ( ( (progif) & 0xff) << 0 ) )
131 /** A PCI device ID list entry */
132 struct pci_device_id {
139 /** Arbitrary driver data */
140 unsigned long driver_data;
143 /** Match-anything ID */
144 #define PCI_ANY_ID 0xffff
146 /** A PCI class ID */
147 struct pci_class_id {
154 /** Construct PCI class ID
156 * @v base Base class (or PCI_ANY_ID)
157 * @v sub Subclass (or PCI_ANY_ID)
158 * @v progif Programming interface (or PCI_ANY_ID)
160 #define PCI_CLASS_ID( base, sub, progif ) { \
161 .class = PCI_CLASS ( base, sub, progif ), \
162 .mask = ( ( ( ( (base) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 16 ) | \
163 ( ( ( (sub) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 8 ) | \
164 ( ( ( (progif) == PCI_ANY_ID ) ? 0x00 : 0xff ) << 0 ) ), \
169 /** Generic device */
173 * This is the physical address of the first valid memory BAR.
175 unsigned long membase;
179 * This is the physical address of the first valid I/O BAR.
181 unsigned long ioaddr;
188 /** Interrupt number */
190 /** Bus, device, and function (bus:dev.fn) number */
192 /** Driver for this device */
193 struct pci_driver *driver;
194 /** Driver-private data
196 * Use pci_set_drvdata() and pci_get_drvdata() to access this
200 /** Driver device ID */
201 struct pci_device_id *id;
207 struct pci_device_id *ids;
208 /** Number of entries in PCI ID table */
209 unsigned int id_count;
211 struct pci_class_id class;
216 * @ret rc Return status code
218 int ( * probe ) ( struct pci_device *pci );
224 void ( * remove ) ( struct pci_device *pci );
227 /** PCI driver table */
228 #define PCI_DRIVERS __table ( struct pci_driver, "pci_drivers" )
230 /** Declare a PCI driver */
231 #define __pci_driver __table_entry ( PCI_DRIVERS, 01 )
233 /** Declare a fallback PCI driver */
234 #define __pci_driver_fallback __table_entry ( PCI_DRIVERS, 02 )
236 #define PCI_BUS( busdevfn ) ( ( (busdevfn) >> 8 ) & 0xff )
237 #define PCI_SLOT( busdevfn ) ( ( (busdevfn) >> 3 ) & 0x1f )
238 #define PCI_FUNC( busdevfn ) ( ( (busdevfn) >> 0 ) & 0x07 )
239 #define PCI_BUSDEVFN( bus, slot, func ) \
240 ( ( (bus) << 8 ) | ( (slot) << 3 ) | ( (func) << 0 ) )
241 #define PCI_FIRST_FUNC( busdevfn ) ( (busdevfn) & ~0x07 )
242 #define PCI_LAST_FUNC( busdevfn ) ( (busdevfn) | 0x07 )
244 #define PCI_BASE_CLASS( class ) ( (class) >> 16 )
245 #define PCI_SUB_CLASS( class ) ( ( (class) >> 8 ) & 0xff )
246 #define PCI_PROG_INTF( class ) ( (class) & 0xff )
249 * PCI_ROM is used to build up entries in a struct pci_id array. It
250 * is also parsed by parserom.pl to generate Makefile rules and files
253 * PCI_ID can be used to generate entries without creating a
254 * corresponding ROM in the build process.
256 #define PCI_ID( _vendor, _device, _name, _description, _data ) { \
260 .driver_data = _data \
262 #define PCI_ROM( _vendor, _device, _name, _description, _data ) \
263 PCI_ID( _vendor, _device, _name, _description, _data )
265 /** PCI device debug message format */
266 #define PCI_FMT "PCI %02x:%02x.%x"
268 /** PCI device debug message arguments */
269 #define PCI_ARGS( pci ) \
270 PCI_BUS ( (pci)->busdevfn ), PCI_SLOT ( (pci)->busdevfn ), \
271 PCI_FUNC ( (pci)->busdevfn )
273 extern void adjust_pci_device ( struct pci_device *pci );
274 extern unsigned long pci_bar_start ( struct pci_device *pci,
276 extern int pci_read_config ( struct pci_device *pci );
277 extern int pci_find_next ( struct pci_device *pci, unsigned int busdevfn );
278 extern int pci_find_driver ( struct pci_device *pci );
279 extern int pci_probe ( struct pci_device *pci );
280 extern void pci_remove ( struct pci_device *pci );
281 extern int pci_find_capability ( struct pci_device *pci, int capability );
282 extern unsigned long pci_bar_size ( struct pci_device *pci, unsigned int reg );
285 * Initialise PCI device
288 * @v busdevfn PCI bus:dev.fn address
290 static inline void pci_init ( struct pci_device *pci, unsigned int busdevfn ) {
291 pci->busdevfn = busdevfn;
298 * @v driver PCI driver
299 * @v id PCI device ID
301 static inline void pci_set_driver ( struct pci_device *pci,
302 struct pci_driver *driver,
303 struct pci_device_id *id ) {
304 pci->driver = driver;
306 pci->dev.driver_name = id->name;
310 * Set PCI driver-private data
313 * @v priv Private data
315 static inline void pci_set_drvdata ( struct pci_device *pci, void *priv ) {
320 * Get PCI driver-private data
323 * @ret priv Private data
325 static inline void * pci_get_drvdata ( struct pci_device *pci ) {
329 #endif /* _IPXE_PCI_H */