2 * vxge-main.h: iPXE driver for Neterion Inc's X3100 Series 10GbE
3 * PCIe I/O Virtualized Server Adapter.
5 * Copyright(c) 2002-2010 Neterion Inc.
7 * This software may be used and distributed according to the terms of
8 * the GNU General Public License (GPL), incorporated herein by
9 * reference. Drivers based on or derived from this code fall under
10 * the GPL and must retain the authorship, copyright and license
15 FILE_LICENCE(GPL2_ONLY);
21 #include "vxge_traffic.h"
22 #include "vxge_config.h"
24 #define VXGE_DRIVER_NAME "vxge"
25 #define VXGE_DRIVER_VENDOR "Neterion, Inc"
27 #ifndef PCI_VENDOR_ID_S2IO
28 #define PCI_VENDOR_ID_S2IO 0x17D5
31 #ifndef PCI_DEVICE_ID_TITAN_WIN
32 #define PCI_DEVICE_ID_TITAN_WIN 0x5733
35 #ifndef PCI_DEVICE_ID_TITAN_UNI
36 #define PCI_DEVICE_ID_TITAN_UNI 0x5833
39 #define VXGE_HW_TITAN1_PCI_REVISION 1
40 #define VXGE_HW_TITAN1A_PCI_REVISION 2
42 #define VXGE_HP_ISS_SUBSYS_VENDORID 0x103C
43 #define VXGE_HP_ISS_SUBSYS_DEVICEID_1 0x323B
44 #define VXGE_HP_ISS_SUBSYS_DEVICEID_2 0x323C
46 #define VXGE_USE_DEFAULT 0xffffffff
47 #define VXGE_HW_VPATH_MSIX_ACTIVE 4
48 #define VXGE_ALARM_MSIX_ID 2
49 #define VXGE_HW_RXSYNC_FREQ_CNT 4
50 #define VXGE_LL_RX_COPY_THRESHOLD 256
51 #define VXGE_DEF_FIFO_LENGTH 84
54 #define PORT_STEERING 0x1
55 #define RTH_TCP_UDP_STEERING 0x2
56 #define RTH_IPV4_STEERING 0x3
57 #define RTH_IPV6_EX_STEERING 0x4
58 #define RTH_BUCKET_SIZE 8
60 #define TX_PRIORITY_STEERING 1
61 #define TX_VLAN_STEERING 2
62 #define TX_PORT_STEERING 3
63 #define TX_MULTIQ_STEERING 4
65 #define VXGE_HW_PROM_MODE_ENABLE 1
66 #define VXGE_HW_PROM_MODE_DISABLE 0
68 #define VXGE_HW_FW_UPGRADE_DISABLE 0
69 #define VXGE_HW_FW_UPGRADE_ALL 1
70 #define VXGE_HW_FW_UPGRADE_FORCE 2
71 #define VXGE_HW_FUNC_MODE_DISABLE 0
73 #define VXGE_TTI_BTIMER_VAL 250000
74 #define VXGE_T1A_TTI_LTIMER_VAL 80
75 #define VXGE_T1A_TTI_RTIMER_VAL 400
77 #define VXGE_TTI_LTIMER_VAL 1000
78 #define VXGE_TTI_RTIMER_VAL 0
79 #define VXGE_RTI_BTIMER_VAL 250
80 #define VXGE_RTI_LTIMER_VAL 100
81 #define VXGE_RTI_RTIMER_VAL 0
82 #define VXGE_FIFO_INDICATE_MAX_PKTS VXGE_DEF_FIFO_LENGTH
83 #define VXGE_ISR_POLLING_CNT 8
84 #define VXGE_MAX_CONFIG_DEV 0xFF
85 #define VXGE_EXEC_MODE_DISABLE 0
86 #define VXGE_EXEC_MODE_ENABLE 1
87 #define VXGE_MAX_CONFIG_PORT 1
88 #define VXGE_ALL_VID_DISABLE 0
89 #define VXGE_ALL_VID_ENABLE 1
90 #define VXGE_PAUSE_CTRL_DISABLE 0
91 #define VXGE_PAUSE_CTRL_ENABLE 1
93 #define TTI_TX_URANGE_A 5
94 #define TTI_TX_URANGE_B 15
95 #define TTI_TX_URANGE_C 40
96 #define TTI_TX_UFC_A 5
97 #define TTI_TX_UFC_B 40
98 #define TTI_TX_UFC_C 60
99 #define TTI_TX_UFC_D 100
100 #define TTI_T1A_TX_UFC_A 30
101 #define TTI_T1A_TX_UFC_B 80
103 /* Slope - (max_mtu - min_mtu)/(max_mtu_ufc - min_mtu_ufc) */
105 /* 60 - 9k Mtu, 140 - 1.5k mtu */
106 #define TTI_T1A_TX_UFC_C(mtu) (60 + ((VXGE_HW_MAX_MTU - mtu)/93))
109 /* 100 - 9k Mtu, 300 - 1.5k mtu */
110 #define TTI_T1A_TX_UFC_D(mtu) (100 + ((VXGE_HW_MAX_MTU - mtu)/37))
112 #define RTI_RX_URANGE_A 5
113 #define RTI_RX_URANGE_B 15
114 #define RTI_RX_URANGE_C 40
115 #define RTI_T1A_RX_URANGE_A 1
116 #define RTI_T1A_RX_URANGE_B 20
117 #define RTI_T1A_RX_URANGE_C 50
118 #define RTI_RX_UFC_A 1
119 #define RTI_RX_UFC_B 5
120 #define RTI_RX_UFC_C 10
121 #define RTI_RX_UFC_D 15
122 #define RTI_T1A_RX_UFC_B 20
123 #define RTI_T1A_RX_UFC_C 50
124 #define RTI_T1A_RX_UFC_D 60
127 * The interrupt rate is maintained at 3k per second with the moderation
128 * parameters for most traffics but not all. This is the maximum interrupt
129 * count per allowed per function with INTA or per vector in the case of in a
130 * MSI-X 10 millisecond time period. Enabled only for Titan 1A.
132 #define VXGE_T1A_MAX_INTERRUPT_COUNT 100
134 #define VXGE_ENABLE_NAPI 1
135 #define VXGE_DISABLE_NAPI 0
136 #define VXGE_LRO_MAX_BYTES 0x4000
137 #define VXGE_T1A_LRO_MAX_BYTES 0xC000
139 #define VXGE_HW_MIN_VPATH_TX_BW_SUPPORT 0
140 #define VXGE_HW_MAX_VPATH_TX_BW_SUPPORT 7
142 /* Milli secs timer period */
143 #define VXGE_TIMER_DELAY 10000
145 #define VXGE_TIMER_COUNT (2 * 60)
147 #define VXGE_LL_MAX_FRAME_SIZE(dev) ((dev)->mtu + VXGE_HW_MAC_HEADER_MAX_SIZE)
149 #define VXGE_REG_DUMP_BUFSIZE 65000
151 #define is_mf(function_mode) \
152 ((function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION) || \
153 (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_17) || \
154 (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_2) || \
155 (function_mode == VXGE_HW_FUNCTION_MODE_MULTI_FUNCTION_4))
157 #define is_titan1(dev_id, rev) (((dev_id == PCI_DEVICE_ID_TITAN_UNI) || \
158 (dev_id == PCI_DEVICE_ID_TITAN_WIN)) && \
159 (rev == VXGE_HW_TITAN1_PCI_REVISION))
161 /* These flags represent the devices temporary state */
162 #define __VXGE_STATE_RESET_CARD 0x01
163 #define __VXGE_STATE_CARD_UP 0x02
165 #define test_bit(bit, loc) ((bit) & (loc))
166 #define set_bit(bit, loc) do { (loc) |= (bit); } while (0);
167 #define clear_bit(bit, loc) do { (loc) &= ~(bit); } while (0);
169 #define msleep(n) mdelay(n)
172 struct net_device *ndev;
173 struct pci_device *pdev;
174 struct __vxge_hw_fifo *fifoh;
178 struct net_device *ndev;
179 struct pci_device *pdev;
180 struct __vxge_hw_ring *ringh;
185 struct vxge_fifo fifo;
186 struct vxge_ring ring;
188 /* Actual vpath id for this vpath in the device - 0 to 16 */
192 u8 (macaddr)[ETH_ALEN];
193 u8 (macmask)[ETH_ALEN];
194 struct vxgedev *vdev;
195 struct __vxge_hw_virtualpath *vpathh;
199 struct net_device *ndev;
200 struct pci_device *pdev;
201 struct __vxge_hw_device *devh;
206 struct vxge_vpath vpath;
211 char fw_version[VXGE_HW_FW_STRLEN];
214 void vxge_vpath_intr_enable(struct vxgedev *vdev, int vp_id);
216 void vxge_vpath_intr_disable(struct vxgedev *vdev, int vp_id);
218 int vxge_reset(struct vxgedev *vdev);
221 vxge_xmit_compl(struct __vxge_hw_fifo *fifo_hw,
222 struct vxge_hw_fifo_txd *txdp, enum vxge_hw_fifo_tcode tcode);
224 void vxge_close_vpaths(struct vxgedev *vdev);
226 int vxge_open_vpaths(struct vxgedev *vdev);
228 enum vxge_hw_status vxge_reset_all_vpaths(struct vxgedev *vdev);