5 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
23 FILE_LICENCE ( GPL2_OR_LATER );
28 * VMware vmxnet3 virtual NIC driver
34 /** Maximum number of TX queues */
35 #define VMXNET3_MAX_TX_QUEUES 8
37 /** Maximum number of RX queues */
38 #define VMXNET3_MAX_RX_QUEUES 16
40 /** Maximum number of interrupts */
41 #define VMXNET3_MAX_INTRS 25
43 /** Maximum packet size */
44 #define VMXNET3_MAX_PACKET_LEN 0x4000
46 /** "PT" PCI BAR address */
47 #define VMXNET3_PT_BAR PCI_BASE_ADDRESS_0
49 /** "PT" PCI BAR size */
50 #define VMXNET3_PT_LEN 0x1000
52 /** Interrupt Mask Register */
53 #define VMXNET3_PT_IMR 0x0
55 /** Transmit producer index */
56 #define VMXNET3_PT_TXPROD 0x600
58 /** Rx producer index for ring 1 */
59 #define VMXNET3_PT_RXPROD 0x800
61 /** Rx producer index for ring 2 */
62 #define VMXNET3_PT_RXPROD2 0xa00
64 /** "VD" PCI BAR address */
65 #define VMXNET3_VD_BAR PCI_BASE_ADDRESS_1
67 /** "VD" PCI BAR size */
68 #define VMXNET3_VD_LEN 0x1000
70 /** vmxnet3 Revision Report Selection */
71 #define VMXNET3_VD_VRRS 0x0
73 /** UPT Version Report Selection */
74 #define VMXNET3_VD_UVRS 0x8
76 /** Driver Shared Address Low */
77 #define VMXNET3_VD_DSAL 0x10
79 /** Driver Shared Address High */
80 #define VMXNET3_VD_DSAH 0x18
83 #define VMXNET3_VD_CMD 0x20
85 /** MAC Address Low */
86 #define VMXNET3_VD_MACL 0x28
88 /** MAC Address High */
89 #define VMXNET3_VD_MACH 0x30
91 /** Interrupt Cause Register */
92 #define VMXNET3_VD_ICR 0x38
94 /** Event Cause Register */
95 #define VMXNET3_VD_ECR 0x40
98 enum vmxnet3_command {
99 VMXNET3_CMD_FIRST_SET = 0xcafe0000,
100 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
101 VMXNET3_CMD_QUIESCE_DEV,
102 VMXNET3_CMD_RESET_DEV,
103 VMXNET3_CMD_UPDATE_RX_MODE,
104 VMXNET3_CMD_UPDATE_MAC_FILTERS,
105 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
106 VMXNET3_CMD_UPDATE_RSSIDT,
107 VMXNET3_CMD_UPDATE_IML,
108 VMXNET3_CMD_UPDATE_PMCFG,
109 VMXNET3_CMD_UPDATE_FEATURE,
110 VMXNET3_CMD_LOAD_PLUGIN,
112 VMXNET3_CMD_FIRST_GET = 0xf00d0000,
113 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
114 VMXNET3_CMD_GET_STATS,
115 VMXNET3_CMD_GET_LINK,
116 VMXNET3_CMD_GET_PERM_MAC_LO,
117 VMXNET3_CMD_GET_PERM_MAC_HI,
118 VMXNET3_CMD_GET_DID_LO,
119 VMXNET3_CMD_GET_DID_HI,
120 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
121 VMXNET3_CMD_GET_CONF_INTR
126 VMXNET3_ECR_RQERR = 0x00000001,
127 VMXNET3_ECR_TQERR = 0x00000002,
128 VMXNET3_ECR_LINK = 0x00000004,
129 VMXNET3_ECR_DIC = 0x00000008,
130 VMXNET3_ECR_DEBUG = 0x00000010,
133 /** Miscellaneous configuration descriptor */
134 struct vmxnet3_misc_config {
135 /** Driver version */
137 /** Guest information */
139 /** Version supported */
140 uint32_t version_support;
141 /** UPT version supported */
142 uint32_t upt_version_support;
143 /** UPT features supported */
144 uint64_t upt_features;
145 /** Driver-private data address */
146 uint64_t driver_data_address;
147 /** Queue descriptors data address */
148 uint64_t queue_desc_address;
149 /** Driver-private data length */
150 uint32_t driver_data_len;
151 /** Queue descriptors data length */
152 uint32_t queue_desc_len;
153 /** Maximum transmission unit */
155 /** Maximum number of RX scatter-gather */
156 uint16_t max_num_rx_sg;
157 /** Number of TX queues */
158 uint8_t num_tx_queues;
159 /** Number of RX queues */
160 uint8_t num_rx_queues;
162 uint32_t reserved0[4];
163 } __attribute__ (( packed ));
165 /** Driver version magic */
166 #define VMXNET3_VERSION_MAGIC 0x69505845
168 /** Interrupt configuration */
169 struct vmxnet3_interrupt_config {
172 uint8_t event_intr_index;
173 uint8_t moderation_level[VMXNET3_MAX_INTRS];
175 uint32_t reserved0[2];
176 } __attribute__ (( packed ));
178 /** Interrupt control - disable all interrupts */
179 #define VMXNET3_IC_DISABLE_ALL 0x1
181 /** Receive filter configuration */
182 struct vmxnet3_rx_filter_config {
183 /** Receive filter mode */
185 /** Multicast filter table length */
186 uint16_t multicast_len;
189 /** Multicast filter table address */
190 uint64_t multicast_address;
191 /** VLAN filter table (one bit per possible VLAN) */
192 uint8_t vlan_filter[512];
193 } __attribute__ (( packed ));
195 /** Receive filter mode */
196 enum vmxnet3_rx_filter_mode {
197 VMXNET3_RXM_UCAST = 0x01, /**< Unicast only */
198 VMXNET3_RXM_MCAST = 0x02, /**< Multicast passing the filters */
199 VMXNET3_RXM_BCAST = 0x04, /**< Broadcast only */
200 VMXNET3_RXM_ALL_MULTI = 0x08, /**< All multicast */
201 VMXNET3_RXM_PROMISC = 0x10, /**< Promiscuous */
204 /** Variable-length configuration descriptor */
205 struct vmxnet3_variable_config {
209 } __attribute__ (( packed ));
211 /** Driver shared area */
212 struct vmxnet3_shared {
213 /** Magic signature */
217 /** Miscellaneous configuration */
218 struct vmxnet3_misc_config misc;
219 /** Interrupt configuration */
220 struct vmxnet3_interrupt_config interrupt;
221 /** Receive filter configuration */
222 struct vmxnet3_rx_filter_config rx_filter;
223 /** RSS configuration */
224 struct vmxnet3_variable_config rss;
225 /** Pattern-matching configuration */
226 struct vmxnet3_variable_config pattern;
227 /** Plugin configuration */
228 struct vmxnet3_variable_config plugin;
229 /** Event notifications */
232 uint32_t reserved1[5];
233 } __attribute__ (( packed ));
235 /** Alignment of driver shared area */
236 #define VMXNET3_SHARED_ALIGN 8
238 /** Driver shared area magic */
239 #define VMXNET3_SHARED_MAGIC 0xbabefee1
241 /** Transmit descriptor */
242 struct vmxnet3_tx_desc {
247 } __attribute__ (( packed ));
249 /** Transmit generation flag */
250 #define VMXNET3_TXF_GEN 0x00004000UL
252 /** Transmit end-of-packet flag */
253 #define VMXNET3_TXF_EOP 0x000001000UL
255 /** Transmit completion request flag */
256 #define VMXNET3_TXF_CQ 0x000002000UL
258 /** Transmit completion descriptor */
259 struct vmxnet3_tx_comp {
260 /** Index of the end-of-packet descriptor */
263 uint32_t reserved0[2];
266 } __attribute__ (( packed ));
268 /** Transmit completion generation flag */
269 #define VMXNET3_TXCF_GEN 0x80000000UL
271 /** Transmit queue control */
272 struct vmxnet3_tx_queue_control {
273 uint32_t num_deferred;
276 } __attribute__ (( packed ));
278 /** Transmit queue configuration */
279 struct vmxnet3_tx_queue_config {
280 /** Descriptor ring address */
281 uint64_t desc_address;
282 /** Data ring address */
283 uint64_t immediate_address;
284 /** Completion ring address */
285 uint64_t comp_address;
286 /** Driver-private data address */
287 uint64_t driver_data_address;
290 /** Number of descriptors */
292 /** Number of data descriptors */
293 uint32_t num_immediate;
294 /** Number of completion descriptors */
296 /** Driver-private data length */
297 uint32_t driver_data_len;
298 /** Interrupt index */
302 } __attribute__ (( packed ));
304 /** Transmit queue statistics */
305 struct vmxnet3_tx_stats {
307 uint64_t reserved[10];
308 } __attribute__ (( packed ));
310 /** Receive descriptor */
311 struct vmxnet3_rx_desc {
318 } __attribute__ (( packed ));
320 /** Receive generation flag */
321 #define VMXNET3_RXF_GEN 0x80000000UL
323 /** Receive completion descriptor */
324 struct vmxnet3_rx_comp {
325 /** Descriptor index */
327 /** RSS hash value */
333 } __attribute__ (( packed ));
335 /** Receive completion generation flag */
336 #define VMXNET3_RXCF_GEN 0x80000000UL
338 /** Receive queue control */
339 struct vmxnet3_rx_queue_control {
341 uint8_t reserved0[7];
343 } __attribute__ (( packed ));
345 /** Receive queue configuration */
346 struct vmxnet3_rx_queue_config {
347 /** Descriptor ring addresses */
348 uint64_t desc_address[2];
349 /** Completion ring address */
350 uint64_t comp_address;
351 /** Driver-private data address */
352 uint64_t driver_data_address;
355 /** Number of descriptors */
356 uint32_t num_desc[2];
357 /** Number of completion descriptors */
359 /** Driver-private data length */
360 uint32_t driver_data_len;
361 /** Interrupt index */
365 } __attribute__ (( packed ));
367 /** Receive queue statistics */
368 struct vmxnet3_rx_stats {
370 uint64_t reserved[10];
371 } __attribute__ (( packed ));
374 struct vmxnet3_queue_status {
376 uint8_t reserved0[3];
378 } __attribute__ (( packed ));
380 /** Transmit queue descriptor */
381 struct vmxnet3_tx_queue {
382 struct vmxnet3_tx_queue_control ctrl;
383 struct vmxnet3_tx_queue_config cfg;
384 struct vmxnet3_queue_status status;
385 struct vmxnet3_tx_stats state;
386 uint8_t reserved[88];
387 } __attribute__ (( packed ));
389 /** Receive queue descriptor */
390 struct vmxnet3_rx_queue {
391 struct vmxnet3_rx_queue_control ctrl;
392 struct vmxnet3_rx_queue_config cfg;
393 struct vmxnet3_queue_status status;
394 struct vmxnet3_rx_stats stats;
395 uint8_t reserved[88];
396 } __attribute__ (( packed ));
399 * Queue descriptor set
401 * We use only a single TX and RX queue
403 struct vmxnet3_queues {
404 /** Transmit queue descriptor(s) */
405 struct vmxnet3_tx_queue tx;
406 /** Receive queue descriptor(s) */
407 struct vmxnet3_rx_queue rx;
408 } __attribute__ (( packed ));
410 /** Alignment of queue descriptor set */
411 #define VMXNET3_QUEUES_ALIGN 128
413 /** Alignment of rings */
414 #define VMXNET3_RING_ALIGN 512
416 /** Number of TX descriptors */
417 #define VMXNET3_NUM_TX_DESC 32
419 /** Number of TX completion descriptors */
420 #define VMXNET3_NUM_TX_COMP 32
422 /** Number of RX descriptors */
423 #define VMXNET3_NUM_RX_DESC 32
425 /** Number of RX completion descriptors */
426 #define VMXNET3_NUM_RX_COMP 32
431 * These are arranged in order of decreasing alignment, to allow for a
435 /** TX descriptor ring */
436 struct vmxnet3_tx_desc tx_desc[VMXNET3_NUM_TX_DESC];
437 /** TX completion ring */
438 struct vmxnet3_tx_comp tx_comp[VMXNET3_NUM_TX_COMP];
439 /** RX descriptor ring */
440 struct vmxnet3_rx_desc rx_desc[VMXNET3_NUM_RX_DESC];
441 /** RX completion ring */
442 struct vmxnet3_rx_comp rx_comp[VMXNET3_NUM_RX_COMP];
443 /** Queue descriptors */
444 struct vmxnet3_queues queues;
446 struct vmxnet3_shared shared;
447 } __attribute__ (( packed ));
449 /** DMA area alignment */
450 #define VMXNET3_DMA_ALIGN 512
452 /** Producer and consumer counters */
453 struct vmxnet3_counters {
454 /** Transmit producer counter */
455 unsigned int tx_prod;
456 /** Transmit completion consumer counter */
457 unsigned int tx_cons;
458 /** Receive producer counter */
459 unsigned int rx_prod;
460 /** Receive fill level */
461 unsigned int rx_fill;
462 /** Receive consumer counter */
463 unsigned int rx_cons;
468 /** "PT" register base address */
470 /** "VD" register base address */
474 struct vmxnet3_dma *dma;
475 /** Producer and consumer counters */
476 struct vmxnet3_counters count;
477 /** Transmit I/O buffers */
478 struct io_buffer *tx_iobuf[VMXNET3_NUM_TX_DESC];
479 /** Receive I/O buffers */
480 struct io_buffer *rx_iobuf[VMXNET3_NUM_RX_DESC];
483 /** vmxnet3 version that we support */
484 #define VMXNET3_VERSION_SELECT 1
486 /** UPT version that we support */
487 #define VMXNET3_UPT_VERSION_SELECT 1
490 #define VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ )
492 /** Receive ring maximum fill level */
493 #define VMXNET3_RX_FILL 8
495 /** Received packet alignment padding */
496 #define NET_IP_ALIGN 2
498 #endif /* _VMXNET3_H */