5 * Copyright (C) 2008 Michael Brown <mbrown@fensystems.co.uk>.
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of the
10 * License, or any later version.
12 * This program is distributed in the hope that it will be useful, but
13 * WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
15 * General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 * You can also choose to distribute this program under the terms of
23 * the Unmodified Binary Distribution Licence (as given in the file
24 * COPYING.UBDL), provided that you have satisfied its requirements.
27 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
32 * VMware vmxnet3 virtual NIC driver
38 /** Maximum number of TX queues */
39 #define VMXNET3_MAX_TX_QUEUES 8
41 /** Maximum number of RX queues */
42 #define VMXNET3_MAX_RX_QUEUES 16
44 /** Maximum number of interrupts */
45 #define VMXNET3_MAX_INTRS 25
47 /** Maximum packet size */
48 #define VMXNET3_MAX_PACKET_LEN 0x4000
50 /** "PT" PCI BAR address */
51 #define VMXNET3_PT_BAR PCI_BASE_ADDRESS_0
53 /** "PT" PCI BAR size */
54 #define VMXNET3_PT_LEN 0x1000
56 /** Interrupt Mask Register */
57 #define VMXNET3_PT_IMR 0x0
59 /** Transmit producer index */
60 #define VMXNET3_PT_TXPROD 0x600
62 /** Rx producer index for ring 1 */
63 #define VMXNET3_PT_RXPROD 0x800
65 /** Rx producer index for ring 2 */
66 #define VMXNET3_PT_RXPROD2 0xa00
68 /** "VD" PCI BAR address */
69 #define VMXNET3_VD_BAR PCI_BASE_ADDRESS_1
71 /** "VD" PCI BAR size */
72 #define VMXNET3_VD_LEN 0x1000
74 /** vmxnet3 Revision Report Selection */
75 #define VMXNET3_VD_VRRS 0x0
77 /** UPT Version Report Selection */
78 #define VMXNET3_VD_UVRS 0x8
80 /** Driver Shared Address Low */
81 #define VMXNET3_VD_DSAL 0x10
83 /** Driver Shared Address High */
84 #define VMXNET3_VD_DSAH 0x18
87 #define VMXNET3_VD_CMD 0x20
89 /** MAC Address Low */
90 #define VMXNET3_VD_MACL 0x28
92 /** MAC Address High */
93 #define VMXNET3_VD_MACH 0x30
95 /** Interrupt Cause Register */
96 #define VMXNET3_VD_ICR 0x38
98 /** Event Cause Register */
99 #define VMXNET3_VD_ECR 0x40
102 enum vmxnet3_command {
103 VMXNET3_CMD_FIRST_SET = 0xcafe0000,
104 VMXNET3_CMD_ACTIVATE_DEV = VMXNET3_CMD_FIRST_SET,
105 VMXNET3_CMD_QUIESCE_DEV,
106 VMXNET3_CMD_RESET_DEV,
107 VMXNET3_CMD_UPDATE_RX_MODE,
108 VMXNET3_CMD_UPDATE_MAC_FILTERS,
109 VMXNET3_CMD_UPDATE_VLAN_FILTERS,
110 VMXNET3_CMD_UPDATE_RSSIDT,
111 VMXNET3_CMD_UPDATE_IML,
112 VMXNET3_CMD_UPDATE_PMCFG,
113 VMXNET3_CMD_UPDATE_FEATURE,
114 VMXNET3_CMD_LOAD_PLUGIN,
116 VMXNET3_CMD_FIRST_GET = 0xf00d0000,
117 VMXNET3_CMD_GET_QUEUE_STATUS = VMXNET3_CMD_FIRST_GET,
118 VMXNET3_CMD_GET_STATS,
119 VMXNET3_CMD_GET_LINK,
120 VMXNET3_CMD_GET_PERM_MAC_LO,
121 VMXNET3_CMD_GET_PERM_MAC_HI,
122 VMXNET3_CMD_GET_DID_LO,
123 VMXNET3_CMD_GET_DID_HI,
124 VMXNET3_CMD_GET_DEV_EXTRA_INFO,
125 VMXNET3_CMD_GET_CONF_INTR
130 VMXNET3_ECR_RQERR = 0x00000001,
131 VMXNET3_ECR_TQERR = 0x00000002,
132 VMXNET3_ECR_LINK = 0x00000004,
133 VMXNET3_ECR_DIC = 0x00000008,
134 VMXNET3_ECR_DEBUG = 0x00000010,
137 /** Miscellaneous configuration descriptor */
138 struct vmxnet3_misc_config {
139 /** Driver version */
141 /** Guest information */
143 /** Version supported */
144 uint32_t version_support;
145 /** UPT version supported */
146 uint32_t upt_version_support;
147 /** UPT features supported */
148 uint64_t upt_features;
149 /** Driver-private data address */
150 uint64_t driver_data_address;
151 /** Queue descriptors data address */
152 uint64_t queue_desc_address;
153 /** Driver-private data length */
154 uint32_t driver_data_len;
155 /** Queue descriptors data length */
156 uint32_t queue_desc_len;
157 /** Maximum transmission unit */
159 /** Maximum number of RX scatter-gather */
160 uint16_t max_num_rx_sg;
161 /** Number of TX queues */
162 uint8_t num_tx_queues;
163 /** Number of RX queues */
164 uint8_t num_rx_queues;
166 uint32_t reserved0[4];
167 } __attribute__ (( packed ));
169 /** Driver version magic */
170 #define VMXNET3_VERSION_MAGIC 0x69505845
172 /** Interrupt configuration */
173 struct vmxnet3_interrupt_config {
176 uint8_t event_intr_index;
177 uint8_t moderation_level[VMXNET3_MAX_INTRS];
179 uint32_t reserved0[2];
180 } __attribute__ (( packed ));
182 /** Interrupt control - disable all interrupts */
183 #define VMXNET3_IC_DISABLE_ALL 0x1
185 /** Receive filter configuration */
186 struct vmxnet3_rx_filter_config {
187 /** Receive filter mode */
189 /** Multicast filter table length */
190 uint16_t multicast_len;
193 /** Multicast filter table address */
194 uint64_t multicast_address;
195 /** VLAN filter table (one bit per possible VLAN) */
196 uint8_t vlan_filter[512];
197 } __attribute__ (( packed ));
199 /** Receive filter mode */
200 enum vmxnet3_rx_filter_mode {
201 VMXNET3_RXM_UCAST = 0x01, /**< Unicast only */
202 VMXNET3_RXM_MCAST = 0x02, /**< Multicast passing the filters */
203 VMXNET3_RXM_BCAST = 0x04, /**< Broadcast only */
204 VMXNET3_RXM_ALL_MULTI = 0x08, /**< All multicast */
205 VMXNET3_RXM_PROMISC = 0x10, /**< Promiscuous */
208 /** Variable-length configuration descriptor */
209 struct vmxnet3_variable_config {
213 } __attribute__ (( packed ));
215 /** Driver shared area */
216 struct vmxnet3_shared {
217 /** Magic signature */
221 /** Miscellaneous configuration */
222 struct vmxnet3_misc_config misc;
223 /** Interrupt configuration */
224 struct vmxnet3_interrupt_config interrupt;
225 /** Receive filter configuration */
226 struct vmxnet3_rx_filter_config rx_filter;
227 /** RSS configuration */
228 struct vmxnet3_variable_config rss;
229 /** Pattern-matching configuration */
230 struct vmxnet3_variable_config pattern;
231 /** Plugin configuration */
232 struct vmxnet3_variable_config plugin;
233 /** Event notifications */
236 uint32_t reserved1[5];
237 } __attribute__ (( packed ));
239 /** Alignment of driver shared area */
240 #define VMXNET3_SHARED_ALIGN 8
242 /** Driver shared area magic */
243 #define VMXNET3_SHARED_MAGIC 0xbabefee1
245 /** Transmit descriptor */
246 struct vmxnet3_tx_desc {
251 } __attribute__ (( packed ));
253 /** Transmit generation flag */
254 #define VMXNET3_TXF_GEN 0x00004000UL
256 /** Transmit end-of-packet flag */
257 #define VMXNET3_TXF_EOP 0x000001000UL
259 /** Transmit completion request flag */
260 #define VMXNET3_TXF_CQ 0x000002000UL
262 /** Transmit completion descriptor */
263 struct vmxnet3_tx_comp {
264 /** Index of the end-of-packet descriptor */
267 uint32_t reserved0[2];
270 } __attribute__ (( packed ));
272 /** Transmit completion generation flag */
273 #define VMXNET3_TXCF_GEN 0x80000000UL
275 /** Transmit queue control */
276 struct vmxnet3_tx_queue_control {
277 uint32_t num_deferred;
280 } __attribute__ (( packed ));
282 /** Transmit queue configuration */
283 struct vmxnet3_tx_queue_config {
284 /** Descriptor ring address */
285 uint64_t desc_address;
286 /** Data ring address */
287 uint64_t immediate_address;
288 /** Completion ring address */
289 uint64_t comp_address;
290 /** Driver-private data address */
291 uint64_t driver_data_address;
294 /** Number of descriptors */
296 /** Number of data descriptors */
297 uint32_t num_immediate;
298 /** Number of completion descriptors */
300 /** Driver-private data length */
301 uint32_t driver_data_len;
302 /** Interrupt index */
306 } __attribute__ (( packed ));
308 /** Transmit queue statistics */
309 struct vmxnet3_tx_stats {
311 uint64_t reserved[10];
312 } __attribute__ (( packed ));
314 /** Receive descriptor */
315 struct vmxnet3_rx_desc {
322 } __attribute__ (( packed ));
324 /** Receive generation flag */
325 #define VMXNET3_RXF_GEN 0x80000000UL
327 /** Receive completion descriptor */
328 struct vmxnet3_rx_comp {
329 /** Descriptor index */
331 /** RSS hash value */
337 } __attribute__ (( packed ));
339 /** Receive completion generation flag */
340 #define VMXNET3_RXCF_GEN 0x80000000UL
342 /** Receive queue control */
343 struct vmxnet3_rx_queue_control {
345 uint8_t reserved0[7];
347 } __attribute__ (( packed ));
349 /** Receive queue configuration */
350 struct vmxnet3_rx_queue_config {
351 /** Descriptor ring addresses */
352 uint64_t desc_address[2];
353 /** Completion ring address */
354 uint64_t comp_address;
355 /** Driver-private data address */
356 uint64_t driver_data_address;
359 /** Number of descriptors */
360 uint32_t num_desc[2];
361 /** Number of completion descriptors */
363 /** Driver-private data length */
364 uint32_t driver_data_len;
365 /** Interrupt index */
369 } __attribute__ (( packed ));
371 /** Receive queue statistics */
372 struct vmxnet3_rx_stats {
374 uint64_t reserved[10];
375 } __attribute__ (( packed ));
378 struct vmxnet3_queue_status {
380 uint8_t reserved0[3];
382 } __attribute__ (( packed ));
384 /** Transmit queue descriptor */
385 struct vmxnet3_tx_queue {
386 struct vmxnet3_tx_queue_control ctrl;
387 struct vmxnet3_tx_queue_config cfg;
388 struct vmxnet3_queue_status status;
389 struct vmxnet3_tx_stats state;
390 uint8_t reserved[88];
391 } __attribute__ (( packed ));
393 /** Receive queue descriptor */
394 struct vmxnet3_rx_queue {
395 struct vmxnet3_rx_queue_control ctrl;
396 struct vmxnet3_rx_queue_config cfg;
397 struct vmxnet3_queue_status status;
398 struct vmxnet3_rx_stats stats;
399 uint8_t reserved[88];
400 } __attribute__ (( packed ));
403 * Queue descriptor set
405 * We use only a single TX and RX queue
407 struct vmxnet3_queues {
408 /** Transmit queue descriptor(s) */
409 struct vmxnet3_tx_queue tx;
410 /** Receive queue descriptor(s) */
411 struct vmxnet3_rx_queue rx;
412 } __attribute__ (( packed ));
414 /** Alignment of queue descriptor set */
415 #define VMXNET3_QUEUES_ALIGN 128
417 /** Alignment of rings */
418 #define VMXNET3_RING_ALIGN 512
420 /** Number of TX descriptors */
421 #define VMXNET3_NUM_TX_DESC 32
423 /** Number of TX completion descriptors */
424 #define VMXNET3_NUM_TX_COMP 32
426 /** Number of RX descriptors */
427 #define VMXNET3_NUM_RX_DESC 32
429 /** Number of RX completion descriptors */
430 #define VMXNET3_NUM_RX_COMP 32
435 * These are arranged in order of decreasing alignment, to allow for a
439 /** TX descriptor ring */
440 struct vmxnet3_tx_desc tx_desc[VMXNET3_NUM_TX_DESC];
441 /** TX completion ring */
442 struct vmxnet3_tx_comp tx_comp[VMXNET3_NUM_TX_COMP];
443 /** RX descriptor ring */
444 struct vmxnet3_rx_desc rx_desc[VMXNET3_NUM_RX_DESC];
445 /** RX completion ring */
446 struct vmxnet3_rx_comp rx_comp[VMXNET3_NUM_RX_COMP];
447 /** Queue descriptors */
448 struct vmxnet3_queues queues;
450 struct vmxnet3_shared shared;
451 } __attribute__ (( packed ));
453 /** DMA area alignment */
454 #define VMXNET3_DMA_ALIGN 512
456 /** Producer and consumer counters */
457 struct vmxnet3_counters {
458 /** Transmit producer counter */
459 unsigned int tx_prod;
460 /** Transmit completion consumer counter */
461 unsigned int tx_cons;
462 /** Receive producer counter */
463 unsigned int rx_prod;
464 /** Receive fill level */
465 unsigned int rx_fill;
466 /** Receive consumer counter */
467 unsigned int rx_cons;
472 /** "PT" register base address */
474 /** "VD" register base address */
478 struct vmxnet3_dma *dma;
479 /** Producer and consumer counters */
480 struct vmxnet3_counters count;
481 /** Transmit I/O buffers */
482 struct io_buffer *tx_iobuf[VMXNET3_NUM_TX_DESC];
483 /** Receive I/O buffers */
484 struct io_buffer *rx_iobuf[VMXNET3_NUM_RX_DESC];
487 /** vmxnet3 version that we support */
488 #define VMXNET3_VERSION_SELECT 1
490 /** UPT version that we support */
491 #define VMXNET3_UPT_VERSION_SELECT 1
494 #define VMXNET3_MTU ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* FCS */ )
496 /** Receive ring maximum fill level */
497 #define VMXNET3_RX_FILL 8
499 /** Received packet alignment padding */
500 #define NET_IP_ALIGN 2
502 #endif /* _VMXNET3_H */