1 /* -*- Mode:C; c-basic-offset:4; -*- */
4 Tulip and clone Etherboot Driver
6 By Marty Connor (mdc@etherboot.org)
7 Copyright (C) 2001 Entity Cyber, Inc.
9 This software may be used and distributed according to the terms
10 of the GNU Public License, incorporated herein by reference.
12 As of April 2001 this driver should support most tulip cards that
13 the Linux tulip driver supports because Donald Becker's Linux media
14 detection code is now included.
16 Based on Ken Yap's Tulip Etherboot Driver and Donald Becker's
17 Linux Tulip Driver. Supports N-Way speed auto-configuration on
18 MX98715, MX98715A and MX98725. Support inexpensive PCI 10/100 cards
19 based on the Macronix MX987x5 chip, such as the SOHOware Fast
20 model SFA110A, and the LinkSYS model LNE100TX. The NetGear
21 model FA310X, based on the LC82C168 chip is supported.
22 The TRENDnet TE100-PCIA NIC which uses a genuine Intel 21143-PD
23 chipset is supported. Also, Davicom DM9102's.
25 Documentation and source code used:
26 Source for Etherboot driver at
27 http://etherboot.sourceforge.net/
28 MX98715A Data Sheet and MX98715A Application Note
29 on http://www.macronix.com/ (PDF format files)
30 Source for Linux tulip driver at
31 http://cesdis.gsfc.nasa.gov/linux/drivers/tulip.html
33 Adapted by Ken Yap from
34 FreeBSD netboot DEC 21143 driver
38 Some code fragments were taken from verious places, Ken Yap's
39 etherboot, FreeBSD's if_de.c, and various Linux related files.
40 DEC's manuals for the 21143 and SROM format were very helpful.
41 The Linux de driver development page has a number of links to
42 useful related information. Have a look at:
43 ftp://cesdis.gsfc.nasa.gov/pub/linux/drivers/tulip-devel.html
46 FILE_LICENCE ( GPL_ANY );
48 /*********************************************************************/
49 /* Revision History */
50 /*********************************************************************/
53 08 Feb 2005 Ramesh Chander chhabaramesh at yahoo.co.in added table entries
54 for SGThomson STE10/100A
55 07 Sep 2003 timlegge Multicast Support Added
56 11 Apr 2001 mdc [patch to etherboot 4.7.24]
57 Major rewrite to include Linux tulip driver media detection
58 code. This driver should support a lot more cards now.
59 16 Jul 2000 mdc 0.75b11
60 Added support for ADMtek 0985 Centaur-P, a "Comet" tulip clone
61 which is used on the LinkSYS LNE100TX v4.x cards. We already
62 support LNE100TX v2.0 cards, which use a different controller.
64 Added test of status after receiving a packet from the card.
65 Also uncommented the tulip_disable routine. Stray packets
66 seemed to be causing problems.
68 29 Feb 2000 mdc 0.75b7
69 Increased reset delay to 3 seconds because Macronix cards seem to
70 need more reset time before card comes back to a usable state.
71 26 Feb 2000 mdc 0.75b6
72 Added a 1 second delay after initializing the transmitter because
73 some cards seem to need the time or they drop the first packet
75 23 Feb 2000 mdc 0.75b5
76 removed udelay code and used currticks() for more reliable delay
77 code in reset pause and sanity timeouts. Added function prototypes
78 and TX debugging code.
79 21 Feb 2000 mdc patch to Etherboot 4.4.3
80 Incorporated patches from Bob Edwards and Paul Mackerras of
81 Linuxcare's OZLabs to deal with inefficiencies in tulip_transmit
82 and udelay. We now wait for packet transmission to complete
84 04 Feb 2000 Robert.Edwards@anu.edu.au patch to Etherboot 4.4.2
85 patch to tulip.c that implements the automatic selection of the MII
86 interface on cards using the Intel/DEC 21143 reference design, in
87 particular, the TRENDnet TE100-PCIA NIC which uses a genuine Intel
89 11 Jan 2000 mdc 0.75b4
90 Added support for NetGear FA310TX card based on the LC82C168
91 chip. This should also support Lite-On LC82C168 boards.
92 Added simple MII support. Re-arranged code to better modularize
94 04 Dec 1999 mdc 0.75b3
95 Added preliminary support for LNE100TX PCI cards. Should work for
96 PNIC2 cards. No MII support, but single interface (RJ45) tulip
97 cards seem to not care.
98 03 Dec 1999 mdc 0.75b2
99 Renamed from mx987x5 to tulip, merged in original tulip init code
100 from tulip.c to support other tulip compatible cards.
101 02 Dec 1999 mdc 0.75b1
102 Released Beta MX987x5 Driver for code review and testing to netboot
103 and thinguin mailing lists.
107 /*********************************************************************/
109 /*********************************************************************/
111 #include "etherboot.h"
114 #include <ipxe/ethernet.h>
115 #include <ipxe/pci.h>
117 /* User settable parameters */
119 #define TX_TIME_OUT 2*TICKS_PER_SEC
121 /* helpful macros if on a big_endian machine for changing byte order.
122 not strictly needed on Intel */
123 #define get_unaligned(ptr) (*(ptr))
124 #define put_unaligned(val, ptr) ((void)( *(ptr) = (val) ))
125 #define get_u16(ptr) (*(u16 *)(ptr))
126 #define virt_to_le32desc(addr) virt_to_bus(addr)
128 #define TULIP_IOTYPE PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0
129 #define TULIP_SIZE 0x80
131 /* This is a mysterious value that can be written to CSR11 in the 21040 (only)
132 to support a pre-NWay full-duplex signaling mechanism using short frames.
133 No one knows what it should be, but if left at its default value some
134 10base2(!) packets trigger a full-duplex-request interrupt. */
135 #define FULL_DUPLEX_MAGIC 0x6969
137 static const int csr0 = 0x01A00000 | 0x8000;
139 /* The possible media types that can be set in options[] are: */
140 #define MEDIA_MASK 31
141 static const char * const medianame[32] = {
142 "10baseT", "10base2", "AUI", "100baseTx",
143 "10baseT-FDX", "100baseTx-FDX", "100baseT4", "100baseFx",
144 "100baseFx-FDX", "MII 10baseT", "MII 10baseT-FDX", "MII",
145 "10baseT(forced)", "MII 100baseTx", "MII 100baseTx-FDX", "MII 100baseT4",
146 "MII 100baseFx-HDX", "MII 100baseFx-FDX", "Home-PNA 1Mbps", "Invalid-19",
149 /* This much match tulip_tbl[]! Note 21142 == 21143. */
151 DC21040=0, DC21041=1, DC21140=2, DC21142=3, DC21143=3,
152 LC82C168, MX98713, MX98715, MX98725, AX88141, AX88140, PNIC2, COMET,
153 COMPEX9881, I21145, XIRCOM, SGThomson, /*Ramesh Chander*/
156 enum pci_id_flags_bits {
157 /* Set PCI command register bits before calling probe1(). */
158 PCI_USES_IO=1, PCI_USES_MEM=2, PCI_USES_MASTER=4,
159 /* Read and map the single following PCI BAR. */
160 PCI_ADDR0=0<<4, PCI_ADDR1=1<<4, PCI_ADDR2=2<<4, PCI_ADDR3=3<<4,
161 PCI_ADDR_64BITS=0x100, PCI_NO_ACPI_WAKE=0x200, PCI_NO_MIN_LATENCY=0x400,
162 PCI_UNUSED_IRQ=0x800,
168 u32 pci, pci_mask, subsystem, subsystem_mask;
169 u32 revision, revision_mask; /* Only 8 bits. */
171 enum pci_id_flags_bits pci_flags;
172 int io_size; /* Needed for I/O region check or ioremap(). */
173 int drv_flags; /* Driver use, intended as capability flags. */
176 static const struct pci_id_info pci_id_tbl[] = {
177 { "Digital DC21040 Tulip", { 0x00021011, 0xffffffff, 0, 0, 0, 0 },
178 TULIP_IOTYPE, 0x80, DC21040 },
179 { "Digital DC21041 Tulip", { 0x00141011, 0xffffffff, 0, 0, 0, 0 },
180 TULIP_IOTYPE, 0x80, DC21041 },
181 { "Digital DS21140A Tulip", { 0x00091011, 0xffffffff, 0,0, 0x20,0xf0 },
182 TULIP_IOTYPE, 0x80, DC21140 },
183 { "Digital DS21140 Tulip", { 0x00091011, 0xffffffff, 0, 0, 0, 0 },
184 TULIP_IOTYPE, 0x80, DC21140 },
185 { "Digital DS21143 Tulip", { 0x00191011, 0xffffffff, 0,0, 65,0xff },
186 TULIP_IOTYPE, TULIP_SIZE, DC21142 },
187 { "Digital DS21142 Tulip", { 0x00191011, 0xffffffff, 0, 0, 0, 0 },
188 TULIP_IOTYPE, TULIP_SIZE, DC21142 },
189 { "Kingston KNE110tx (PNIC)", { 0x000211AD, 0xffffffff, 0xf0022646, 0xffffffff, 0, 0 },
190 TULIP_IOTYPE, 256, LC82C168 },
191 { "Lite-On 82c168 PNIC", { 0x000211AD, 0xffffffff, 0, 0, 0, 0 },
192 TULIP_IOTYPE, 256, LC82C168 },
193 { "Macronix 98713 PMAC", { 0x051210d9, 0xffffffff, 0, 0, 0, 0 },
194 TULIP_IOTYPE, 256, MX98713 },
195 { "Macronix 98715 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
196 TULIP_IOTYPE, 256, MX98715 },
197 { "Macronix 98725 PMAC", { 0x053110d9, 0xffffffff, 0, 0, 0, 0 },
198 TULIP_IOTYPE, 256, MX98725 },
199 { "ASIX AX88141", { 0x1400125B, 0xffffffff, 0,0, 0x10, 0xf0 },
200 TULIP_IOTYPE, 128, AX88141 },
201 { "ASIX AX88140", { 0x1400125B, 0xffffffff, 0, 0, 0, 0 },
202 TULIP_IOTYPE, 128, AX88140 },
203 { "Lite-On LC82C115 PNIC-II", { 0xc11511AD, 0xffffffff, 0, 0, 0, 0 },
204 TULIP_IOTYPE, 256, PNIC2 },
205 { "ADMtek AN981 Comet", { 0x09811317, 0xffffffff, 0, 0, 0, 0 },
206 TULIP_IOTYPE, 256, COMET },
207 { "ADMTek AN983 Comet", { 0x12161113, 0xffffffff, 0, 0, 0, 0 },
208 TULIP_IOTYPE, 256, COMET },
209 { "ADMTek Comet AN983b", { 0x95111317, 0xffffffff, 0, 0, 0, 0 },
210 TULIP_IOTYPE, 256, COMET },
211 { "ADMtek Centaur-P", { 0x09851317, 0xffffffff, 0, 0, 0, 0 },
212 TULIP_IOTYPE, 256, COMET },
213 { "ADMtek Centaur-C", { 0x19851317, 0xffffffff, 0, 0, 0, 0 },
214 TULIP_IOTYPE, 256, COMET },
215 { "Compex RL100-TX", { 0x988111F6, 0xffffffff, 0, 0, 0, 0 },
216 TULIP_IOTYPE, 128, COMPEX9881 },
217 { "Intel 21145 Tulip", { 0x00398086, 0xffffffff, 0, 0, 0, 0 },
218 TULIP_IOTYPE, 128, I21145 },
219 { "Xircom Tulip clone", { 0x0003115d, 0xffffffff, 0, 0, 0, 0 },
220 TULIP_IOTYPE, 128, XIRCOM },
221 { "Davicom DM9102", { 0x91021282, 0xffffffff, 0, 0, 0, 0 },
222 TULIP_IOTYPE, 0x80, DC21140 },
223 { "Davicom DM9100", { 0x91001282, 0xffffffff, 0, 0, 0, 0 },
224 TULIP_IOTYPE, 0x80, DC21140 },
225 { "Macronix mxic-98715 (EN1217)", { 0x12171113, 0xffffffff, 0, 0, 0, 0 },
226 TULIP_IOTYPE, 256, MX98715 },
227 { "3Com 3cSOHO100B-TX (ADMtek Centuar)", { 0x930010b7, 0xffffffff, 0, 0, 0, 0 },
228 TULIP_IOTYPE, TULIP_SIZE, COMET },
229 { "SG Thomson STE10/100A", { 0x2774104a, 0xffffffff, 0, 0, 0, 0 },
230 TULIP_IOTYPE, 256, COMET }, /*Ramesh Chander*/
231 { NULL, { 0, 0, 0, 0, 0, 0 }, 0, 0, 0 },
235 HAS_MII=1, HAS_MEDIA_TABLE=2, CSR12_IN_SROM=4, ALWAYS_CHECK_MII=8,
236 HAS_PWRDWN=0x10, MC_HASH_ONLY=0x20, /* Hash-only multicast filter. */
237 HAS_PNICNWAY=0x80, HAS_NWAY=0x40, /* Uses internal NWay xcvr. */
238 HAS_INTR_MITIGATION=0x100, IS_ASIX=0x200, HAS_8023X=0x400,
241 /* Note: this table must match enum tulip_chips above. */
242 static struct tulip_chip_table {
246 { "Digital DC21040 Tulip", 0},
247 { "Digital DC21041 Tulip", HAS_MEDIA_TABLE | HAS_NWAY },
248 { "Digital DS21140 Tulip", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
249 { "Digital DS21143 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII
250 | HAS_PWRDWN | HAS_NWAY | HAS_INTR_MITIGATION },
251 { "Lite-On 82c168 PNIC", HAS_MII | HAS_PNICNWAY },
252 { "Macronix 98713 PMAC", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
253 { "Macronix 98715 PMAC", HAS_MEDIA_TABLE },
254 { "Macronix 98725 PMAC", HAS_MEDIA_TABLE },
255 { "ASIX AX88140", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM
256 | MC_HASH_ONLY | IS_ASIX },
257 { "ASIX AX88141", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM | MC_HASH_ONLY
259 { "Lite-On PNIC-II", HAS_MII | HAS_NWAY | HAS_8023X },
260 { "ADMtek Comet", HAS_MII | MC_HASH_ONLY },
261 { "Compex 9881 PMAC", HAS_MII | HAS_MEDIA_TABLE | CSR12_IN_SROM },
262 { "Intel DS21145 Tulip", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII
263 | HAS_PWRDWN | HAS_NWAY },
264 { "Xircom tulip work-alike", HAS_MII | HAS_MEDIA_TABLE | ALWAYS_CHECK_MII
265 | HAS_PWRDWN | HAS_NWAY },
266 { "SGThomson STE10/100A", HAS_MII | MC_HASH_ONLY }, /*Ramesh Chander*/
270 /* A full-duplex map for media types. */
272 MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8,
275 static const char media_cap[32] =
276 {0,0,0,16, 3,19,16,24, 27,4,7,5, 0,20,23,20, 20,31,0,0, };
277 static u8 t21040_csr13[] = {2,0x0C,8,4, 4,0,0,0, 0,0,0,0, 4,0,0,0};
279 /* 21041 transceiver register settings: 10-T, 10-2, AUI, 10-T, 10T-FD */
280 static u16 t21041_csr13[] = { 0xEF01, 0xEF09, 0xEF09, 0xEF01, 0xEF09, };
281 static u16 t21041_csr14[] = { 0xFFFF, 0xF7FD, 0xF7FD, 0x7F3F, 0x7F3D, };
282 static u16 t21041_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
285 static u16 t21142_csr13[] = { 0x0001, 0x0009, 0x0009, 0x0000, 0x0001, };
287 static u16 t21142_csr14[] = { 0xFFFF, 0x0705, 0x0705, 0x0000, 0x7F3D, };
289 static u16 t21142_csr15[] = { 0x0008, 0x0006, 0x000E, 0x0008, 0x0008, };
292 /* Offsets to the Command and Status Registers, "CSRs". All accesses
293 must be longword instructions and quadword aligned. */
295 CSR0=0, CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,
296 CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,
297 CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x80, CSR20=0xA0
300 /* The bits in the CSR5 status registers, mostly interrupt sources. */
302 TimerInt=0x800, TPLnkFail=0x1000, TPLnkPass=0x10,
303 NormalIntr=0x10000, AbnormalIntr=0x8000,
304 RxJabber=0x200, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,
305 TxFIFOUnderflow=0x20, TxJabber=0x08, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,
308 /* The configuration bits in CSR6. */
309 enum csr6_mode_bits {
310 TxOn=0x2000, RxOn=0x0002, FullDuplex=0x0200,
311 AcceptBroadcast=0x0100, AcceptAllMulticast=0x0080,
312 AcceptAllPhys=0x0040, AcceptRunt=0x0008,
316 enum desc_status_bits {
317 DescOwnded=0x80000000, RxDescFatalErr=0x8000, RxWholePkt=0x0300,
323 unsigned char *leafdata;
328 u8 leafcount, csr12dir; /* General purpose pin directions. */
329 unsigned has_mii:1, has_nonmii:1, has_reset:6;
330 u32 csr15dir, csr15val; /* 21143 NWay setting. */
331 struct medialeaf mleaf[0];
335 struct mediainfo *next;
341 /* EEPROM Address width definitions */
342 #define EEPROM_ADDRLEN 6
343 #define EEPROM_SIZE 128 /* 2 << EEPROM_ADDRLEN */
345 /* The EEPROM commands include the alway-set leading bit. */
346 #define EE_WRITE_CMD (5 << addr_len)
347 #define EE_READ_CMD (6 << addr_len)
348 #define EE_ERASE_CMD (7 << addr_len)
350 /* EEPROM_Ctrl bits. */
351 #define EE_SHIFT_CLK 0x02 /* EEPROM shift clock. */
352 #define EE_CS 0x01 /* EEPROM chip select. */
353 #define EE_DATA_WRITE 0x04 /* EEPROM chip data in. */
354 #define EE_WRITE_0 0x01
355 #define EE_WRITE_1 0x05
356 #define EE_DATA_READ 0x08 /* EEPROM chip data out. */
357 #define EE_ENB (0x4800 | EE_CS)
359 /* Delay between EEPROM clock transitions. Even at 33Mhz current PCI
360 implementations don't overrun the EEPROM clock. We add a bus
361 turn-around to insure that this remains true. */
362 #define eeprom_delay() inl(ee_addr)
364 /* Size of transmit and receive buffers */
367 /* Ring-wrap flag in length field, use for last ring entry.
368 0x01000000 means chain on buffer2 address,
369 0x02000000 means use the ring start address in CSR2/3.
370 Note: Some work-alike chips do not function correctly in chained mode.
371 The ASIX chip works only in chained mode.
372 Thus we indicate ring mode, but always write the 'next' field for
373 chained mode as well. */
374 #define DESC_RING_WRAP 0x02000000
376 /* transmit and receive descriptor format */
377 struct tulip_rx_desc {
380 u32 buffer1, buffer2;
383 struct tulip_tx_desc {
386 u32 buffer1, buffer2;
389 /*********************************************************************/
391 /*********************************************************************/
395 struct tulip_private {
397 int chip_id; /* index into tulip_tbl[] */
398 int pci_id_idx; /* index into pci_id_tbl[] */
401 unsigned short vendor_id; /* PCI card vendor code */
402 unsigned short dev_id; /* PCI card device code */
403 unsigned char ehdr[ETH_HLEN]; /* buffer for ethernet header */
404 const char *nic_name;
405 unsigned int csr0, csr6; /* Current CSR0, CSR6 settings. */
406 unsigned int if_port;
407 unsigned int full_duplex; /* Full-duplex operation requested. */
408 unsigned int full_duplex_lock;
409 unsigned int medialock; /* Do not sense media type. */
410 unsigned int mediasense; /* Media sensing in progress. */
411 unsigned int nway, nwayset; /* 21143 internal NWay. */
412 unsigned int default_port;
413 unsigned char eeprom[EEPROM_SIZE]; /* Serial EEPROM contents. */
414 u8 media_table_storage[(sizeof(struct mediatable) + 32*sizeof(struct medialeaf))];
415 u16 sym_advertise, mii_advertise; /* NWay to-advertise. */
416 struct mediatable *mtable;
417 u16 lpar; /* 21143 Link partner ability. */
418 u16 advertising[4]; /* MII advertise, from SROM table. */
419 signed char phys[4], mii_cnt; /* MII device addresses. */
420 int cur_index; /* Current media index. */
424 /* Note: transmit and receive buffers must be longword aligned and
425 longword divisable */
427 #define TX_RING_SIZE 2
428 #define RX_RING_SIZE 4
430 struct tulip_tx_desc tx_ring[TX_RING_SIZE];
431 unsigned char txb[BUFLEN];
432 struct tulip_rx_desc rx_ring[RX_RING_SIZE];
433 unsigned char rxb[RX_RING_SIZE * BUFLEN];
434 struct tulip_private tpx;
435 } tulip_bss __shared __attribute__ ((aligned(4)));
436 #define tx_ring tulip_bss.tx_ring
437 #define txb tulip_bss.txb
438 #define rx_ring tulip_bss.rx_ring
439 #define rxb tulip_bss.rxb
441 static struct tulip_private *tp;
443 /* Known cards that have old-style EEPROMs.
444 Writing this table is described at
445 http://cesdis.gsfc.nasa.gov/linux/drivers/tulip-drivers/tulip-media.html */
446 static struct fixups {
448 unsigned char addr0, addr1, addr2;
449 u16 newtable[32]; /* Max length below. */
450 } eeprom_fixups[] = {
451 {"Asante", 0, 0, 0x94, {0x1e00, 0x0000, 0x0800, 0x0100, 0x018c,
452 0x0000, 0x0000, 0xe078, 0x0001, 0x0050, 0x0018 }},
453 {"SMC9332DST", 0, 0, 0xC0, { 0x1e00, 0x0000, 0x0800, 0x041f,
454 0x0000, 0x009E, /* 10baseT */
455 0x0004, 0x009E, /* 10baseT-FD */
456 0x0903, 0x006D, /* 100baseTx */
457 0x0905, 0x006D, /* 100baseTx-FD */ }},
458 {"Cogent EM100", 0, 0, 0x92, { 0x1e00, 0x0000, 0x0800, 0x063f,
459 0x0107, 0x8021, /* 100baseFx */
460 0x0108, 0x8021, /* 100baseFx-FD */
461 0x0100, 0x009E, /* 10baseT */
462 0x0104, 0x009E, /* 10baseT-FD */
463 0x0103, 0x006D, /* 100baseTx */
464 0x0105, 0x006D, /* 100baseTx-FD */ }},
465 {"Maxtech NX-110", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x0513,
466 0x1001, 0x009E, /* 10base2, CSR12 0x10*/
467 0x0000, 0x009E, /* 10baseT */
468 0x0004, 0x009E, /* 10baseT-FD */
469 0x0303, 0x006D, /* 100baseTx, CSR12 0x03 */
470 0x0305, 0x006D, /* 100baseTx-FD CSR12 0x03 */}},
471 {"Accton EN1207", 0, 0, 0xE8, { 0x1e00, 0x0000, 0x0800, 0x051F,
472 0x1B01, 0x0000, /* 10base2, CSR12 0x1B */
473 0x0B00, 0x009E, /* 10baseT, CSR12 0x0B */
474 0x0B04, 0x009E, /* 10baseT-FD,CSR12 0x0B */
475 0x1B03, 0x006D, /* 100baseTx, CSR12 0x1B */
476 0x1B05, 0x006D, /* 100baseTx-FD CSR12 0x1B */
478 {NULL, 0, 0, 0, {}}};
480 static const char * block_name[] = {"21140 non-MII", "21140 MII PHY",
481 "21142 Serial PHY", "21142 MII PHY", "21143 SYM PHY", "21143 reset method"};
484 /*********************************************************************/
485 /* Function Prototypes */
486 /*********************************************************************/
487 static int mdio_read(struct nic *nic, int phy_id, int location);
488 static void mdio_write(struct nic *nic, int phy_id, int location, int value);
489 static int read_eeprom(unsigned long ioaddr, int location, int addr_len);
490 static void parse_eeprom(struct nic *nic);
491 static int tulip_probe(struct nic *nic,struct pci_device *pci);
492 static void tulip_init_ring(struct nic *nic);
493 static void tulip_reset(struct nic *nic);
494 static void tulip_transmit(struct nic *nic, const char *d, unsigned int t,
495 unsigned int s, const char *p);
496 static int tulip_poll(struct nic *nic, int retrieve);
497 static void tulip_disable(struct nic *nic);
498 static void nway_start(struct nic *nic);
499 static void pnic_do_nway(struct nic *nic);
500 static void select_media(struct nic *nic, int startup);
501 static void init_media(struct nic *nic);
502 static void start_link(struct nic *nic);
503 static int tulip_check_duplex(struct nic *nic);
505 static void tulip_wait(unsigned int nticks);
508 /*********************************************************************/
509 /* Utility Routines */
510 /*********************************************************************/
512 static void whereami (const char *str)
518 static void tulip_wait(unsigned int nticks)
520 unsigned int to = currticks() + nticks;
521 while (currticks() < to)
526 /*********************************************************************/
527 /* Media Descriptor Code */
528 /*********************************************************************/
530 /* MII transceiver control section.
531 Read and write the MII registers using software-generated serial
532 MDIO protocol. See the MII specifications or DP83840A data sheet
535 /* The maximum data clock rate is 2.5 Mhz. The minimum timing is usually
536 met by back-to-back PCI I/O cycles, but we insert a delay to avoid
537 "overclocking" issues or future 66Mhz PCI. */
538 #define mdio_delay() inl(mdio_addr)
540 /* Read and write the MII registers using software-generated serial
541 MDIO protocol. It is just different enough from the EEPROM protocol
542 to not share code. The maxium data clock rate is 2.5 Mhz. */
543 #define MDIO_SHIFT_CLK 0x10000
544 #define MDIO_DATA_WRITE0 0x00000
545 #define MDIO_DATA_WRITE1 0x20000
546 #define MDIO_ENB 0x00000 /* Ignore the 0x02000 databook setting. */
547 #define MDIO_ENB_IN 0x40000
548 #define MDIO_DATA_READ 0x80000
550 /* MII transceiver control section.
551 Read and write the MII registers using software-generated serial
552 MDIO protocol. See the MII specifications or DP83840A data sheet
555 int mdio_read(struct nic *nic __unused, int phy_id, int location)
558 int read_cmd = (0xf6 << 10) | (phy_id << 5) | location;
560 long mdio_addr = ioaddr + CSR9;
562 whereami("mdio_read\n");
564 if (tp->chip_id == LC82C168) {
566 outl(0x60020000 + (phy_id<<23) + (location<<18), ioaddr + 0xA0);
570 if ( ! ((retval = inl(ioaddr + 0xA0)) & 0x80000000))
571 return retval & 0xffff;
575 if (tp->chip_id == COMET) {
578 return inl(ioaddr + 0xB4 + (location<<2));
579 else if (location == 17)
580 return inl(ioaddr + 0xD0);
581 else if (location >= 29 && location <= 31)
582 return inl(ioaddr + 0xD4 + ((location-29)<<2));
587 /* Establish sync by sending at least 32 logic ones. */
588 for (i = 32; i >= 0; i--) {
589 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
591 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
594 /* Shift the read command bits out. */
595 for (i = 15; i >= 0; i--) {
596 int dataval = (read_cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
598 outl(MDIO_ENB | dataval, mdio_addr);
600 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
603 /* Read the two transition, 16 data, and wire-idle bits. */
604 for (i = 19; i > 0; i--) {
605 outl(MDIO_ENB_IN, mdio_addr);
607 retval = (retval << 1) | ((inl(mdio_addr) & MDIO_DATA_READ) ? 1 : 0);
608 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
611 return (retval>>1) & 0xffff;
614 void mdio_write(struct nic *nic __unused, int phy_id, int location, int value)
617 int cmd = (0x5002 << 16) | (phy_id << 23) | (location<<18) | value;
618 long mdio_addr = ioaddr + CSR9;
620 whereami("mdio_write\n");
622 if (tp->chip_id == LC82C168) {
624 outl(cmd, ioaddr + 0xA0);
626 if ( ! (inl(ioaddr + 0xA0) & 0x80000000))
632 if (tp->chip_id == COMET) {
636 outl(value, ioaddr + 0xB4 + (location<<2));
637 else if (location == 17)
638 outl(value, ioaddr + 0xD0);
639 else if (location >= 29 && location <= 31)
640 outl(value, ioaddr + 0xD4 + ((location-29)<<2));
644 /* Establish sync by sending 32 logic ones. */
645 for (i = 32; i >= 0; i--) {
646 outl(MDIO_ENB | MDIO_DATA_WRITE1, mdio_addr);
648 outl(MDIO_ENB | MDIO_DATA_WRITE1 | MDIO_SHIFT_CLK, mdio_addr);
651 /* Shift the command bits out. */
652 for (i = 31; i >= 0; i--) {
653 int dataval = (cmd & (1 << i)) ? MDIO_DATA_WRITE1 : 0;
654 outl(MDIO_ENB | dataval, mdio_addr);
656 outl(MDIO_ENB | dataval | MDIO_SHIFT_CLK, mdio_addr);
659 /* Clear out extra bits. */
660 for (i = 2; i > 0; i--) {
661 outl(MDIO_ENB_IN, mdio_addr);
663 outl(MDIO_ENB_IN | MDIO_SHIFT_CLK, mdio_addr);
669 /*********************************************************************/
670 /* EEPROM Reading Code */
671 /*********************************************************************/
672 /* EEPROM routines adapted from the Linux Tulip Code */
673 /* Reading a serial EEPROM is a "bit" grungy, but we work our way
676 static int read_eeprom(unsigned long ioaddr, int location, int addr_len)
679 unsigned short retval = 0;
680 long ee_addr = ioaddr + CSR9;
681 int read_cmd = location | EE_READ_CMD;
683 whereami("read_eeprom\n");
685 outl(EE_ENB & ~EE_CS, ee_addr);
686 outl(EE_ENB, ee_addr);
688 /* Shift the read command bits out. */
689 for (i = 4 + addr_len; i >= 0; i--) {
690 short dataval = (read_cmd & (1 << i)) ? EE_DATA_WRITE : 0;
691 outl(EE_ENB | dataval, ee_addr);
693 outl(EE_ENB | dataval | EE_SHIFT_CLK, ee_addr);
696 outl(EE_ENB, ee_addr);
698 for (i = 16; i > 0; i--) {
699 outl(EE_ENB | EE_SHIFT_CLK, ee_addr);
701 retval = (retval << 1) | ((inl(ee_addr) & EE_DATA_READ) ? 1 : 0);
702 outl(EE_ENB, ee_addr);
706 /* Terminate the EEPROM access. */
707 outl(EE_ENB & ~EE_CS, ee_addr);
712 /*********************************************************************/
713 /* EEPROM Parsing Code */
714 /*********************************************************************/
715 static void parse_eeprom(struct nic *nic)
717 unsigned char *p, *ee_data = tp->eeprom;
718 int new_advertise = 0;
721 whereami("parse_eeprom\n");
724 /* Detect an old-style (SA only) EEPROM layout:
725 memcmp(ee_data, ee_data+16, 8). */
726 for (i = 0; i < 8; i ++)
727 if (ee_data[i] != ee_data[16+i])
730 /* Do a fix-up based on the vendor half of the station address. */
731 for (i = 0; eeprom_fixups[i].name; i++) {
732 if (nic->node_addr[0] == eeprom_fixups[i].addr0
733 && nic->node_addr[1] == eeprom_fixups[i].addr1
734 && nic->node_addr[2] == eeprom_fixups[i].addr2) {
735 if (nic->node_addr[2] == 0xE8 && ee_data[0x1a] == 0x55)
736 i++; /* An Accton EN1207, not an outlaw Maxtech. */
737 memcpy(ee_data + 26, eeprom_fixups[i].newtable,
738 sizeof(eeprom_fixups[i].newtable));
739 DBG("%s: Old format EEPROM on '%s' board.\n%s: Using substitute media control info.\n",
740 tp->nic_name, eeprom_fixups[i].name, tp->nic_name);
744 if (eeprom_fixups[i].name == NULL) { /* No fixup found. */
745 DBG("%s: Old style EEPROM with no media selection information.\n",
751 if (ee_data[19] > 1) {
752 DBG("%s: Multiport cards (%d ports) may not work correctly.\n",
753 tp->nic_name, ee_data[19]);
756 p = (void *)ee_data + ee_data[27];
758 if (ee_data[27] == 0) { /* No valid media table. */
759 DBG2("%s: No Valid Media Table. ee_data[27] = %hhX\n",
760 tp->nic_name, ee_data[27]);
761 } else if (tp->chip_id == DC21041) {
762 int media = get_u16(p);
766 DBG("%s: 21041 Media table, default media %hX (%s).\n",
768 media & 0x0800 ? "Autosense" : medianame[media & 15]);
769 for (i = 0; i < count; i++) {
770 unsigned char media_block = *p++;
771 int media_code = media_block & MEDIA_MASK;
772 if (media_block & 0x40)
775 case 0: new_advertise |= 0x0020; break;
776 case 4: new_advertise |= 0x0040; break;
778 DBG("%s: 21041 media #%d, %s.\n",
779 tp->nic_name, media_code, medianame[media_code]);
782 unsigned char csr12dir = 0;
784 struct mediatable *mtable;
785 u16 media = get_u16(p);
788 if (tp->flags & CSR12_IN_SROM)
792 tp->mtable = mtable = (struct mediatable *)&tp->media_table_storage[0];
794 mtable->defaultmedia = media;
795 mtable->leafcount = count;
796 mtable->csr12dir = csr12dir;
797 mtable->has_nonmii = mtable->has_mii = mtable->has_reset = 0;
798 mtable->csr15dir = mtable->csr15val = 0;
800 DBG("%s: EEPROM default media type %s.\n", tp->nic_name,
801 media & 0x0800 ? "Autosense" : medianame[media & MEDIA_MASK]);
803 for (i = 0; i < count; i++) {
804 struct medialeaf *leaf = &mtable->mleaf[i];
806 if ((p[0] & 0x80) == 0) { /* 21140 Compact block. */
808 leaf->media = p[0] & 0x3f;
810 if ((p[2] & 0x61) == 0x01) /* Bogus, but Znyx boards do it. */
814 switch(leaf->type = p[1]) {
816 mtable->has_reset = i;
817 leaf->media = p[2] & 0x0f;
824 if ((p[2] & 0x3f) == 0) {
825 u32 base15 = (p[2] & 0x40) ? get_u16(p + 7) : 0x0008;
826 u16 *p1 = (u16 *)(p + (p[2] & 0x40 ? 9 : 3));
827 mtable->csr15dir = (get_unaligned(p1 + 0)<<16) + base15;
828 mtable->csr15val = (get_unaligned(p1 + 1)<<16) + base15;
832 mtable->has_nonmii = 1;
833 leaf->media = p[2] & MEDIA_MASK;
834 switch (leaf->media) {
835 case 0: new_advertise |= 0x0020; break;
836 case 4: new_advertise |= 0x0040; break;
837 case 3: new_advertise |= 0x0080; break;
838 case 5: new_advertise |= 0x0100; break;
839 case 6: new_advertise |= 0x0200; break;
845 leaf->leafdata = p + 2;
846 p += (p[0] & 0x3f) + 1;
848 if (leaf->media == 11) {
849 unsigned char *bp = leaf->leafdata;
850 DBG2("%s: MII interface PHY %d, setup/reset sequences %d/%d long, capabilities %hhX %hhX.\n",
851 tp->nic_name, bp[0], bp[1], bp[2 + bp[1]*2],
852 bp[5 + bp[2 + bp[1]*2]*2], bp[4 + bp[2 + bp[1]*2]*2]);
854 DBG("%s: Index #%d - Media %s (#%d) described "
855 "by a %s (%d) block.\n",
856 tp->nic_name, i, medianame[leaf->media], leaf->media,
857 leaf->type < 6 ? block_name[leaf->type] : "UNKNOWN",
861 tp->sym_advertise = new_advertise;
866 /*********************************************************************/
867 /* tulip_init_ring - setup the tx and rx descriptors */
868 /*********************************************************************/
869 static void tulip_init_ring(struct nic *nic __unused)
873 whereami("tulip_init_ring\n");
877 for (i = 0; i < RX_RING_SIZE; i++) {
878 rx_ring[i].status = cpu_to_le32(0x80000000);
879 rx_ring[i].length = cpu_to_le32(BUFLEN);
880 rx_ring[i].buffer1 = virt_to_le32desc(&rxb[i * BUFLEN]);
881 rx_ring[i].buffer2 = virt_to_le32desc(&rx_ring[i+1]);
883 /* Mark the last entry as wrapping the ring. */
884 rx_ring[i-1].length = cpu_to_le32(DESC_RING_WRAP | BUFLEN);
885 rx_ring[i-1].buffer2 = virt_to_le32desc(&rx_ring[0]);
887 /* We only use 1 transmit buffer, but we use 2 descriptors so
888 transmit engines have somewhere to point to if they feel the need */
890 tx_ring[0].status = 0x00000000;
891 tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]);
892 tx_ring[0].buffer2 = virt_to_le32desc(&tx_ring[1]);
894 /* this descriptor should never get used, since it will never be owned
895 by the machine (status will always == 0) */
896 tx_ring[1].status = 0x00000000;
897 tx_ring[1].buffer1 = virt_to_le32desc(&txb[0]);
898 tx_ring[1].buffer2 = virt_to_le32desc(&tx_ring[0]);
900 /* Mark the last entry as wrapping the ring, though this should never happen */
901 tx_ring[1].length = cpu_to_le32(DESC_RING_WRAP | BUFLEN);
905 static void set_rx_mode(struct nic *nic __unused) {
906 int csr6 = inl(ioaddr + CSR6) & ~0x00D5;
911 tp->csr6 |= AcceptAllMulticast;
912 csr6 |= AcceptAllMulticast;
914 outl(csr6, ioaddr + CSR6);
920 /*********************************************************************/
921 /* eth_reset - Reset adapter */
922 /*********************************************************************/
923 static void tulip_reset(struct nic *nic)
928 whereami("tulip_reset\n");
931 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
933 /* On some chip revs we must set the MII/SYM port before the reset!? */
934 if (tp->mii_cnt || (tp->mtable && tp->mtable->has_mii)) {
935 outl(0x814C0000, ioaddr + CSR6);
938 /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */
939 outl(0x00000001, ioaddr + CSR0);
942 /* turn off reset and set cache align=16lword, burst=unlimit */
943 outl(tp->csr0, ioaddr + CSR0);
945 /* Wait the specified 50 PCI cycles after a reset */
948 /* set up transmit and receive descriptors */
949 tulip_init_ring(nic);
951 if (tp->chip_id == PNIC2) {
952 u32 addr_high = (nic->node_addr[1]<<8) + (nic->node_addr[0]<<0);
953 /* This address setting does not appear to impact chip operation?? */
954 outl((nic->node_addr[5]<<8) + nic->node_addr[4] +
955 (nic->node_addr[3]<<24) + (nic->node_addr[2]<<16),
957 outl(addr_high + (addr_high<<16), ioaddr + 0xB8);
960 /* MC_HASH_ONLY boards don't support setup packets */
961 if (tp->flags & MC_HASH_ONLY) {
962 u32 addr_low = cpu_to_le32(get_unaligned((u32 *)nic->node_addr));
963 u32 addr_high = cpu_to_le32(get_unaligned((u16 *)(nic->node_addr+4)));
965 /* clear multicast hash filters and setup MAC address filters */
966 if (tp->flags & IS_ASIX) {
967 outl(0, ioaddr + CSR13);
968 outl(addr_low, ioaddr + CSR14);
969 outl(1, ioaddr + CSR13);
970 outl(addr_high, ioaddr + CSR14);
971 outl(2, ioaddr + CSR13);
972 outl(0, ioaddr + CSR14);
973 outl(3, ioaddr + CSR13);
974 outl(0, ioaddr + CSR14);
975 } else if (tp->chip_id == COMET) {
976 outl(addr_low, ioaddr + 0xA4);
977 outl(addr_high, ioaddr + 0xA8);
978 outl(0, ioaddr + 0xAC);
979 outl(0, ioaddr + 0xB0);
982 /* for other boards we send a setup packet to initialize
984 u32 tx_flags = 0x08000000 | 192;
986 /* construct perfect filter frame with mac address as first match
987 and broadcast address for all others */
988 for (i=0; i<192; i++)
990 txb[0] = nic->node_addr[0];
991 txb[1] = nic->node_addr[1];
992 txb[4] = nic->node_addr[2];
993 txb[5] = nic->node_addr[3];
994 txb[8] = nic->node_addr[4];
995 txb[9] = nic->node_addr[5];
997 tx_ring[0].length = cpu_to_le32(tx_flags);
998 tx_ring[0].buffer1 = virt_to_le32desc(&txb[0]);
999 tx_ring[0].status = cpu_to_le32(0x80000000);
1002 /* Point to rx and tx descriptors */
1003 outl(virt_to_le32desc(&rx_ring[0]), ioaddr + CSR3);
1004 outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4);
1008 /* set the chip's operating mode (but don't turn on xmit and recv yet) */
1009 outl((tp->csr6 & ~0x00002002), ioaddr + CSR6);
1011 /* send setup packet for cards that support it */
1012 if (!(tp->flags & MC_HASH_ONLY)) {
1013 /* enable transmit wait for completion */
1014 outl(tp->csr6 | 0x00002000, ioaddr + CSR6);
1015 /* immediate transmit demand */
1016 outl(0, ioaddr + CSR1);
1018 to = currticks() + TX_TIME_OUT;
1019 while ((tx_ring[0].status & 0x80000000) && (currticks() < to))
1022 if (currticks() >= to) {
1023 DBG ("%s: TX Setup Timeout.\n", tp->nic_name);
1027 if (tp->chip_id == LC82C168)
1028 tulip_check_duplex(nic);
1032 /* enable transmit and receive */
1033 outl(tp->csr6 | 0x00002002, ioaddr + CSR6);
1037 /*********************************************************************/
1038 /* eth_transmit - Transmit a frame */
1039 /*********************************************************************/
1040 static void tulip_transmit(struct nic *nic, const char *d, unsigned int t,
1041 unsigned int s, const char *p)
1045 u32 csr6 = inl(ioaddr + CSR6);
1047 whereami("tulip_transmit\n");
1050 outl(csr6 & ~0x00002000, ioaddr + CSR6);
1052 memcpy(txb, d, ETH_ALEN);
1053 memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
1054 nstype = htons((u16) t);
1055 memcpy(txb + 2 * ETH_ALEN, (u8 *)&nstype, 2);
1056 memcpy(txb + ETH_HLEN, p, s);
1061 /* pad to minimum packet size */
1062 while (s < ETH_ZLEN)
1065 DBG2("%s: sending %d bytes ethtype %hX\n", tp->nic_name, s, t);
1067 /* setup the transmit descriptor */
1068 /* 0x60000000 = no interrupt on completion */
1069 tx_ring[0].length = cpu_to_le32(0x60000000 | s);
1070 tx_ring[0].status = cpu_to_le32(0x80000000);
1072 /* Point to transmit descriptor */
1073 outl(virt_to_le32desc(&tx_ring[0]), ioaddr + CSR4);
1076 outl(csr6 | 0x00002000, ioaddr + CSR6);
1077 /* immediate transmit demand */
1078 outl(0, ioaddr + CSR1);
1080 to = currticks() + TX_TIME_OUT;
1081 while ((tx_ring[0].status & 0x80000000) && (currticks() < to))
1084 if (currticks() >= to) {
1085 DBG ("TX Timeout!\n");
1089 outl(csr6 & ~0x00002000, ioaddr + CSR6);
1092 /*********************************************************************/
1093 /* eth_poll - Wait for a frame */
1094 /*********************************************************************/
1095 static int tulip_poll(struct nic *nic, int retrieve)
1098 whereami("tulip_poll\n");
1100 /* no packet waiting. packet still owned by NIC */
1101 if (rx_ring[tp->cur_rx].status & 0x80000000)
1104 if ( ! retrieve ) return 1;
1106 whereami("tulip_poll got one\n");
1108 nic->packetlen = (rx_ring[tp->cur_rx].status & 0x3FFF0000) >> 16;
1110 /* if we get a corrupted packet. throw it away and move on */
1111 if (rx_ring[tp->cur_rx].status & 0x00008000) {
1112 /* return the descriptor and buffer to receive ring */
1113 rx_ring[tp->cur_rx].status = 0x80000000;
1114 tp->cur_rx = (tp->cur_rx + 1) % RX_RING_SIZE;
1118 /* copy packet to working buffer */
1119 memcpy(nic->packet, rxb + tp->cur_rx * BUFLEN, nic->packetlen);
1121 /* return the descriptor and buffer to receive ring */
1122 rx_ring[tp->cur_rx].status = 0x80000000;
1123 tp->cur_rx = (tp->cur_rx + 1) % RX_RING_SIZE;
1128 /*********************************************************************/
1129 /* eth_disable - Disable the interface */
1130 /*********************************************************************/
1131 static void tulip_disable ( struct nic *nic ) {
1133 whereami("tulip_disable\n");
1137 /* disable interrupts */
1138 outl(0x00000000, ioaddr + CSR7);
1140 /* Stop the chip's Tx and Rx processes. */
1141 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
1143 /* Clear the missed-packet counter. */
1147 /*********************************************************************/
1148 /*IRQ - Enable, Disable, or Force interrupts */
1149 /*********************************************************************/
1150 static void tulip_irq(struct nic *nic __unused, irq_action_t action __unused)
1162 static struct nic_operations tulip_operations = {
1163 .connect = dummy_connect,
1165 .transmit = tulip_transmit,
1170 /*********************************************************************/
1171 /* eth_probe - Look for an adapter */
1172 /*********************************************************************/
1173 static int tulip_probe ( struct nic *nic, struct pci_device *pci ) {
1177 u8 ee_data[EEPROM_SIZE];
1180 static unsigned char last_phys_addr[ETH_ALEN] = {0x00, 'L', 'i', 'n', 'u', 'x'};
1182 if (pci->ioaddr == 0)
1185 ioaddr = pci->ioaddr;
1186 nic->ioaddr = pci->ioaddr & ~3;
1189 /* point to private storage */
1190 tp = &tulip_bss.tpx;
1192 tp->vendor_id = pci->vendor;
1193 tp->dev_id = pci->device;
1194 tp->nic_name = pci->id->name;
1197 tp->default_port = 0;
1199 adjust_pci_device(pci);
1201 /* disable interrupts */
1202 outl(0x00000000, ioaddr + CSR7);
1204 /* Stop the chip's Tx and Rx processes. */
1205 outl(inl(ioaddr + CSR6) & ~0x00002002, ioaddr + CSR6);
1207 /* Clear the missed-packet counter. */
1210 DBG("\n"); /* so we start on a fresh line */
1211 whereami("tulip_probe\n");
1213 DBG2 ("%s: Looking for Tulip Chip: Vendor=%hX Device=%hX\n", tp->nic_name,
1214 tp->vendor_id, tp->dev_id);
1216 /* Figure out which chip we're dealing with */
1220 while (pci_id_tbl[i].name) {
1221 if ( (((u32) tp->dev_id << 16) | tp->vendor_id) ==
1222 (pci_id_tbl[i].id.pci & pci_id_tbl[i].id.pci_mask) ) {
1223 chip_idx = pci_id_tbl[i].drv_flags;
1229 if (chip_idx == -1) {
1230 DBG ("%s: Unknown Tulip Chip: Vendor=%hX Device=%hX\n", tp->nic_name,
1231 tp->vendor_id, tp->dev_id);
1236 tp->flags = tulip_tbl[chip_idx].flags;
1238 DBG2 ("%s: tp->pci_id_idx == %d, name == %s\n", tp->nic_name,
1239 tp->pci_id_idx, pci_id_tbl[tp->pci_id_idx].name);
1240 DBG2 ("%s: chip_idx == %d, name == %s\n", tp->nic_name, chip_idx,
1241 tulip_tbl[chip_idx].chip_name);
1243 /* Bring the 21041/21143 out of sleep mode.
1244 Caution: Snooze mode does not work with some boards! */
1245 if (tp->flags & HAS_PWRDWN)
1246 pci_write_config_dword(pci, 0x40, 0x00000000);
1248 if (inl(ioaddr + CSR5) == 0xFFFFFFFF) {
1249 DBG("%s: The Tulip chip at %X is not functioning.\n",
1250 tp->nic_name, (unsigned int) ioaddr);
1254 pci_read_config_byte(pci, PCI_REVISION, &chip_rev);
1256 DBG("%s: [chip: %s] rev %d at %hX\n", tp->nic_name,
1257 tulip_tbl[chip_idx].chip_name, chip_rev, (unsigned int) ioaddr);
1258 DBG("%s: Vendor=%hX Device=%hX", tp->nic_name, tp->vendor_id, tp->dev_id);
1260 if (chip_idx == DC21041 && inl(ioaddr + CSR9) & 0x8000) {
1261 DBG(" 21040 compatible mode.");
1267 /* The SROM/EEPROM interface varies dramatically. */
1269 if (chip_idx == DC21040) {
1270 outl(0, ioaddr + CSR9); /* Reset the pointer with a dummy write. */
1271 for (i = 0; i < ETH_ALEN; i++) {
1272 int value, boguscnt = 100000;
1274 value = inl(ioaddr + CSR9);
1275 while (value < 0 && --boguscnt > 0);
1276 nic->node_addr[i] = value;
1277 sum += value & 0xff;
1279 } else if (chip_idx == LC82C168) {
1280 for (i = 0; i < 3; i++) {
1281 int value, boguscnt = 100000;
1282 outl(0x600 | i, ioaddr + 0x98);
1284 value = inl(ioaddr + CSR9);
1285 while (value < 0 && --boguscnt > 0);
1286 put_unaligned(le16_to_cpu(value), ((u16*)nic->node_addr) + i);
1287 sum += value & 0xffff;
1289 } else if (chip_idx == COMET) {
1290 /* No need to read the EEPROM. */
1291 put_unaligned(inl(ioaddr + 0xA4), (u32 *)nic->node_addr);
1292 put_unaligned(inl(ioaddr + 0xA8), (u16 *)(nic->node_addr + 4));
1293 for (i = 0; i < ETH_ALEN; i ++)
1294 sum += nic->node_addr[i];
1296 /* A serial EEPROM interface, we read now and sort it out later. */
1298 int ee_addr_size = read_eeprom(ioaddr, 0xff, 8) & 0x40000 ? 8 : 6;
1300 for (i = 0; i < sizeof(ee_data)/2; i++)
1301 ((u16 *)ee_data)[i] =
1302 le16_to_cpu(read_eeprom(ioaddr, i, ee_addr_size));
1304 /* DEC now has a specification (see Notes) but early board makers
1305 just put the address in the first EEPROM locations. */
1306 /* This does memcmp(eedata, eedata+16, 8) */
1307 for (i = 0; i < 8; i ++)
1308 if (ee_data[i] != ee_data[16+i])
1310 if (ee_data[0] == 0xff && ee_data[1] == 0xff && ee_data[2] == 0) {
1311 sa_offset = 2; /* Grrr, damn Matrox boards. */
1313 for (i = 0; i < ETH_ALEN; i ++) {
1314 nic->node_addr[i] = ee_data[i + sa_offset];
1315 sum += ee_data[i + sa_offset];
1318 /* Lite-On boards have the address byte-swapped. */
1319 if ((nic->node_addr[0] == 0xA0 || nic->node_addr[0] == 0xC0)
1320 && nic->node_addr[1] == 0x00)
1321 for (i = 0; i < ETH_ALEN; i+=2) {
1322 char tmp = nic->node_addr[i];
1323 nic->node_addr[i] = nic->node_addr[i+1];
1324 nic->node_addr[i+1] = tmp;
1327 if (sum == 0 || sum == ETH_ALEN*0xff) {
1328 DBG("%s: EEPROM not present!\n", tp->nic_name);
1329 for (i = 0; i < ETH_ALEN-1; i++)
1330 nic->node_addr[i] = last_phys_addr[i];
1331 nic->node_addr[i] = last_phys_addr[i] + 1;
1334 for (i = 0; i < ETH_ALEN; i++)
1335 last_phys_addr[i] = nic->node_addr[i];
1337 DBG ( "%s: %s at ioaddr %hX\n", tp->nic_name, eth_ntoa ( nic->node_addr ),
1338 (unsigned int) ioaddr );
1340 tp->chip_id = chip_idx;
1341 tp->revision = chip_rev;
1344 /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles.
1345 And the ASIX must have a burst limit or horrible things happen. */
1346 if (chip_idx == DC21143 && chip_rev == 65)
1347 tp->csr0 &= ~0x01000000;
1348 else if (tp->flags & IS_ASIX)
1351 if (media_cap[tp->default_port] & MediaIsMII) {
1352 static const u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60,
1353 0x80, 0x100, 0x200 };
1354 tp->mii_advertise = media2advert[tp->default_port - 9];
1355 tp->mii_advertise |= (tp->flags & HAS_8023X); /* Matching bits! */
1358 /* This is logically part of the probe routine, but too complex
1360 if (tp->flags & HAS_MEDIA_TABLE) {
1361 memcpy(tp->eeprom, ee_data, sizeof(tp->eeprom));
1367 /* reset the device and make ready for tx and rx of packets */
1369 nic->nic_op = &tulip_operations;
1371 /* give the board a chance to reset before returning */
1372 tulip_wait(4*TICKS_PER_SEC);
1377 static void start_link(struct nic *nic)
1381 whereami("start_link\n");
1383 if ((tp->flags & ALWAYS_CHECK_MII) ||
1384 (tp->mtable && tp->mtable->has_mii) ||
1385 ( ! tp->mtable && (tp->flags & HAS_MII))) {
1386 unsigned int phy, phy_idx;
1387 if (tp->mtable && tp->mtable->has_mii) {
1388 for (i = 0; i < tp->mtable->leafcount; i++)
1389 if (tp->mtable->mleaf[i].media == 11) {
1391 tp->saved_if_port = tp->if_port;
1392 select_media(nic, 2);
1393 tp->if_port = tp->saved_if_port;
1398 /* Find the connected MII xcvrs. */
1399 for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys);
1401 int mii_status = mdio_read(nic, phy, 1);
1402 if ((mii_status & 0x8301) == 0x8001 ||
1403 ((mii_status & 0x8000) == 0 && (mii_status & 0x7800) != 0)) {
1404 int mii_reg0 = mdio_read(nic, phy, 0);
1405 int mii_advert = mdio_read(nic, phy, 4);
1408 if (tp->mii_advertise)
1409 to_advert = tp->mii_advertise;
1410 else if (tp->advertising[phy_idx])
1411 to_advert = tp->advertising[phy_idx];
1412 else /* Leave unchanged. */
1413 tp->mii_advertise = to_advert = mii_advert;
1415 tp->phys[phy_idx++] = phy;
1416 DBG("%s: MII transceiver %d config %hX status %hX advertising %hX.\n",
1417 tp->nic_name, phy, mii_reg0, mii_status, mii_advert);
1418 /* Fixup for DLink with miswired PHY. */
1419 if (mii_advert != to_advert) {
1420 DBG("%s: Advertising %hX on PHY %d previously advertising %hX.\n",
1421 tp->nic_name, to_advert, phy, mii_advert);
1422 mdio_write(nic, phy, 4, to_advert);
1424 /* Enable autonegotiation: some boards default to off. */
1425 mdio_write(nic, phy, 0, mii_reg0 |
1426 (tp->full_duplex ? 0x1100 : 0x1000) |
1427 (media_cap[tp->default_port]&MediaIs100 ? 0x2000:0));
1430 tp->mii_cnt = phy_idx;
1431 if (tp->mtable && tp->mtable->has_mii && phy_idx == 0) {
1432 DBG("%s: ***WARNING***: No MII transceiver found!\n",
1438 /* Reset the xcvr interface and turn on heartbeat. */
1439 switch (tp->chip_id) {
1441 outl(0x00000000, ioaddr + CSR13);
1442 outl(0x00000004, ioaddr + CSR13);
1445 /* This is nway_start(). */
1446 if (tp->sym_advertise == 0)
1447 tp->sym_advertise = 0x0061;
1448 outl(0x00000000, ioaddr + CSR13);
1449 outl(0xFFFFFFFF, ioaddr + CSR14);
1450 outl(0x00000008, ioaddr + CSR15); /* Listen on AUI also. */
1451 outl(inl(ioaddr + CSR6) | 0x0200, ioaddr + CSR6);
1452 outl(0x0000EF01, ioaddr + CSR13);
1454 case DC21140: default:
1456 outl(tp->mtable->csr12dir | 0x100, ioaddr + CSR12);
1460 if (tp->mii_cnt || media_cap[tp->if_port] & MediaIsMII) {
1461 outl(0x82020000, ioaddr + CSR6);
1462 outl(0x0000, ioaddr + CSR13);
1463 outl(0x0000, ioaddr + CSR14);
1464 outl(0x820E0000, ioaddr + CSR6);
1469 if ( ! tp->mii_cnt) {
1472 outl(0x00420000, ioaddr + CSR6);
1473 outl(0x30, ioaddr + CSR12);
1474 outl(0x0001F078, ioaddr + 0xB8);
1475 outl(0x0201F078, ioaddr + 0xB8); /* Turn on autonegotiation. */
1478 case MX98713: case COMPEX9881:
1479 outl(0x00000000, ioaddr + CSR6);
1480 outl(0x000711C0, ioaddr + CSR14); /* Turn on NWay. */
1481 outl(0x00000001, ioaddr + CSR13);
1483 case MX98715: case MX98725:
1484 outl(0x01a80000, ioaddr + CSR6);
1485 outl(0xFFFFFFFF, ioaddr + CSR14);
1486 outl(0x00001000, ioaddr + CSR12);
1489 /* No initialization necessary. */
1494 static void nway_start(struct nic *nic __unused)
1496 int csr14 = ((tp->sym_advertise & 0x0780) << 9) |
1497 ((tp->sym_advertise&0x0020)<<1) | 0xffbf;
1499 whereami("nway_start\n");
1502 tp->nway = tp->mediasense = 1;
1503 tp->nwayset = tp->lpar = 0;
1504 if (tp->chip_id == PNIC2) {
1505 tp->csr6 = 0x01000000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0);
1508 DBG2("%s: Restarting internal NWay autonegotiation, %X.\n",
1509 tp->nic_name, csr14);
1510 outl(0x0001, ioaddr + CSR13);
1511 outl(csr14, ioaddr + CSR14);
1512 tp->csr6 = 0x82420000 | (tp->sym_advertise & 0x0040 ? 0x0200 : 0);
1513 outl(tp->csr6, ioaddr + CSR6);
1514 if (tp->mtable && tp->mtable->csr15dir) {
1515 outl(tp->mtable->csr15dir, ioaddr + CSR15);
1516 outl(tp->mtable->csr15val, ioaddr + CSR15);
1517 } else if (tp->chip_id != PNIC2)
1518 outw(0x0008, ioaddr + CSR15);
1519 if (tp->chip_id == DC21041) /* Trigger NWAY. */
1520 outl(0xEF01, ioaddr + CSR12);
1522 outl(0x1301, ioaddr + CSR12);
1525 static void init_media(struct nic *nic)
1529 whereami("init_media\n");
1531 tp->saved_if_port = tp->if_port;
1532 if (tp->if_port == 0)
1533 tp->if_port = tp->default_port;
1535 /* Allow selecting a default media. */
1537 if (tp->mtable == NULL)
1540 int looking_for = media_cap[tp->if_port] & MediaIsMII ? 11 :
1541 (tp->if_port == 12 ? 0 : tp->if_port);
1542 for (i = 0; i < tp->mtable->leafcount; i++)
1543 if (tp->mtable->mleaf[i].media == looking_for) {
1544 DBG("%s: Using user-specified media %s.\n",
1545 tp->nic_name, medianame[tp->if_port]);
1549 if ((tp->mtable->defaultmedia & 0x0800) == 0) {
1550 int looking_for = tp->mtable->defaultmedia & 15;
1551 for (i = 0; i < tp->mtable->leafcount; i++)
1552 if (tp->mtable->mleaf[i].media == looking_for) {
1553 DBG("%s: Using EEPROM-set media %s.\n",
1554 tp->nic_name, medianame[looking_for]);
1558 /* Start sensing first non-full-duplex media. */
1559 for (i = tp->mtable->leafcount - 1;
1560 (media_cap[tp->mtable->mleaf[i].media] & MediaAlwaysFD) && i > 0; i--)
1569 if (tp->chip_id == DC21143 && media_cap[tp->if_port] & MediaIsMII) {
1570 /* We must reset the media CSRs when we force-select MII mode. */
1571 outl(0x0000, ioaddr + CSR13);
1572 outl(0x0000, ioaddr + CSR14);
1573 outl(0x0008, ioaddr + CSR15);
1575 select_media(nic, 1);
1578 switch(tp->chip_id) {
1585 select_media(nic, 1);
1586 DBG2("%s: Using MII transceiver %d, status %hX.\n",
1587 tp->nic_name, tp->phys[0], mdio_read(nic, tp->phys[0], 1));
1588 outl(0x82020000, ioaddr + CSR6);
1589 tp->csr6 = 0x820E0000;
1591 outl(0x0000, ioaddr + CSR13);
1592 outl(0x0000, ioaddr + CSR14);
1602 tp->csr6 = 0x814C0000 | (tp->full_duplex ? 0x0200 : 0);
1603 outl(0x0001, ioaddr + CSR15);
1604 } else if (inl(ioaddr + CSR5) & TPLnkPass)
1607 /* Start with 10mbps to do autonegotiation. */
1608 outl(0x32, ioaddr + CSR12);
1609 tp->csr6 = 0x00420000;
1610 outl(0x0001B078, ioaddr + 0xB8);
1611 outl(0x0201B078, ioaddr + 0xB8);
1614 case MX98713: case COMPEX9881:
1616 tp->csr6 = 0x01880000 | (tp->full_duplex ? 0x0200 : 0);
1617 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
1619 case MX98715: case MX98725:
1620 /* Provided by BOLO, Macronix - 12/10/1998. */
1622 tp->csr6 = 0x01a80200;
1623 outl(0x0f370000 | inw(ioaddr + 0x80), ioaddr + 0x80);
1624 outl(0x11000 | inw(ioaddr + 0xa0), ioaddr + 0xa0);
1627 /* Enable automatic Tx underrun recovery */
1628 outl(inl(ioaddr + 0x88) | 1, ioaddr + 0x88);
1630 tp->csr6 = 0x00040000;
1632 case AX88140: case AX88141:
1633 tp->csr6 = tp->mii_cnt ? 0x00040100 : 0x00000100;
1636 select_media(nic, 1);
1640 static void pnic_do_nway(struct nic *nic __unused)
1642 u32 phy_reg = inl(ioaddr + 0xB8);
1643 u32 new_csr6 = tp->csr6 & ~0x40C40200;
1645 whereami("pnic_do_nway\n");
1647 if (phy_reg & 0x78000000) { /* Ignore baseT4 */
1648 if (phy_reg & 0x20000000) tp->if_port = 5;
1649 else if (phy_reg & 0x40000000) tp->if_port = 3;
1650 else if (phy_reg & 0x10000000) tp->if_port = 4;
1651 else if (phy_reg & 0x08000000) tp->if_port = 0;
1653 new_csr6 = (tp->if_port & 1) ? 0x01860000 : 0x00420000;
1654 outl(0x32 | (tp->if_port & 1), ioaddr + CSR12);
1655 if (tp->if_port & 1)
1656 outl(0x1F868, ioaddr + 0xB8);
1657 if (phy_reg & 0x30000000) {
1658 tp->full_duplex = 1;
1659 new_csr6 |= 0x00000200;
1661 DBG2("%s: PNIC autonegotiated status %X, %s.\n",
1662 tp->nic_name, phy_reg, medianame[tp->if_port]);
1663 if (tp->csr6 != new_csr6) {
1664 tp->csr6 = new_csr6;
1665 outl(tp->csr6 | 0x0002, ioaddr + CSR6); /* Restart Tx */
1666 outl(tp->csr6 | 0x2002, ioaddr + CSR6);
1671 /* Set up the transceiver control registers for the selected media type. */
1672 static void select_media(struct nic *nic, int startup)
1674 struct mediatable *mtable = tp->mtable;
1678 whereami("select_media\n");
1681 struct medialeaf *mleaf = &mtable->mleaf[tp->cur_index];
1682 unsigned char *p = mleaf->leafdata;
1683 switch (mleaf->type) {
1684 case 0: /* 21140 non-MII xcvr. */
1685 DBG2("%s: Using a 21140 non-MII transceiver"
1686 " with control setting %hhX.\n",
1687 tp->nic_name, p[1]);
1690 outl(mtable->csr12dir | 0x100, ioaddr + CSR12);
1691 outl(p[1], ioaddr + CSR12);
1692 new_csr6 = 0x02000000 | ((p[2] & 0x71) << 18);
1696 u32 csr13val, csr14val, csr15dir, csr15val;
1697 for (i = 0; i < 5; i++)
1698 setup[i] = get_u16(&p[i*2 + 1]);
1700 tp->if_port = p[0] & 15;
1701 if (media_cap[tp->if_port] & MediaAlwaysFD)
1702 tp->full_duplex = 1;
1704 if (startup && mtable->has_reset) {
1705 struct medialeaf *rleaf = &mtable->mleaf[mtable->has_reset];
1706 unsigned char *rst = rleaf->leafdata;
1707 DBG2("%s: Resetting the transceiver.\n",
1709 for (i = 0; i < rst[0]; i++)
1710 outl(get_u16(rst + 1 + (i<<1)) << 16, ioaddr + CSR15);
1712 DBG2("%s: 21143 non-MII %s transceiver control %hX/%hX.\n",
1713 tp->nic_name, medianame[tp->if_port], setup[0], setup[1]);
1714 if (p[0] & 0x40) { /* SIA (CSR13-15) setup values are provided. */
1715 csr13val = setup[0];
1716 csr14val = setup[1];
1717 csr15dir = (setup[3]<<16) | setup[2];
1718 csr15val = (setup[4]<<16) | setup[2];
1719 outl(0, ioaddr + CSR13);
1720 outl(csr14val, ioaddr + CSR14);
1721 outl(csr15dir, ioaddr + CSR15); /* Direction */
1722 outl(csr15val, ioaddr + CSR15); /* Data */
1723 outl(csr13val, ioaddr + CSR13);
1726 csr14val = 0x0003FF7F;
1727 csr15dir = (setup[0]<<16) | 0x0008;
1728 csr15val = (setup[1]<<16) | 0x0008;
1729 if (tp->if_port <= 4)
1730 csr14val = t21142_csr14[tp->if_port];
1732 outl(0, ioaddr + CSR13);
1733 outl(csr14val, ioaddr + CSR14);
1735 outl(csr15dir, ioaddr + CSR15); /* Direction */
1736 outl(csr15val, ioaddr + CSR15); /* Data */
1737 if (startup) outl(csr13val, ioaddr + CSR13);
1739 DBG2("%s: Setting CSR15 to %X/%X.\n",
1740 tp->nic_name, csr15dir, csr15val);
1741 if (mleaf->type == 4)
1742 new_csr6 = 0x82020000 | ((setup[2] & 0x71) << 18);
1744 new_csr6 = 0x82420000;
1749 int init_length = p[1];
1753 new_csr6 = 0x020E0000;
1754 if (mleaf->type == 3) { /* 21142 */
1755 u16 *init_sequence = (u16*)(p+2);
1756 u16 *reset_sequence = &((u16*)(p+3))[init_length];
1757 int reset_length = p[2 + init_length*2];
1758 misc_info = reset_sequence + reset_length;
1760 for (i = 0; i < reset_length; i++)
1761 outl(get_u16(&reset_sequence[i]) << 16, ioaddr + CSR15);
1762 for (i = 0; i < init_length; i++)
1763 outl(get_u16(&init_sequence[i]) << 16, ioaddr + CSR15);
1765 u8 *init_sequence = p + 2;
1766 u8 *reset_sequence = p + 3 + init_length;
1767 int reset_length = p[2 + init_length];
1768 misc_info = (u16*)(reset_sequence + reset_length);
1770 outl(mtable->csr12dir | 0x100, ioaddr + CSR12);
1771 for (i = 0; i < reset_length; i++)
1772 outl(reset_sequence[i], ioaddr + CSR12);
1774 for (i = 0; i < init_length; i++)
1775 outl(init_sequence[i], ioaddr + CSR12);
1777 tp->advertising[phy_num] = get_u16(&misc_info[1]) | 1;
1779 if (tp->mii_advertise == 0)
1780 tp->mii_advertise = tp->advertising[phy_num];
1781 DBG2("%s: Advertising %hX on MII %d.\n",
1782 tp->nic_name, tp->mii_advertise, tp->phys[phy_num]);
1783 mdio_write(nic, tp->phys[phy_num], 4, tp->mii_advertise);
1788 DBG("%s: Invalid media table selection %d.\n",
1789 tp->nic_name, mleaf->type);
1790 new_csr6 = 0x020E0000;
1792 DBG2("%s: Using media type %s, CSR12 is %hhX.\n",
1793 tp->nic_name, medianame[tp->if_port],
1794 inl(ioaddr + CSR12) & 0xff);
1795 } else if (tp->chip_id == DC21041) {
1796 int port = tp->if_port <= 4 ? tp->if_port : 0;
1797 DBG2("%s: 21041 using media %s, CSR12 is %hX.\n",
1798 tp->nic_name, medianame[port == 3 ? 12: port],
1799 inl(ioaddr + CSR12));
1800 outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */
1801 outl(t21041_csr14[port], ioaddr + CSR14);
1802 outl(t21041_csr15[port], ioaddr + CSR15);
1803 outl(t21041_csr13[port], ioaddr + CSR13);
1804 new_csr6 = 0x80020000;
1805 } else if (tp->chip_id == LC82C168) {
1806 if (startup && ! tp->medialock)
1807 tp->if_port = tp->mii_cnt ? 11 : 0;
1808 DBG2("%s: PNIC PHY status is %hX, media %s.\n",
1809 tp->nic_name, inl(ioaddr + 0xB8), medianame[tp->if_port]);
1811 new_csr6 = 0x810C0000;
1812 outl(0x0001, ioaddr + CSR15);
1813 outl(0x0201B07A, ioaddr + 0xB8);
1814 } else if (startup) {
1815 /* Start with 10mbps to do autonegotiation. */
1816 outl(0x32, ioaddr + CSR12);
1817 new_csr6 = 0x00420000;
1818 outl(0x0001B078, ioaddr + 0xB8);
1819 outl(0x0201B078, ioaddr + 0xB8);
1820 } else if (tp->if_port == 3 || tp->if_port == 5) {
1821 outl(0x33, ioaddr + CSR12);
1822 new_csr6 = 0x01860000;
1823 /* Trigger autonegotiation. */
1824 outl(startup ? 0x0201F868 : 0x0001F868, ioaddr + 0xB8);
1826 outl(0x32, ioaddr + CSR12);
1827 new_csr6 = 0x00420000;
1828 outl(0x1F078, ioaddr + 0xB8);
1830 } else if (tp->chip_id == DC21040) { /* 21040 */
1831 /* Turn on the xcvr interface. */
1832 int csr12 = inl(ioaddr + CSR12);
1833 DBG2("%s: 21040 media type is %s, CSR12 is %hhX.\n",
1834 tp->nic_name, medianame[tp->if_port], csr12);
1835 if (media_cap[tp->if_port] & MediaAlwaysFD)
1836 tp->full_duplex = 1;
1838 /* Set the full duplux match frame. */
1839 outl(FULL_DUPLEX_MAGIC, ioaddr + CSR11);
1840 outl(0x00000000, ioaddr + CSR13); /* Reset the serial interface */
1841 if (t21040_csr13[tp->if_port] & 8) {
1842 outl(0x0705, ioaddr + CSR14);
1843 outl(0x0006, ioaddr + CSR15);
1845 outl(0xffff, ioaddr + CSR14);
1846 outl(0x0000, ioaddr + CSR15);
1848 outl(0x8f01 | t21040_csr13[tp->if_port], ioaddr + CSR13);
1849 } else { /* Unknown chip type with no media table. */
1850 if (tp->default_port == 0)
1851 tp->if_port = tp->mii_cnt ? 11 : 3;
1852 if (media_cap[tp->if_port] & MediaIsMII) {
1853 new_csr6 = 0x020E0000;
1854 } else if (media_cap[tp->if_port] & MediaIsFx) {
1855 new_csr6 = 0x028600000;
1857 new_csr6 = 0x038600000;
1858 DBG2("%s: No media description table, assuming "
1859 "%s transceiver, CSR12 %hhX.\n",
1860 tp->nic_name, medianame[tp->if_port],
1861 inl(ioaddr + CSR12));
1864 tp->csr6 = new_csr6 | (tp->csr6 & 0xfdff) | (tp->full_duplex ? 0x0200 : 0);
1869 Check the MII negotiated duplex and change the CSR6 setting if
1871 Return 0 if everything is OK.
1872 Return < 0 if the transceiver is missing or has no link beat.
1874 static int tulip_check_duplex(struct nic *nic)
1876 unsigned int bmsr, lpa, negotiated, new_csr6;
1878 bmsr = mdio_read(nic, tp->phys[0], 1);
1879 lpa = mdio_read(nic, tp->phys[0], 5);
1881 DBG2("%s: MII status %#x, Link partner report %#x.\n",
1882 tp->nic_name, bmsr, lpa);
1886 if ((bmsr & 4) == 0) {
1887 int new_bmsr = mdio_read(nic, tp->phys[0], 1);
1888 if ((new_bmsr & 4) == 0) {
1889 DBG2("%s: No link beat on the MII interface,"
1890 " status %#x.\n", tp->nic_name,
1895 tp->full_duplex = lpa & 0x140;
1897 new_csr6 = tp->csr6;
1898 negotiated = lpa & tp->advertising[0];
1900 if(negotiated & 0x380) new_csr6 &= ~0x400000;
1901 else new_csr6 |= 0x400000;
1902 if (tp->full_duplex) new_csr6 |= 0x200;
1903 else new_csr6 &= ~0x200;
1905 if (new_csr6 != tp->csr6) {
1906 tp->csr6 = new_csr6;
1908 DBG("%s: Setting %s-duplex based on MII"
1909 "#%d link partner capability of %#x.\n",
1911 tp->full_duplex ? "full" : "half",
1919 static struct pci_device_id tulip_nics[] = {
1920 PCI_ROM(0x1011, 0x0002, "dc21040", "Digital Tulip", 0),
1921 PCI_ROM(0x1011, 0x0009, "ds21140", "Digital Tulip Fast", 0),
1922 PCI_ROM(0x1011, 0x0014, "dc21041", "Digital Tulip+", 0),
1923 PCI_ROM(0x1011, 0x0019, "ds21142", "Digital Tulip 21142", 0),
1924 PCI_ROM(0x10b7, 0x9300, "3csoho100b-tx","3ComSOHO100B-TX", 0),
1925 PCI_ROM(0x10b9, 0x5261, "ali1563", "ALi 1563 integrated ethernet", 0),
1926 PCI_ROM(0x10d9, 0x0512, "mx98713", "Macronix MX987x3", 0),
1927 PCI_ROM(0x10d9, 0x0531, "mx98715", "Macronix MX987x5", 0),
1928 PCI_ROM(0x1113, 0x1217, "mxic-98715", "Macronix MX987x5", 0),
1929 PCI_ROM(0x11ad, 0xc115, "lc82c115", "LinkSys LNE100TX", 0),
1930 PCI_ROM(0x11ad, 0x0002, "82c168", "Netgear FA310TX", 0),
1931 PCI_ROM(0x1282, 0x9100, "dm9100", "Davicom 9100", 0),
1932 PCI_ROM(0x1282, 0x9102, "dm9102", "Davicom 9102", 0),
1933 PCI_ROM(0x1282, 0x9009, "dm9009", "Davicom 9009", 0),
1934 PCI_ROM(0x1282, 0x9132, "dm9132", "Davicom 9132", 0),
1935 PCI_ROM(0x1317, 0x0985, "centaur-p", "ADMtek Centaur-P", 0),
1936 PCI_ROM(0x1317, 0x0981, "an981", "ADMtek AN981 Comet", 0), /* ADMTek Centaur-P (stmicro) */
1937 PCI_ROM(0x1113, 0x1216, "an983", "ADMTek AN983 Comet", 0),
1938 PCI_ROM(0x1317, 0x9511, "an983b", "ADMTek Comet 983b", 0),
1939 PCI_ROM(0x1317, 0x1985, "centaur-c", "ADMTek Centaur-C", 0),
1940 PCI_ROM(0x8086, 0x0039, "intel21145", "Intel Tulip", 0),
1941 PCI_ROM(0x125b, 0x1400, "ax88140", "ASIX AX88140", 0),
1942 PCI_ROM(0x11f6, 0x9881, "rl100tx", "Compex RL100-TX", 0),
1943 PCI_ROM(0x115d, 0x0003, "xircomtulip", "Xircom Tulip", 0),
1944 PCI_ROM(0x104a, 0x0981, "tulip-0981", "Tulip 0x104a 0x0981", 0),
1945 PCI_ROM(0x104a, 0x2774, "SGThomson-STE10100A", "Tulip 0x104a 0x2774", 0), /*Modified by Ramesh Chander*/
1946 PCI_ROM(0x1113, 0x9511, "tulip-9511", "Tulip 0x1113 0x9511", 0),
1947 PCI_ROM(0x1186, 0x1561, "tulip-1561", "Tulip 0x1186 0x1561", 0),
1948 PCI_ROM(0x1259, 0xa120, "tulip-a120", "Tulip 0x1259 0xa120", 0),
1949 PCI_ROM(0x13d1, 0xab02, "tulip-ab02", "Tulip 0x13d1 0xab02", 0),
1950 PCI_ROM(0x13d1, 0xab03, "tulip-ab03", "Tulip 0x13d1 0xab03", 0),
1951 PCI_ROM(0x13d1, 0xab08, "tulip-ab08", "Tulip 0x13d1 0xab08", 0),
1952 PCI_ROM(0x14f1, 0x1803, "lanfinity", "Conexant LANfinity", 0),
1953 PCI_ROM(0x1626, 0x8410, "tulip-8410", "Tulip 0x1626 0x8410", 0),
1954 PCI_ROM(0x1737, 0xab08, "tulip-1737-ab08","Tulip 0x1737 0xab08", 0),
1955 PCI_ROM(0x1737, 0xab09, "tulip-ab09", "Tulip 0x1737 0xab09", 0),
1958 PCI_DRIVER ( tulip_driver, tulip_nics, PCI_NO_CLASS );
1960 DRIVER ( "Tulip", nic_driver, pci_driver, tulip_driver,
1961 tulip_probe, tulip_disable );