qemu/roms/ipxe/src/drivers/net/tlan.c

   1 /**************************************************************************
   2 *
   3 *    tlan.c -- Etherboot device driver for the Texas Instruments ThunderLAN
   4 *    Written 2003-2003 by Timothy Legge <tlegge@rogers.com>
   5 *
   6 *    This program is free software; you can redistribute it and/or modify
   7 *    it under the terms of the GNU General Public License as published by
   8 *    the Free Software Foundation; either version 2 of the License, or
   9 *    (at your option) any later version.
  10 *
  11 *    This program is distributed in the hope that it will be useful,
  12 *    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 *    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 *    GNU General Public License for more details.
  15 *
  16 *    You should have received a copy of the GNU General Public License
  17 *    along with this program; if not, write to the Free Software
  18 *    Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
  19 *    02110-1301, USA.
  20 *
  21 *    Portions of this code based on:
  22 *       lan.c: Linux ThunderLan Driver:
  23 *
  24 *       by James Banks
  25 *
  26 *       (C) 1997-1998 Caldera, Inc.
  27 *       (C) 1998 James Banks
  28 *       (C) 1999-2001 Torben Mathiasen
  29 *       (C) 2002 Samuel Chessman
  30 *
  31 *    REVISION HISTORY:
  32 *    ================
  33 *    v1.0       07-08-2003      timlegge        Initial not quite working version
  34 *    v1.1       07-27-2003      timlegge        Sync 5.0 and 5.1 versions
  35 *    v1.2       08-19-2003      timlegge        Implement Multicast Support
  36 *    v1.3       08-23-2003      timlegge        Fix the transmit Function
  37 *    v1.4       01-17-2004      timlegge        Initial driver output cleanup
  38 *
  39 *    Indent Options: indent -kr -i8
  40 ***************************************************************************/
  41
  42 FILE_LICENCE ( GPL2_OR_LATER );
  43
  44 #include "etherboot.h"
  45 #include "nic.h"
  46 #include <ipxe/pci.h>
  47 #include <ipxe/ethernet.h>
  48 #include <mii.h>
  49 #include "tlan.h"
  50
  51 #define drv_version "v1.4"
  52 #define drv_date "01-17-2004"
  53
  54 /* NIC specific static variables go here */
  55 #define HZ 100
  56 #define TX_TIME_OUT       (6*HZ)
  57
  58 /* Condensed operations for readability. */
  59 #define virt_to_le32desc(addr)  cpu_to_le32(virt_to_bus(addr))
  60 #define le32desc_to_virt(addr)  bus_to_virt(le32_to_cpu(addr))
  61
  62 static void TLan_ResetLists(struct nic *nic __unused);
  63 static void TLan_ResetAdapter(struct nic *nic __unused);
  64 static void TLan_FinishReset(struct nic *nic __unused);
  65
  66 static void TLan_EeSendStart(u16);
  67 static int TLan_EeSendByte(u16, u8, int);
  68 static void TLan_EeReceiveByte(u16, u8 *, int);
  69 static int TLan_EeReadByte(u16 io_base, u8, u8 *);
  70
  71 static void TLan_PhyDetect(struct nic *nic);
  72 static void TLan_PhyPowerDown(struct nic *nic);
  73 static void TLan_PhyPowerUp(struct nic *nic);
  74
  75
  76 static void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac);
  77
  78 static void TLan_PhyReset(struct nic *nic);
  79 static void TLan_PhyStartLink(struct nic *nic);
  80 static void TLan_PhyFinishAutoNeg(struct nic *nic);
  81
  82 #ifdef MONITOR
  83 static void TLan_PhyMonitor(struct nic *nic);
  84 #endif
  85
  86
  87 static void refill_rx(struct nic *nic __unused);
  88
  89 static int TLan_MiiReadReg(struct nic *nic __unused, u16, u16, u16 *);
  90 static void TLan_MiiSendData(u16, u32, unsigned);
  91 static void TLan_MiiSync(u16);
  92 static void TLan_MiiWriteReg(struct nic *nic __unused, u16, u16, u16);
  93
  94
  95 static const char *media[] = {
  96         "10BaseT-HD ", "10BaseT-FD ", "100baseTx-HD ",
  97         "100baseTx-FD", "100baseT4", NULL
  98 };
  99
 100 /* This much match tlan_pci_tbl[]!  */
 101 enum tlan_nics {
 102         NETEL10 = 0, NETEL100 = 1, NETFLEX3I = 2, THUNDER = 3, NETFLEX3B =
 103             4, NETEL100PI = 5,
 104         NETEL100D = 6, NETEL100I = 7, OC2183 = 8, OC2325 = 9, OC2326 =
 105             10, NETELLIGENT_10_100_WS_5100 = 11,
 106         NETELLIGENT_10_T2 = 12
 107 };
 108
 109 struct pci_id_info {
 110         const char *name;
 111         int nic_id;
 112         struct match_info {
 113                 u32 pci, pci_mask, subsystem, subsystem_mask;
 114                 u32 revision, revision_mask;    /* Only 8 bits. */
 115         } id;
 116         u32 flags;
 117         u16 addrOfs;            /* Address Offset */
 118 };
 119
 120 static const struct pci_id_info tlan_pci_tbl[] = {
 121         {"Compaq Netelligent 10 T PCI UTP", NETEL10,
 122          {0xae340e11, 0xffffffff, 0, 0, 0, 0},
 123          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
 124         {"Compaq Netelligent 10/100 TX PCI UTP", NETEL100,
 125          {0xae320e11, 0xffffffff, 0, 0, 0, 0},
 126          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
 127         {"Compaq Integrated NetFlex-3/P", NETFLEX3I,
 128          {0xae350e11, 0xffffffff, 0, 0, 0, 0},
 129          TLAN_ADAPTER_NONE, 0x83},
 130         {"Compaq NetFlex-3/P", THUNDER,
 131          {0xf1300e11, 0xffffffff, 0, 0, 0, 0},
 132          TLAN_ADAPTER_UNMANAGED_PHY | TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
 133         {"Compaq NetFlex-3/P", NETFLEX3B,
 134          {0xf1500e11, 0xffffffff, 0, 0, 0, 0},
 135          TLAN_ADAPTER_NONE, 0x83},
 136         {"Compaq Netelligent Integrated 10/100 TX UTP", NETEL100PI,
 137          {0xae430e11, 0xffffffff, 0, 0, 0, 0},
 138          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
 139         {"Compaq Netelligent Dual 10/100 TX PCI UTP", NETEL100D,
 140          {0xae400e11, 0xffffffff, 0, 0, 0, 0},
 141          TLAN_ADAPTER_NONE, 0x83},
 142         {"Compaq Netelligent 10/100 TX Embedded UTP", NETEL100I,
 143          {0xb0110e11, 0xffffffff, 0, 0, 0, 0},
 144          TLAN_ADAPTER_NONE, 0x83},
 145         {"Olicom OC-2183/2185", OC2183,
 146          {0x0013108d, 0xffffffff, 0, 0, 0, 0},
 147          TLAN_ADAPTER_USE_INTERN_10, 0x83},
 148         {"Olicom OC-2325", OC2325,
 149          {0x0012108d, 0xffffffff, 0, 0, 0, 0},
 150          TLAN_ADAPTER_UNMANAGED_PHY, 0xF8},
 151         {"Olicom OC-2326", OC2326,
 152          {0x0014108d, 0xffffffff, 0, 0, 0, 0},
 153          TLAN_ADAPTER_USE_INTERN_10, 0xF8},
 154         {"Compaq Netelligent 10/100 TX UTP", NETELLIGENT_10_100_WS_5100,
 155          {0xb0300e11, 0xffffffff, 0, 0, 0, 0},
 156          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
 157         {"Compaq Netelligent 10 T/2 PCI UTP/Coax", NETELLIGENT_10_T2,
 158          {0xb0120e11, 0xffffffff, 0, 0, 0, 0},
 159          TLAN_ADAPTER_NONE, 0x83},
 160         {"Compaq NetFlex-3/E", 0,       /* EISA card */
 161          {0, 0, 0, 0, 0, 0},
 162          TLAN_ADAPTER_ACTIVITY_LED | TLAN_ADAPTER_UNMANAGED_PHY |
 163          TLAN_ADAPTER_BIT_RATE_PHY, 0x83},
 164         {"Compaq NetFlex-3/E", 0,       /* EISA card */
 165          {0, 0, 0, 0, 0, 0},
 166          TLAN_ADAPTER_ACTIVITY_LED, 0x83},
 167         {NULL, 0,
 168          {0, 0, 0, 0, 0, 0},
 169          0, 0},
 170 };
 171
 172 struct TLanList {
 173         u32 forward;
 174         u16 cStat;
 175         u16 frameSize;
 176         struct {
 177                 u32 count;
 178                 u32 address;
 179         } buffer[TLAN_BUFFERS_PER_LIST];
 180 };
 181
 182 struct {
 183         struct TLanList tx_ring[TLAN_NUM_TX_LISTS];
 184         unsigned char txb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_TX_LISTS];
 185         struct TLanList rx_ring[TLAN_NUM_RX_LISTS];
 186         unsigned char rxb[TLAN_MAX_FRAME_SIZE * TLAN_NUM_RX_LISTS];
 187 } tlan_buffers __shared;
 188 #define tx_ring tlan_buffers.tx_ring
 189 #define txb tlan_buffers.txb
 190 #define rx_ring tlan_buffers.rx_ring
 191 #define rxb tlan_buffers.rxb
 192
 193 typedef u8 TLanBuffer[TLAN_MAX_FRAME_SIZE];
 194
 195 static int chip_idx;
 196
 197 /*****************************************************************
 198 * TLAN Private Information Structure
 199 *
 200 ****************************************************************/
 201 static struct tlan_private {
 202         unsigned short vendor_id;       /* PCI Vendor code */
 203         unsigned short dev_id;  /* PCI Device code */
 204         const char *nic_name;
 205         unsigned int cur_rx, dirty_rx;  /* Producer/consumer ring indices */
 206         unsigned rx_buf_sz;     /* Based on mtu + Slack */
 207         struct TLanList *txList;
 208         u32 txHead;
 209         u32 txInProgress;
 210         u32 txTail;
 211         int eoc;
 212         u32 phyOnline;
 213         u32 aui;
 214         u32 duplex;
 215         u32 phy[2];
 216         u32 phyNum;
 217         u32 speed;
 218         u8 tlanRev;
 219         u8 tlanFullDuplex;
 220         u8 link;
 221         u8 neg_be_verbose;
 222 } TLanPrivateInfo;
 223
 224 static struct tlan_private *priv;
 225
 226 static u32 BASE;
 227
 228 /***************************************************************
 229 *       TLan_ResetLists
 230 *
 231 *       Returns:
 232 *               Nothing
 233 *       Parms:
 234 *               dev     The device structure with the list
 235 *                       stuctures to be reset.
 236 *
 237 *       This routine sets the variables associated with managing
 238 *       the TLAN lists to their initial values.
 239 *
 240 **************************************************************/
 241
 242 static void TLan_ResetLists(struct nic *nic __unused)
 243 {
 244
 245         int i;
 246         struct TLanList *list;
 247         priv->txHead = 0;
 248         priv->txTail = 0;
 249
 250         for (i = 0; i < TLAN_NUM_TX_LISTS; i++) {
 251                 list = &tx_ring[i];
 252                 list->cStat = TLAN_CSTAT_UNUSED;
 253                 list->buffer[0].address = virt_to_bus(txb +
 254                                 (i * TLAN_MAX_FRAME_SIZE));
 255                 list->buffer[2].count = 0;
 256                 list->buffer[2].address = 0;
 257                 list->buffer[9].address = 0;
 258         }
 259
 260         priv->cur_rx = 0;
 261         priv->rx_buf_sz = (TLAN_MAX_FRAME_SIZE);
 262 //      priv->rx_head_desc = &rx_ring[0];
 263
 264         /* Initialize all the Rx descriptors */
 265         for (i = 0; i < TLAN_NUM_RX_LISTS; i++) {
 266                 rx_ring[i].forward = virt_to_le32desc(&rx_ring[i + 1]);
 267                 rx_ring[i].cStat = TLAN_CSTAT_READY;
 268                 rx_ring[i].frameSize = TLAN_MAX_FRAME_SIZE;
 269                 rx_ring[i].buffer[0].count =
 270                     TLAN_MAX_FRAME_SIZE | TLAN_LAST_BUFFER;
 271                 rx_ring[i].buffer[0].address =
 272                     virt_to_le32desc(&rxb[i * TLAN_MAX_FRAME_SIZE]);
 273                 rx_ring[i].buffer[1].count = 0;
 274                 rx_ring[i].buffer[1].address = 0;
 275         }
 276
 277         /* Mark the last entry as wrapping the ring */
 278         rx_ring[i - 1].forward = virt_to_le32desc(&rx_ring[0]);
 279         priv->dirty_rx = (unsigned int) (i - TLAN_NUM_RX_LISTS);
 280
 281 } /* TLan_ResetLists */
 282
 283 /***************************************************************
 284 *       TLan_Reset
 285 *
 286 *       Returns:
 287 *               0
 288 *       Parms:
 289 *               dev     Pointer to device structure of adapter
 290 *                       to be reset.
 291 *
 292 *       This function resets the adapter and it's physical
 293 *       device.  See Chap. 3, pp. 9-10 of the "ThunderLAN
 294 *       Programmer's Guide" for details.  The routine tries to
 295 *       implement what is detailed there, though adjustments
 296 *       have been made.
 297 *
 298 **************************************************************/
 299
 300 void TLan_ResetAdapter(struct nic *nic __unused)
 301 {
 302         int i;
 303         u32 addr;
 304         u32 data;
 305         u8 data8;
 306
 307         priv->tlanFullDuplex = FALSE;
 308         priv->phyOnline = 0;
 309 /*  1.  Assert reset bit. */
 310
 311         data = inl(BASE + TLAN_HOST_CMD);
 312         data |= TLAN_HC_AD_RST;
 313         outl(data, BASE + TLAN_HOST_CMD);
 314
 315         udelay(1000);
 316
 317 /*  2.  Turn off interrupts. ( Probably isn't necessary ) */
 318
 319         data = inl(BASE + TLAN_HOST_CMD);
 320         data |= TLAN_HC_INT_OFF;
 321         outl(data, BASE + TLAN_HOST_CMD);
 322 /*  3.  Clear AREGs and HASHs. */
 323
 324         for (i = TLAN_AREG_0; i <= TLAN_HASH_2; i += 4) {
 325                 TLan_DioWrite32(BASE, (u16) i, 0);
 326         }
 327
 328 /*  4.  Setup NetConfig register. */
 329
 330         data =
 331             TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN | TLAN_NET_CFG_PHY_EN;
 332         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
 333
 334 /*  5.  Load Ld_Tmr and Ld_Thr in HOST_CMD. */
 335
 336         outl(TLAN_HC_LD_TMR | 0x3f, BASE + TLAN_HOST_CMD);
 337         outl(TLAN_HC_LD_THR | 0x0, BASE + TLAN_HOST_CMD);
 338
 339 /*  6.  Unreset the MII by setting NMRST (in NetSio) to 1. */
 340
 341         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
 342         addr = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
 343         TLan_SetBit(TLAN_NET_SIO_NMRST, addr);
 344
 345 /*  7.  Setup the remaining registers. */
 346
 347         if (priv->tlanRev >= 0x30) {
 348                 data8 = TLAN_ID_TX_EOC | TLAN_ID_RX_EOC;
 349                 TLan_DioWrite8(BASE, TLAN_INT_DIS, data8);
 350         }
 351         TLan_PhyDetect(nic);
 352         data = TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN;
 353
 354         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_BIT_RATE_PHY) {
 355                 data |= TLAN_NET_CFG_BIT;
 356                 if (priv->aui == 1) {
 357                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x0a);
 358                 } else if (priv->duplex == TLAN_DUPLEX_FULL) {
 359                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x00);
 360                         priv->tlanFullDuplex = TRUE;
 361                 } else {
 362                         TLan_DioWrite8(BASE, TLAN_ACOMMIT, 0x08);
 363                 }
 364         }
 365
 366         if (priv->phyNum == 0) {
 367                 data |= TLAN_NET_CFG_PHY_EN;
 368         }
 369         TLan_DioWrite16(BASE, TLAN_NET_CONFIG, (u16) data);
 370
 371         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
 372                 TLan_FinishReset(nic);
 373         } else {
 374                 TLan_PhyPowerDown(nic);
 375         }
 376
 377 }       /* TLan_ResetAdapter */
 378
 379 void TLan_FinishReset(struct nic *nic)
 380 {
 381
 382         u8 data;
 383         u32 phy;
 384         u8 sio;
 385         u16 status;
 386         u16 partner;
 387         u16 tlphy_ctl;
 388         u16 tlphy_par;
 389         u16 tlphy_id1, tlphy_id2;
 390         int i;
 391
 392         phy = priv->phy[priv->phyNum];
 393
 394         data = TLAN_NET_CMD_NRESET | TLAN_NET_CMD_NWRAP;
 395         if (priv->tlanFullDuplex) {
 396                 data |= TLAN_NET_CMD_DUPLEX;
 397         }
 398         TLan_DioWrite8(BASE, TLAN_NET_CMD, data);
 399         data = TLAN_NET_MASK_MASK4 | TLAN_NET_MASK_MASK5;
 400         if (priv->phyNum == 0) {
 401                 data |= TLAN_NET_MASK_MASK7;
 402         }
 403         TLan_DioWrite8(BASE, TLAN_NET_MASK, data);
 404         TLan_DioWrite16(BASE, TLAN_MAX_RX, ((1536) + 7) & ~7);
 405         TLan_MiiReadReg(nic, phy, MII_PHYSID1, &tlphy_id1);
 406         TLan_MiiReadReg(nic, phy, MII_PHYSID2, &tlphy_id2);
 407
 408         if ((tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY)
 409             || (priv->aui)) {
 410                 status = BMSR_LSTATUS;
 411                 DBG ( "TLAN:  %s: Link forced.\n", priv->nic_name );
 412         } else {
 413                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
 414                 udelay(1000);
 415                 TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
 416                 if ((status & BMSR_LSTATUS) &&  /* We only support link info on Nat.Sem. PHY's */
 417                     (tlphy_id1 == NAT_SEM_ID1)
 418                     && (tlphy_id2 == NAT_SEM_ID2)) {
 419                         TLan_MiiReadReg(nic, phy, MII_LPA, &partner);
 420                         TLan_MiiReadReg(nic, phy, TLAN_TLPHY_PAR,
 421                                         &tlphy_par);
 422
 423                         DBG ( "TLAN: %s: Link active with ",
 424                                priv->nic_name );
 425                         if (!(tlphy_par & TLAN_PHY_AN_EN_STAT)) {
 426                                 DBG ( "forced 10%sMbps %s-Duplex\n",
 427                                        tlphy_par & TLAN_PHY_SPEED_100 ? ""
 428                                        : "0",
 429                                        tlphy_par & TLAN_PHY_DUPLEX_FULL ?
 430                                        "Full" : "Half" );
 431                         } else {
 432                                 DBG
 433                                     ( "AutoNegotiation enabled, at 10%sMbps %s-Duplex\n",
 434                                      tlphy_par & TLAN_PHY_SPEED_100 ? "" :
 435                                      "0",
 436                                      tlphy_par & TLAN_PHY_DUPLEX_FULL ?
 437                                      "Full" : "Half" );
 438                                 DBG ( "TLAN: Partner capability: " );
 439                                 for (i = 5; i <= 10; i++)
 440                                         if (partner & (1 << i)) {
 441                                                 DBG ( "%s", media[i - 5] );
 442                                         }
 443                                 DBG ( "\n" );
 444                         }
 445
 446                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
 447 #ifdef MONITOR
 448                         /* We have link beat..for now anyway */
 449                         priv->link = 1;
 450                         /*Enabling link beat monitoring */
 451                         /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_LINK_BEAT ); */
 452                         mdelay(10000);
 453                         TLan_PhyMonitor(nic);
 454 #endif
 455                 } else if (status & BMSR_LSTATUS) {
 456                         DBG ( "TLAN: %s: Link active\n", priv->nic_name );
 457                         TLan_DioWrite8(BASE, TLAN_LED_REG, TLAN_LED_LINK);
 458                 }
 459         }
 460
 461         if (priv->phyNum == 0) {
 462                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tlphy_ctl);
 463                 tlphy_ctl |= TLAN_TC_INTEN;
 464                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tlphy_ctl);
 465                 sio = TLan_DioRead8(BASE, TLAN_NET_SIO);
 466                 sio |= TLAN_NET_SIO_MINTEN;
 467                 TLan_DioWrite8(BASE, TLAN_NET_SIO, sio);
 468         }
 469
 470         if (status & BMSR_LSTATUS) {
 471                 TLan_SetMac(nic, 0, nic->node_addr);
 472                 priv->phyOnline = 1;
 473                 outb((TLAN_HC_INT_ON >> 8), BASE + TLAN_HOST_CMD + 1);
 474                 outl(virt_to_bus(&rx_ring), BASE + TLAN_CH_PARM);
 475                 outl(TLAN_HC_GO | TLAN_HC_RT, BASE + TLAN_HOST_CMD);
 476         } else {
 477                 DBG
 478                     ( "TLAN: %s: Link inactive, will retry in 10 secs...\n",
 479                      priv->nic_name );
 480                 /* TLan_SetTimer( nic, (10*HZ), TLAN_TIMER_FINISH_RESET ); */
 481                 mdelay(10000);
 482                 TLan_FinishReset(nic);
 483                 return;
 484
 485         }
 486
 487 }       /* TLan_FinishReset */
 488
 489 /**************************************************************************
 490 POLL - Wait for a frame
 491 ***************************************************************************/
 492 static int tlan_poll(struct nic *nic, int retrieve)
 493 {
 494         /* return true if there's an ethernet packet ready to read */
 495         /* nic->packet should contain data on return */
 496         /* nic->packetlen should contain length of data */
 497         u32 framesize;
 498         u32 host_cmd = 0;
 499         u32 ack = 1;
 500         int eoc = 0;
 501         int entry = priv->cur_rx % TLAN_NUM_RX_LISTS;
 502         u16 tmpCStat = le32_to_cpu(rx_ring[entry].cStat);
 503         u16 host_int = inw(BASE + TLAN_HOST_INT);
 504
 505         if ((tmpCStat & TLAN_CSTAT_FRM_CMP) && !retrieve)
 506           return 1;
 507
 508         outw(host_int, BASE + TLAN_HOST_INT);
 509
 510         if (!(tmpCStat & TLAN_CSTAT_FRM_CMP))
 511                 return 0;
 512
 513         /* printf("PI-1: 0x%hX\n", host_int); */
 514         if (tmpCStat & TLAN_CSTAT_EOC)
 515                 eoc = 1;
 516
 517         framesize = rx_ring[entry].frameSize;
 518
 519         nic->packetlen = framesize;
 520
 521         DBG ( ".%d.", (unsigned int) framesize );
 522
 523         memcpy(nic->packet, rxb +
 524                (priv->cur_rx * TLAN_MAX_FRAME_SIZE), nic->packetlen);
 525
 526         rx_ring[entry].cStat = 0;
 527
 528         DBG ( "%d", entry );
 529
 530         entry = (entry + 1) % TLAN_NUM_RX_LISTS;
 531         priv->cur_rx = entry;
 532         if (eoc) {
 533                 if ((rx_ring[entry].cStat & TLAN_CSTAT_READY) ==
 534                     TLAN_CSTAT_READY) {
 535                         ack |= TLAN_HC_GO | TLAN_HC_RT;
 536                         host_cmd = TLAN_HC_ACK | ack | 0x001C0000;
 537                         outl(host_cmd, BASE + TLAN_HOST_CMD);
 538                 }
 539         } else {
 540                 host_cmd = TLAN_HC_ACK | ack | (0x000C0000);
 541                 outl(host_cmd, BASE + TLAN_HOST_CMD);
 542
 543                 DBG ( "AC: 0x%hX\n", inw(BASE + TLAN_CH_PARM) );
 544                 DBG ( "PI-2: 0x%hX\n", inw(BASE + TLAN_HOST_INT) );
 545         }
 546         refill_rx(nic);
 547         return (1);             /* initially as this is called to flush the input */
 548 }
 549
 550 static void refill_rx(struct nic *nic __unused)
 551 {
 552         int entry = 0;
 553
 554         for (;
 555              (priv->cur_rx - priv->dirty_rx +
 556               TLAN_NUM_RX_LISTS) % TLAN_NUM_RX_LISTS > 0;
 557              priv->dirty_rx = (priv->dirty_rx + 1) % TLAN_NUM_RX_LISTS) {
 558                 entry = priv->dirty_rx % TLAN_NUM_TX_LISTS;
 559                 rx_ring[entry].frameSize = TLAN_MAX_FRAME_SIZE;
 560                 rx_ring[entry].cStat = TLAN_CSTAT_READY;
 561         }
 562
 563 }
 564
 565 /**************************************************************************
 566 TRANSMIT - Transmit a frame
 567 ***************************************************************************/
 568 static void tlan_transmit(struct nic *nic, const char *d,       /* Destination */
 569                           unsigned int t,       /* Type */
 570                           unsigned int s,       /* size */
 571                           const char *p)
 572 {                               /* Packet */
 573         u16 nstype;
 574         u32 to;
 575         struct TLanList *tail_list;
 576         struct TLanList *head_list;
 577         u8 *tail_buffer;
 578         u32 ack = 0;
 579         u32 host_cmd;
 580         int eoc = 0;
 581         u16 tmpCStat;
 582         u16 host_int = inw(BASE + TLAN_HOST_INT);
 583
 584         int entry = 0;
 585
 586         DBG ( "INT0-0x%hX\n", host_int );
 587
 588         if (!priv->phyOnline) {
 589                 printf("TRANSMIT:  %s PHY is not ready\n", priv->nic_name);
 590                 return;
 591         }
 592
 593         tail_list = priv->txList + priv->txTail;
 594
 595         if (tail_list->cStat != TLAN_CSTAT_UNUSED) {
 596                 printf("TRANSMIT: %s is busy (Head=%p Tail=%x)\n",
 597                        priv->nic_name, priv->txList, (unsigned int) priv->txTail);
 598                 tx_ring[entry].cStat = TLAN_CSTAT_UNUSED;
 599 //              priv->txBusyCount++;
 600                 return;
 601         }
 602
 603         tail_list->forward = 0;
 604
 605         tail_buffer = txb + (priv->txTail * TLAN_MAX_FRAME_SIZE);
 606
 607         /* send the packet to destination */
 608         memcpy(tail_buffer, d, ETH_ALEN);
 609         memcpy(tail_buffer + ETH_ALEN, nic->node_addr, ETH_ALEN);
 610         nstype = htons((u16) t);
 611         memcpy(tail_buffer + 2 * ETH_ALEN, (u8 *) & nstype, 2);
 612         memcpy(tail_buffer + ETH_HLEN, p, s);
 613
 614         s += ETH_HLEN;
 615         s &= 0x0FFF;
 616         while (s < ETH_ZLEN)
 617                 tail_buffer[s++] = '\0';
 618
 619         /*=====================================================*/
 620         /* Receive
 621          * 0000 0000 0001 1100
 622          * 0000 0000 0000 1100
 623          * 0000 0000 0000 0011 = 0x0003
 624          *
 625          * 0000 0000 0000 0000 0000 0000 0000 0011
 626          * 0000 0000 0000 1100 0000 0000 0000 0000 = 0x000C0000
 627          *
 628          * Transmit
 629          * 0000 0000 0001 1100
 630          * 0000 0000 0000 0100
 631          * 0000 0000 0000 0001 = 0x0001
 632          *
 633          * 0000 0000 0000 0000 0000 0000 0000 0001
 634          * 0000 0000 0000 0100 0000 0000 0000 0000 = 0x00040000
 635          * */
 636
 637         /* Setup the transmit descriptor */
 638         tail_list->frameSize = (u16) s;
 639         tail_list->buffer[0].count = TLAN_LAST_BUFFER | (u32) s;
 640         tail_list->buffer[1].count = 0;
 641         tail_list->buffer[1].address = 0;
 642
 643         tail_list->cStat = TLAN_CSTAT_READY;
 644
 645         DBG ( "INT1-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
 646
 647         if (!priv->txInProgress) {
 648                 priv->txInProgress = 1;
 649                 outl(virt_to_le32desc(tail_list), BASE + TLAN_CH_PARM);
 650                 outl(TLAN_HC_GO, BASE + TLAN_HOST_CMD);
 651         } else {
 652                 if (priv->txTail == 0) {
 653                         DBG ( "Out buffer\n" );
 654                         (priv->txList + (TLAN_NUM_TX_LISTS - 1))->forward =
 655                             virt_to_le32desc(tail_list);
 656                 } else {
 657                         DBG ( "Fix this \n" );
 658                         (priv->txList + (priv->txTail - 1))->forward =
 659                             virt_to_le32desc(tail_list);
 660                 }
 661         }
 662
 663         CIRC_INC(priv->txTail, TLAN_NUM_TX_LISTS);
 664
 665         DBG ( "INT2-0x%hX\n", inw(BASE + TLAN_HOST_INT) );
 666
 667         to = currticks() + TX_TIME_OUT;
 668         while ((tail_list->cStat == TLAN_CSTAT_READY) && currticks() < to);
 669
 670         head_list = priv->txList + priv->txHead;
 671         while (((tmpCStat = head_list->cStat) & TLAN_CSTAT_FRM_CMP)
 672                         && (ack < 255)) {
 673                 ack++;
 674                 if(tmpCStat & TLAN_CSTAT_EOC)
 675                         eoc =1;
 676                 head_list->cStat = TLAN_CSTAT_UNUSED;
 677                 CIRC_INC(priv->txHead, TLAN_NUM_TX_LISTS);
 678                 head_list = priv->txList + priv->txHead;
 679
 680         }
 681         if(!ack)
 682                 printf("Incomplete TX Frame\n");
 683
 684         if(eoc) {
 685                 head_list = priv->txList + priv->txHead;
 686                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
 687                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
 688                         ack |= TLAN_HC_GO;
 689                 } else {
 690                         priv->txInProgress = 0;
 691                 }
 692         }
 693         if(ack) {
 694                 host_cmd = TLAN_HC_ACK | ack;
 695                 outl(host_cmd, BASE + TLAN_HOST_CMD);
 696         }
 697
 698         if(priv->tlanRev < 0x30 ) {
 699                 ack = 1;
 700                 head_list = priv->txList + priv->txHead;
 701                 if ((head_list->cStat & TLAN_CSTAT_READY) == TLAN_CSTAT_READY) {
 702                         outl(virt_to_le32desc(head_list), BASE + TLAN_CH_PARM);
 703                         ack |= TLAN_HC_GO;
 704                 } else {
 705                         priv->txInProgress = 0;
 706                 }
 707                 host_cmd = TLAN_HC_ACK | ack | 0x00140000;
 708                 outl(host_cmd, BASE + TLAN_HOST_CMD);
 709
 710         }
 711
 712         if (currticks() >= to) {
 713                 printf("TX Time Out");
 714         }
 715 }
 716
 717 /**************************************************************************
 718 DISABLE - Turn off ethernet interface
 719 ***************************************************************************/
 720 static void tlan_disable ( struct nic *nic __unused ) {
 721         /* put the card in its initial state */
 722         /* This function serves 3 purposes.
 723          * This disables DMA and interrupts so we don't receive
 724          *  unexpected packets or interrupts from the card after
 725          *  etherboot has finished.
 726          * This frees resources so etherboot may use
 727          *  this driver on another interface
 728          * This allows etherboot to reinitialize the interface
 729          *  if something is something goes wrong.
 730          *
 731          */
 732         outl(TLAN_HC_AD_RST, BASE + TLAN_HOST_CMD);
 733 }
 734
 735 /**************************************************************************
 736 IRQ - Enable, Disable, or Force interrupts
 737 ***************************************************************************/
 738 static void tlan_irq(struct nic *nic __unused, irq_action_t action __unused)
 739 {
 740   switch ( action ) {
 741   case DISABLE :
 742     break;
 743   case ENABLE :
 744     break;
 745   case FORCE :
 746     break;
 747   }
 748 }
 749
 750 static struct nic_operations tlan_operations = {
 751         .connect        = dummy_connect,
 752         .poll           = tlan_poll,
 753         .transmit       = tlan_transmit,
 754         .irq            = tlan_irq,
 755
 756 };
 757
 758 static void TLan_SetMulticastList(struct nic *nic) {
 759         int i;
 760         u8 tmp;
 761
 762         /* !IFF_PROMISC */
 763         tmp = TLan_DioRead8(BASE, TLAN_NET_CMD);
 764         TLan_DioWrite8(BASE, TLAN_NET_CMD, tmp & ~TLAN_NET_CMD_CAF);
 765
 766         /* IFF_ALLMULTI */
 767         for(i = 0; i< 3; i++)
 768                 TLan_SetMac(nic, i + 1, NULL);
 769         TLan_DioWrite32(BASE, TLAN_HASH_1, 0xFFFFFFFF);
 770         TLan_DioWrite32(BASE, TLAN_HASH_2, 0xFFFFFFFF);
 771
 772
 773 }
 774 /**************************************************************************
 775 PROBE - Look for an adapter, this routine's visible to the outside
 776 ***************************************************************************/
 777
 778 #define board_found 1
 779 #define valid_link 0
 780 static int tlan_probe ( struct nic *nic, struct pci_device *pci ) {
 781
 782         u16 data = 0;
 783         int err;
 784         int i;
 785
 786         if (pci->ioaddr == 0)
 787                 return 0;
 788
 789         nic->irqno  = 0;
 790         nic->ioaddr = pci->ioaddr;
 791
 792         BASE = pci->ioaddr;
 793
 794         /* Set nic as PCI bus master */
 795         adjust_pci_device(pci);
 796
 797         /* Point to private storage */
 798         priv = &TLanPrivateInfo;
 799
 800         /* Figure out which chip we're dealing with */
 801         i = 0;
 802         chip_idx = -1;
 803         while (tlan_pci_tbl[i].name) {
 804                 if ((((u32) pci->device << 16) | pci->vendor) ==
 805                     (tlan_pci_tbl[i].id.pci & 0xffffffff)) {
 806                         chip_idx = i;
 807                         break;
 808                 }
 809                 i++;
 810         }
 811
 812         priv->vendor_id = pci->vendor;
 813         priv->dev_id = pci->device;
 814         priv->nic_name = pci->id->name;
 815         priv->eoc = 0;
 816
 817         err = 0;
 818         for (i = 0; i < 6; i++)
 819                 err |= TLan_EeReadByte(BASE,
 820                                        (u8) tlan_pci_tbl[chip_idx].
 821                                        addrOfs + i,
 822                                        (u8 *) & nic->node_addr[i]);
 823         if (err) {
 824             printf ( "TLAN: %s: Error reading MAC from eeprom: %d\n",
 825                     pci->id->name, err);
 826         } else {
 827             DBG ( "%s: %s at ioaddr %#lX, ",
 828                   pci->id->name, eth_ntoa ( nic->node_addr ), pci->ioaddr );
 829         }
 830
 831         priv->tlanRev = TLan_DioRead8(BASE, TLAN_DEF_REVISION);
 832         printf("revision: 0x%hX\n", priv->tlanRev);
 833
 834         TLan_ResetLists(nic);
 835         TLan_ResetAdapter(nic);
 836
 837         data = inl(BASE + TLAN_HOST_CMD);
 838         data |= TLAN_HC_INT_OFF;
 839         outw(data, BASE + TLAN_HOST_CMD);
 840
 841         TLan_SetMulticastList(nic);
 842         udelay(100);
 843         priv->txList = tx_ring;
 844
 845 /*      if (board_found && valid_link)
 846         {*/
 847         /* point to NIC specific routines */
 848         nic->nic_op     = &tlan_operations;
 849         return 1;
 850 }
 851
 852
 853 /*****************************************************************************
 854 ******************************************************************************
 855
 856         ThunderLAN Driver Eeprom routines
 857
 858         The Compaq Netelligent 10 and 10/100 cards use a Microchip 24C02A
 859         EEPROM.  These functions are based on information in Microchip's
 860         data sheet.  I don't know how well this functions will work with
 861         other EEPROMs.
 862
 863 ******************************************************************************
 864 *****************************************************************************/
 865
 866
 867 /***************************************************************
 868 *       TLan_EeSendStart
 869 *
 870 *       Returns:
 871 *               Nothing
 872 *       Parms:
 873 *               io_base         The IO port base address for the
 874 *                               TLAN device with the EEPROM to
 875 *                               use.
 876 *
 877 *       This function sends a start cycle to an EEPROM attached
 878 *       to a TLAN chip.
 879 *
 880 **************************************************************/
 881
 882 void TLan_EeSendStart(u16 io_base)
 883 {
 884         u16 sio;
 885
 886         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
 887         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
 888
 889         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 890         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
 891         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
 892         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
 893         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
 894
 895 }       /* TLan_EeSendStart */
 896
 897 /***************************************************************
 898 *       TLan_EeSendByte
 899 *
 900 *       Returns:
 901 *               If the correct ack was received, 0, otherwise 1
 902 *       Parms:  io_base         The IO port base address for the
 903 *                               TLAN device with the EEPROM to
 904 *                               use.
 905 *               data            The 8 bits of information to
 906 *                               send to the EEPROM.
 907 *               stop            If TLAN_EEPROM_STOP is passed, a
 908 *                               stop cycle is sent after the
 909 *                               byte is sent after the ack is
 910 *                               read.
 911 *
 912 *       This function sends a byte on the serial EEPROM line,
 913 *       driving the clock to send each bit. The function then
 914 *       reverses transmission direction and reads an acknowledge
 915 *       bit.
 916 *
 917 **************************************************************/
 918
 919 int TLan_EeSendByte(u16 io_base, u8 data, int stop)
 920 {
 921         int err;
 922         u8 place;
 923         u16 sio;
 924
 925         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
 926         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
 927
 928         /* Assume clock is low, tx is enabled; */
 929         for (place = 0x80; place != 0; place >>= 1) {
 930                 if (place & data)
 931                         TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
 932                 else
 933                         TLan_ClearBit(TLAN_NET_SIO_EDATA, sio);
 934                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 935                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
 936         }
 937         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
 938         TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 939         err = TLan_GetBit(TLAN_NET_SIO_EDATA, sio);
 940         TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
 941         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
 942
 943         if ((!err) && stop) {
 944                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
 945                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 946                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
 947         }
 948
 949         return (err);
 950
 951 }       /* TLan_EeSendByte */
 952
 953 /***************************************************************
 954 *       TLan_EeReceiveByte
 955 *
 956 *       Returns:
 957 *               Nothing
 958 *       Parms:
 959 *               io_base         The IO port base address for the
 960 *                               TLAN device with the EEPROM to
 961 *                               use.
 962 *               data            An address to a char to hold the
 963 *                               data sent from the EEPROM.
 964 *               stop            If TLAN_EEPROM_STOP is passed, a
 965 *                               stop cycle is sent after the
 966 *                               byte is received, and no ack is
 967 *                               sent.
 968 *
 969 *       This function receives 8 bits of data from the EEPROM
 970 *       over the serial link.  It then sends and ack bit, or no
 971 *       ack and a stop bit.  This function is used to retrieve
 972 *       data after the address of a byte in the EEPROM has been
 973 *       sent.
 974 *
 975 **************************************************************/
 976
 977 void TLan_EeReceiveByte(u16 io_base, u8 * data, int stop)
 978 {
 979         u8 place;
 980         u16 sio;
 981
 982         outw(TLAN_NET_SIO, io_base + TLAN_DIO_ADR);
 983         sio = io_base + TLAN_DIO_DATA + TLAN_NET_SIO;
 984         *data = 0;
 985
 986         /* Assume clock is low, tx is enabled; */
 987         TLan_ClearBit(TLAN_NET_SIO_ETXEN, sio);
 988         for (place = 0x80; place; place >>= 1) {
 989                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 990                 if (TLan_GetBit(TLAN_NET_SIO_EDATA, sio))
 991                         *data |= place;
 992                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
 993         }
 994
 995         TLan_SetBit(TLAN_NET_SIO_ETXEN, sio);
 996         if (!stop) {
 997                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* Ack = 0 */
 998                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
 999                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1000         } else {
1001                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);   /* No ack = 1 (?) */
1002                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1003                 TLan_ClearBit(TLAN_NET_SIO_ECLOK, sio);
1004                 TLan_ClearBit(TLAN_NET_SIO_EDATA, sio); /* STOP, raise data while clock is high */
1005                 TLan_SetBit(TLAN_NET_SIO_ECLOK, sio);
1006                 TLan_SetBit(TLAN_NET_SIO_EDATA, sio);
1007         }
1008
1009 }       /* TLan_EeReceiveByte */
1010
1011 /***************************************************************
1012 *       TLan_EeReadByte
1013 *
1014 *       Returns:
1015 *               No error = 0, else, the stage at which the error
1016 *               occurred.
1017 *       Parms:
1018 *               io_base         The IO port base address for the
1019 *                               TLAN device with the EEPROM to
1020 *                               use.
1021 *               ee_addr         The address of the byte in the
1022 *                               EEPROM whose contents are to be
1023 *                               retrieved.
1024 *               data            An address to a char to hold the
1025 *                               data obtained from the EEPROM.
1026 *
1027 *       This function reads a byte of information from an byte
1028 *       cell in the EEPROM.
1029 *
1030 **************************************************************/
1031
1032 int TLan_EeReadByte(u16 io_base, u8 ee_addr, u8 * data)
1033 {
1034         int err;
1035         int ret = 0;
1036
1037
1038         TLan_EeSendStart(io_base);
1039         err = TLan_EeSendByte(io_base, 0xA0, TLAN_EEPROM_ACK);
1040         if (err) {
1041                 ret = 1;
1042                 goto fail;
1043         }
1044         err = TLan_EeSendByte(io_base, ee_addr, TLAN_EEPROM_ACK);
1045         if (err) {
1046                 ret = 2;
1047                 goto fail;
1048         }
1049         TLan_EeSendStart(io_base);
1050         err = TLan_EeSendByte(io_base, 0xA1, TLAN_EEPROM_ACK);
1051         if (err) {
1052                 ret = 3;
1053                 goto fail;
1054         }
1055         TLan_EeReceiveByte(io_base, data, TLAN_EEPROM_STOP);
1056       fail:
1057
1058         return ret;
1059
1060 }       /* TLan_EeReadByte */
1061
1062
1063 /*****************************************************************************
1064 ******************************************************************************
1065
1066 ThunderLAN Driver MII Routines
1067
1068 These routines are based on the information in Chap. 2 of the
1069 "ThunderLAN Programmer's Guide", pp. 15-24.
1070
1071 ******************************************************************************
1072 *****************************************************************************/
1073
1074
1075 /***************************************************************
1076 *       TLan_MiiReadReg
1077 *
1078 *       Returns:
1079 *               0       if ack received ok
1080 *               1       otherwise.
1081 *
1082 *       Parms:
1083 *               dev             The device structure containing
1084 *                               The io address and interrupt count
1085 *                               for this device.
1086 *               phy             The address of the PHY to be queried.
1087 *               reg             The register whose contents are to be
1088 *                               retrieved.
1089 *               val             A pointer to a variable to store the
1090 *                               retrieved value.
1091 *
1092 *       This function uses the TLAN's MII bus to retrieve the contents
1093 *       of a given register on a PHY.  It sends the appropriate info
1094 *       and then reads the 16-bit register value from the MII bus via
1095 *       the TLAN SIO register.
1096 *
1097 **************************************************************/
1098
1099 int TLan_MiiReadReg(struct nic *nic __unused, u16 phy, u16 reg, u16 * val)
1100 {
1101         u8 nack;
1102         u16 sio, tmp;
1103         u32 i;
1104         int err;
1105         int minten;
1106
1107         err = FALSE;
1108         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1109         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1110
1111         TLan_MiiSync(BASE);
1112
1113         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1114         if (minten)
1115                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1116
1117         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1118         TLan_MiiSendData(BASE, 0x2, 2); /* Read  ( 10b ) */
1119         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1120         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1121
1122
1123         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio); /* Change direction */
1124
1125         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Clock Idle bit */
1126         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1127         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Wait 300ns */
1128
1129         nack = TLan_GetBit(TLAN_NET_SIO_MDATA, sio);    /* Check for ACK */
1130         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);    /* Finish ACK */
1131         if (nack) {             /* No ACK, so fake it */
1132                 for (i = 0; i < 16; i++) {
1133                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1134                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1135                 }
1136                 tmp = 0xffff;
1137                 err = TRUE;
1138         } else {                /* ACK, so read data */
1139                 for (tmp = 0, i = 0x8000; i; i >>= 1) {
1140                         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1141                         if (TLan_GetBit(TLAN_NET_SIO_MDATA, sio))
1142                                 tmp |= i;
1143                         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1144                 }
1145         }
1146
1147
1148         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1149         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1150
1151         if (minten)
1152                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1153
1154         *val = tmp;
1155
1156         return err;
1157
1158 }                               /* TLan_MiiReadReg */
1159
1160 /***************************************************************
1161 *       TLan_MiiSendData
1162 *
1163 *       Returns:
1164 *               Nothing
1165 *       Parms:
1166 *               base_port       The base IO port of the adapter in
1167 *                               question.
1168 *               dev             The address of the PHY to be queried.
1169 *               data            The value to be placed on the MII bus.
1170 *               num_bits        The number of bits in data that are to
1171 *                               be placed on the MII bus.
1172 *
1173 *       This function sends on sequence of bits on the MII
1174 *       configuration bus.
1175 *
1176 **************************************************************/
1177
1178 void TLan_MiiSendData(u16 base_port, u32 data, unsigned num_bits)
1179 {
1180         u16 sio;
1181         u32 i;
1182
1183         if (num_bits == 0)
1184                 return;
1185
1186         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1187         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1188         TLan_SetBit(TLAN_NET_SIO_MTXEN, sio);
1189
1190         for (i = (0x1 << (num_bits - 1)); i; i >>= 1) {
1191                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1192                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1193                 if (data & i)
1194                         TLan_SetBit(TLAN_NET_SIO_MDATA, sio);
1195                 else
1196                         TLan_ClearBit(TLAN_NET_SIO_MDATA, sio);
1197                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1198                 (void) TLan_GetBit(TLAN_NET_SIO_MCLK, sio);
1199         }
1200
1201 }                               /* TLan_MiiSendData */
1202
1203 /***************************************************************
1204 *       TLan_MiiSync
1205 *
1206 *       Returns:
1207 *               Nothing
1208 *       Parms:
1209 *               base_port       The base IO port of the adapter in
1210 *                               question.
1211 *
1212 *       This functions syncs all PHYs in terms of the MII configuration
1213 *       bus.
1214 *
1215 **************************************************************/
1216
1217 void TLan_MiiSync(u16 base_port)
1218 {
1219         int i;
1220         u16 sio;
1221
1222         outw(TLAN_NET_SIO, base_port + TLAN_DIO_ADR);
1223         sio = base_port + TLAN_DIO_DATA + TLAN_NET_SIO;
1224
1225         TLan_ClearBit(TLAN_NET_SIO_MTXEN, sio);
1226         for (i = 0; i < 32; i++) {
1227                 TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);
1228                 TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1229         }
1230
1231 }                               /* TLan_MiiSync */
1232
1233 /***************************************************************
1234 *       TLan_MiiWriteReg
1235 *
1236 *       Returns:
1237 *               Nothing
1238 *       Parms:
1239 *               dev             The device structure for the device
1240 *                               to write to.
1241 *               phy             The address of the PHY to be written to.
1242 *               reg             The register whose contents are to be
1243 *                               written.
1244 *               val             The value to be written to the register.
1245 *
1246 *       This function uses the TLAN's MII bus to write the contents of a
1247 *       given register on a PHY.  It sends the appropriate info and then
1248 *       writes the 16-bit register value from the MII configuration bus
1249 *       via the TLAN SIO register.
1250 *
1251 **************************************************************/
1252
1253 void TLan_MiiWriteReg(struct nic *nic __unused, u16 phy, u16 reg, u16 val)
1254 {
1255         u16 sio;
1256         int minten;
1257
1258         outw(TLAN_NET_SIO, BASE + TLAN_DIO_ADR);
1259         sio = BASE + TLAN_DIO_DATA + TLAN_NET_SIO;
1260
1261         TLan_MiiSync(BASE);
1262
1263         minten = TLan_GetBit(TLAN_NET_SIO_MINTEN, sio);
1264         if (minten)
1265                 TLan_ClearBit(TLAN_NET_SIO_MINTEN, sio);
1266
1267         TLan_MiiSendData(BASE, 0x1, 2); /* Start ( 01b ) */
1268         TLan_MiiSendData(BASE, 0x1, 2); /* Write ( 01b ) */
1269         TLan_MiiSendData(BASE, phy, 5); /* Device #      */
1270         TLan_MiiSendData(BASE, reg, 5); /* Register #    */
1271
1272         TLan_MiiSendData(BASE, 0x2, 2); /* Send ACK */
1273         TLan_MiiSendData(BASE, val, 16);        /* Send Data */
1274
1275         TLan_ClearBit(TLAN_NET_SIO_MCLK, sio);  /* Idle cycle */
1276         TLan_SetBit(TLAN_NET_SIO_MCLK, sio);
1277
1278         if (minten)
1279                 TLan_SetBit(TLAN_NET_SIO_MINTEN, sio);
1280
1281
1282 }                               /* TLan_MiiWriteReg */
1283
1284 /***************************************************************
1285 *       TLan_SetMac
1286 *
1287 *       Returns:
1288 *               Nothing
1289 *       Parms:
1290 *               dev     Pointer to device structure of adapter
1291 *                       on which to change the AREG.
1292 *               areg    The AREG to set the address in (0 - 3).
1293 *               mac     A pointer to an array of chars.  Each
1294 *                       element stores one byte of the address.
1295 *                       IE, it isn't in ascii.
1296 *
1297 *       This function transfers a MAC address to one of the
1298 *       TLAN AREGs (address registers).  The TLAN chip locks
1299 *       the register on writing to offset 0 and unlocks the
1300 *       register after writing to offset 5.  If NULL is passed
1301 *       in mac, then the AREG is filled with 0's.
1302 *
1303 **************************************************************/
1304
1305 void TLan_SetMac(struct nic *nic __unused, int areg, unsigned char *mac)
1306 {
1307         int i;
1308
1309         areg *= 6;
1310
1311         if (mac != NULL) {
1312                 for (i = 0; i < 6; i++)
1313                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i,
1314                                        mac[i]);
1315         } else {
1316                 for (i = 0; i < 6; i++)
1317                         TLan_DioWrite8(BASE, TLAN_AREG_0 + areg + i, 0);
1318         }
1319
1320 }                               /* TLan_SetMac */
1321
1322 /*********************************************************************
1323 *       TLan_PhyDetect
1324 *
1325 *       Returns:
1326 *               Nothing
1327 *       Parms:
1328 *               dev     A pointer to the device structure of the adapter
1329 *                       for which the PHY needs determined.
1330 *
1331 *       So far I've found that adapters which have external PHYs
1332 *       may also use the internal PHY for part of the functionality.
1333 *       (eg, AUI/Thinnet).  This function finds out if this TLAN
1334 *       chip has an internal PHY, and then finds the first external
1335 *       PHY (starting from address 0) if it exists).
1336 *
1337 ********************************************************************/
1338
1339 void TLan_PhyDetect(struct nic *nic)
1340 {
1341         u16 control;
1342         u16 hi;
1343         u16 lo;
1344         u32 phy;
1345
1346         if (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_UNMANAGED_PHY) {
1347                 priv->phyNum = 0xFFFF;
1348                 return;
1349         }
1350
1351         TLan_MiiReadReg(nic, TLAN_PHY_MAX_ADDR, MII_PHYSID1, &hi);
1352
1353         if (hi != 0xFFFF) {
1354                 priv->phy[0] = TLAN_PHY_MAX_ADDR;
1355         } else {
1356                 priv->phy[0] = TLAN_PHY_NONE;
1357         }
1358
1359         priv->phy[1] = TLAN_PHY_NONE;
1360         for (phy = 0; phy <= TLAN_PHY_MAX_ADDR; phy++) {
1361                 TLan_MiiReadReg(nic, phy, MII_BMCR, &control);
1362                 TLan_MiiReadReg(nic, phy, MII_PHYSID1, &hi);
1363                 TLan_MiiReadReg(nic, phy, MII_PHYSID2, &lo);
1364                 if ((control != 0xFFFF) || (hi != 0xFFFF)
1365                     || (lo != 0xFFFF)) {
1366                         printf("PHY found at %hX %hX %hX %hX\n",
1367                                (unsigned int) phy, control, hi, lo);
1368                         if ((priv->phy[1] == TLAN_PHY_NONE)
1369                             && (phy != TLAN_PHY_MAX_ADDR)) {
1370                                 priv->phy[1] = phy;
1371                         }
1372                 }
1373         }
1374
1375         if (priv->phy[1] != TLAN_PHY_NONE) {
1376                 priv->phyNum = 1;
1377         } else if (priv->phy[0] != TLAN_PHY_NONE) {
1378                 priv->phyNum = 0;
1379         } else {
1380                 printf
1381                     ("TLAN:  Cannot initialize device, no PHY was found!\n");
1382         }
1383
1384 }                               /* TLan_PhyDetect */
1385
1386 void TLan_PhyPowerDown(struct nic *nic)
1387 {
1388
1389         u16 value;
1390         DBG ( "%s: Powering down PHY(s).\n", priv->nic_name );
1391         value = BMCR_PDOWN | BMCR_LOOPBACK | BMCR_ISOLATE;
1392         TLan_MiiSync(BASE);
1393         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
1394         if ((priv->phyNum == 0) && (priv->phy[1] != TLAN_PHY_NONE)
1395             &&
1396             (!(tlan_pci_tbl[chip_idx].
1397                flags & TLAN_ADAPTER_USE_INTERN_10))) {
1398                 TLan_MiiSync(BASE);
1399                 TLan_MiiWriteReg(nic, priv->phy[1], MII_BMCR, value);
1400         }
1401
1402         /* Wait for 50 ms and powerup
1403          * This is abitrary.  It is intended to make sure the
1404          * tranceiver settles.
1405          */
1406         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_PUP ); */
1407         mdelay(50);
1408         TLan_PhyPowerUp(nic);
1409
1410 }                               /* TLan_PhyPowerDown */
1411
1412
1413 void TLan_PhyPowerUp(struct nic *nic)
1414 {
1415         u16 value;
1416
1417         DBG ( "%s: Powering up PHY.\n", priv->nic_name );
1418         TLan_MiiSync(BASE);
1419         value = BMCR_LOOPBACK;
1420         TLan_MiiWriteReg(nic, priv->phy[priv->phyNum], MII_BMCR, value);
1421         TLan_MiiSync(BASE);
1422         /* Wait for 500 ms and reset the
1423          * tranceiver.  The TLAN docs say both 50 ms and
1424          * 500 ms, so do the longer, just in case.
1425          */
1426         mdelay(500);
1427         TLan_PhyReset(nic);
1428         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_RESET ); */
1429
1430 }                               /* TLan_PhyPowerUp */
1431
1432 void TLan_PhyReset(struct nic *nic)
1433 {
1434         u16 phy;
1435         u16 value;
1436
1437         phy = priv->phy[priv->phyNum];
1438
1439         DBG ( "%s: Reseting PHY.\n", priv->nic_name );
1440         TLan_MiiSync(BASE);
1441         value = BMCR_LOOPBACK | BMCR_RESET;
1442         TLan_MiiWriteReg(nic, phy, MII_BMCR, value);
1443         TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
1444         while (value & BMCR_RESET) {
1445                 TLan_MiiReadReg(nic, phy, MII_BMCR, &value);
1446         }
1447
1448         /* Wait for 500 ms and initialize.
1449          * I don't remember why I wait this long.
1450          * I've changed this to 50ms, as it seems long enough.
1451          */
1452         /* TLan_SetTimer( dev, (HZ/20), TLAN_TIMER_PHY_START_LINK ); */
1453         mdelay(50);
1454         TLan_PhyStartLink(nic);
1455
1456 }                               /* TLan_PhyReset */
1457
1458
1459 void TLan_PhyStartLink(struct nic *nic)
1460 {
1461
1462         u16 ability;
1463         u16 control;
1464         u16 data;
1465         u16 phy;
1466         u16 status;
1467         u16 tctl;
1468
1469         phy = priv->phy[priv->phyNum];
1470         DBG ( "%s: Trying to activate link.\n", priv->nic_name );
1471         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1472         TLan_MiiReadReg(nic, phy, MII_BMSR, &ability);
1473
1474         if ((status & BMSR_ANEGCAPABLE) && (!priv->aui)) {
1475                 ability = status >> 11;
1476                 if (priv->speed == TLAN_SPEED_10 &&
1477                     priv->duplex == TLAN_DUPLEX_HALF) {
1478                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0000);
1479                 } else if (priv->speed == TLAN_SPEED_10 &&
1480                            priv->duplex == TLAN_DUPLEX_FULL) {
1481                         priv->tlanFullDuplex = TRUE;
1482                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x0100);
1483                 } else if (priv->speed == TLAN_SPEED_100 &&
1484                            priv->duplex == TLAN_DUPLEX_HALF) {
1485                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2000);
1486                 } else if (priv->speed == TLAN_SPEED_100 &&
1487                            priv->duplex == TLAN_DUPLEX_FULL) {
1488                         priv->tlanFullDuplex = TRUE;
1489                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x2100);
1490                 } else {
1491
1492                         /* Set Auto-Neg advertisement */
1493                         TLan_MiiWriteReg(nic, phy, MII_ADVERTISE,
1494                                          (ability << 5) | 1);
1495                         /* Enablee Auto-Neg */
1496                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1000);
1497                         /* Restart Auto-Neg */
1498                         TLan_MiiWriteReg(nic, phy, MII_BMCR, 0x1200);
1499                         /* Wait for 4 sec for autonegotiation
1500                          * to complete.  The max spec time is less than this
1501                          * but the card need additional time to start AN.
1502                          * .5 sec should be plenty extra.
1503                          */
1504                         DBG ( "TLAN: %s: Starting autonegotiation.\n",
1505                                priv->nic_name );
1506                         mdelay(4000);
1507                         TLan_PhyFinishAutoNeg(nic);
1508                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1509                         return;
1510                 }
1511
1512         }
1513
1514         if ((priv->aui) && (priv->phyNum != 0)) {
1515                 priv->phyNum = 0;
1516                 data =
1517                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1518                     TLAN_NET_CFG_PHY_EN;
1519                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1520                 mdelay(50);
1521                 /* TLan_SetTimer( dev, (40*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1522                 TLan_PhyPowerDown(nic);
1523                 return;
1524         } else if (priv->phyNum == 0) {
1525                 control = 0;
1526                 TLan_MiiReadReg(nic, phy, TLAN_TLPHY_CTL, &tctl);
1527                 if (priv->aui) {
1528                         tctl |= TLAN_TC_AUISEL;
1529                 } else {
1530                         tctl &= ~TLAN_TC_AUISEL;
1531                         if (priv->duplex == TLAN_DUPLEX_FULL) {
1532                                 control |= BMCR_FULLDPLX;
1533                                 priv->tlanFullDuplex = TRUE;
1534                         }
1535                         if (priv->speed == TLAN_SPEED_100) {
1536                                 control |= BMCR_SPEED100;
1537                         }
1538                 }
1539                 TLan_MiiWriteReg(nic, phy, MII_BMCR, control);
1540                 TLan_MiiWriteReg(nic, phy, TLAN_TLPHY_CTL, tctl);
1541         }
1542
1543         /* Wait for 2 sec to give the tranceiver time
1544          * to establish link.
1545          */
1546         /* TLan_SetTimer( dev, (4*HZ), TLAN_TIMER_FINISH_RESET ); */
1547         mdelay(2000);
1548         TLan_FinishReset(nic);
1549
1550 }                               /* TLan_PhyStartLink */
1551
1552 void TLan_PhyFinishAutoNeg(struct nic *nic)
1553 {
1554
1555         u16 an_adv;
1556         u16 an_lpa;
1557         u16 data;
1558         u16 mode;
1559         u16 phy;
1560         u16 status;
1561
1562         phy = priv->phy[priv->phyNum];
1563
1564         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1565         udelay(1000);
1566         TLan_MiiReadReg(nic, phy, MII_BMSR, &status);
1567
1568         if (!(status & BMSR_ANEGCOMPLETE)) {
1569                 /* Wait for 8 sec to give the process
1570                  * more time.  Perhaps we should fail after a while.
1571                  */
1572                 if (!priv->neg_be_verbose++) {
1573                         printf
1574                             ("TLAN:  Giving autonegotiation more time.\n");
1575                         printf
1576                             ("TLAN:  Please check that your adapter has\n");
1577                         printf
1578                             ("TLAN:  been properly connected to a HUB or Switch.\n");
1579                         printf
1580                             ("TLAN:  Trying to establish link in the background...\n");
1581                 }
1582                 mdelay(8000);
1583                 TLan_PhyFinishAutoNeg(nic);
1584                 /* TLan_SetTimer( dev, (8*HZ), TLAN_TIMER_PHY_FINISH_AN ); */
1585                 return;
1586         }
1587
1588         DBG ( "TLAN: %s: Autonegotiation complete.\n", priv->nic_name );
1589         TLan_MiiReadReg(nic, phy, MII_ADVERTISE, &an_adv);
1590         TLan_MiiReadReg(nic, phy, MII_LPA, &an_lpa);
1591         mode = an_adv & an_lpa & 0x03E0;
1592         if (mode & 0x0100) {
1593                 printf("Full Duplex\n");
1594                 priv->tlanFullDuplex = TRUE;
1595         } else if (!(mode & 0x0080) && (mode & 0x0040)) {
1596                 priv->tlanFullDuplex = TRUE;
1597                 printf("Full Duplex\n");
1598         }
1599
1600         if ((!(mode & 0x0180))
1601             && (tlan_pci_tbl[chip_idx].flags & TLAN_ADAPTER_USE_INTERN_10)
1602             && (priv->phyNum != 0)) {
1603                 priv->phyNum = 0;
1604                 data =
1605                     TLAN_NET_CFG_1FRAG | TLAN_NET_CFG_1CHAN |
1606                     TLAN_NET_CFG_PHY_EN;
1607                 TLan_DioWrite16(BASE, TLAN_NET_CONFIG, data);
1608                 /* TLan_SetTimer( nic, (400*HZ/1000), TLAN_TIMER_PHY_PDOWN ); */
1609                 mdelay(400);
1610                 TLan_PhyPowerDown(nic);
1611                 return;
1612         }
1613
1614         if (priv->phyNum == 0) {
1615                 if ((priv->duplex == TLAN_DUPLEX_FULL)
1616                     || (an_adv & an_lpa & 0x0040)) {
1617                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
1618                                          BMCR_ANENABLE | BMCR_FULLDPLX);
1619                         DBG
1620                             ( "TLAN:  Starting internal PHY with FULL-DUPLEX\n" );
1621                 } else {
1622                         TLan_MiiWriteReg(nic, phy, MII_BMCR,
1623                                          BMCR_ANENABLE);
1624                         DBG
1625                             ( "TLAN:  Starting internal PHY with HALF-DUPLEX\n" );
1626                 }
1627         }
1628
1629         /* Wait for 100 ms.  No reason in partiticular.
1630          */
1631         /* TLan_SetTimer( dev, (HZ/10), TLAN_TIMER_FINISH_RESET ); */
1632         mdelay(100);
1633         TLan_FinishReset(nic);
1634
1635 }                               /* TLan_PhyFinishAutoNeg */
1636
1637 #ifdef MONITOR
1638
1639 /*********************************************************************
1640 *
1641 *      TLan_phyMonitor
1642 *
1643 *      Returns:
1644 *              None
1645 *
1646 *      Params:
1647 *              dev             The device structure of this device.
1648 *
1649 *
1650 *      This function monitors PHY condition by reading the status
1651 *      register via the MII bus. This can be used to give info
1652 *      about link changes (up/down), and possible switch to alternate
1653 *      media.
1654 *
1655 ********************************************************************/
1656
1657 void TLan_PhyMonitor(struct net_device *dev)
1658 {
1659         TLanPrivateInfo *priv = dev->priv;
1660         u16 phy;
1661         u16 phy_status;
1662
1663         phy = priv->phy[priv->phyNum];
1664
1665         /* Get PHY status register */
1666         TLan_MiiReadReg(nic, phy, MII_BMSR, &phy_status);
1667
1668         /* Check if link has been lost */
1669         if (!(phy_status & BMSR_LSTATUS)) {
1670                 if (priv->link) {
1671                         priv->link = 0;
1672                         printf("TLAN: %s has lost link\n", priv->nic_name);
1673                         priv->flags &= ~IFF_RUNNING;
1674                         mdelay(2000);
1675                         TLan_PhyMonitor(nic);
1676                         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1677                         return;
1678                 }
1679         }
1680
1681         /* Link restablished? */
1682         if ((phy_status & BMSR_LSTATUS) && !priv->link) {
1683                 priv->link = 1;
1684                 printf("TLAN: %s has reestablished link\n",
1685                        priv->nic_name);
1686                 priv->flags |= IFF_RUNNING;
1687         }
1688
1689         /* Setup a new monitor */
1690         /* TLan_SetTimer( dev, (2*HZ), TLAN_TIMER_LINK_BEAT ); */
1691         mdelay(2000);
1692         TLan_PhyMonitor(nic);
1693 }
1694
1695 #endif                          /* MONITOR */
1696
1697 static struct pci_device_id tlan_nics[] = {
1698         PCI_ROM(0x0e11, 0xae34, "netel10", "Compaq Netelligent 10 T PCI UTP", 0),
1699         PCI_ROM(0x0e11, 0xae32, "netel100","Compaq Netelligent 10/100 TX PCI UTP", 0),
1700         PCI_ROM(0x0e11, 0xae35, "netflex3i", "Compaq Integrated NetFlex-3/P", 0),
1701         PCI_ROM(0x0e11, 0xf130, "thunder", "Compaq NetFlex-3/P", 0),
1702         PCI_ROM(0x0e11, 0xf150, "netflex3b", "Compaq NetFlex-3/P", 0),
1703         PCI_ROM(0x0e11, 0xae43, "netel100pi", "Compaq Netelligent Integrated 10/100 TX UTP", 0),
1704         PCI_ROM(0x0e11, 0xae40, "netel100d", "Compaq Netelligent Dual 10/100 TX PCI UTP", 0),
1705         PCI_ROM(0x0e11, 0xb011, "netel100i", "Compaq Netelligent 10/100 TX Embedded UTP", 0),
1706         PCI_ROM(0x108d, 0x0013, "oc2183", "Olicom OC-2183/2185", 0),
1707         PCI_ROM(0x108d, 0x0012, "oc2325", "Olicom OC-2325", 0),
1708         PCI_ROM(0x108d, 0x0014, "oc2326", "Olicom OC-2326", 0),
1709         PCI_ROM(0x0e11, 0xb030, "netelligent_10_100_ws_5100", "Compaq Netelligent 10/100 TX UTP", 0),
1710         PCI_ROM(0x0e11, 0xb012, "netelligent_10_t2", "Compaq Netelligent 10 T/2 PCI UTP/Coax", 0),
1711 };
1712
1713 PCI_DRIVER ( tlan_driver, tlan_nics, PCI_NO_CLASS );
1714
1715 DRIVER ( "TLAN/PCI", nic_driver, pci_driver, tlan_driver,
1716          tlan_probe, tlan_disable );
1717
1718 /*
1719  * Local variables:
1720  *  c-basic-offset: 8
1721  *  c-indent-level: 8
1722  *  tab-width: 8
1723  * End:
1724  */