qemu/roms/ipxe/src/drivers/net/tg3/tg3_phy.c

   1
   2 #include <mii.h>
   3 #include <stdio.h>
   4 #include <errno.h>
   5 #include <unistd.h>
   6 #include <byteswap.h>
   7 #include <ipxe/pci.h>
   8
   9 #include "tg3.h"
  10
  11 static void tg3_link_report(struct tg3 *tp);
  12
  13 void tg3_mdio_init(struct tg3 *tp)
  14 {       DBGP("%s\n", __func__);
  15
  16         if (tg3_flag(tp, 5717_PLUS)) {
  17                 u32 is_serdes;
  18
  19                 tp->phy_addr = PCI_FUNC(tp->pdev->busdevfn) + 1;
  20
  21                 if (tp->pci_chip_rev_id != CHIPREV_ID_5717_A0)
  22                         is_serdes = tr32(SG_DIG_STATUS) & SG_DIG_IS_SERDES;
  23                 else
  24                         is_serdes = tr32(TG3_CPMU_PHY_STRAP) &
  25                                     TG3_CPMU_PHY_STRAP_IS_SERDES;
  26                 if (is_serdes)
  27                         tp->phy_addr += 7;
  28         } else
  29                 tp->phy_addr = TG3_PHY_MII_ADDR;
  30 }
  31
  32 static int tg3_issue_otp_command(struct tg3 *tp, u32 cmd)
  33 {       DBGP("%s\n", __func__);
  34
  35         int i;
  36         u32 val;
  37
  38         tw32(OTP_CTRL, cmd | OTP_CTRL_OTP_CMD_START);
  39         tw32(OTP_CTRL, cmd);
  40
  41         /* Wait for up to 1 ms for command to execute. */
  42         for (i = 0; i < 100; i++) {
  43                 val = tr32(OTP_STATUS);
  44                 if (val & OTP_STATUS_CMD_DONE)
  45                         break;
  46                 udelay(10);
  47         }
  48
  49         return (val & OTP_STATUS_CMD_DONE) ? 0 : -EBUSY;
  50 }
  51
  52 /* Read the gphy configuration from the OTP region of the chip.  The gphy
  53  * configuration is a 32-bit value that straddles the alignment boundary.
  54  * We do two 32-bit reads and then shift and merge the results.
  55  */
  56 u32 tg3_read_otp_phycfg(struct tg3 *tp)
  57 {       DBGP("%s\n", __func__);
  58
  59         u32 bhalf_otp, thalf_otp;
  60
  61         tw32(OTP_MODE, OTP_MODE_OTP_THRU_GRC);
  62
  63         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_INIT))
  64                 return 0;
  65
  66         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC1);
  67
  68         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  69                 return 0;
  70
  71         thalf_otp = tr32(OTP_READ_DATA);
  72
  73         tw32(OTP_ADDRESS, OTP_ADDRESS_MAGIC2);
  74
  75         if (tg3_issue_otp_command(tp, OTP_CTRL_OTP_CMD_READ))
  76                 return 0;
  77
  78         bhalf_otp = tr32(OTP_READ_DATA);
  79
  80         return ((thalf_otp & 0x0000ffff) << 16) | (bhalf_otp >> 16);
  81 }
  82
  83 #define PHY_BUSY_LOOPS  5000
  84
  85 int tg3_readphy(struct tg3 *tp, int reg, u32 *val)
  86 {       DBGP("%s\n", __func__);
  87
  88         u32 frame_val;
  89         unsigned int loops;
  90         int ret;
  91
  92         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
  93                 tw32_f(MAC_MI_MODE,
  94                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
  95                 udelay(80);
  96         }
  97
  98         *val = 0x0;
  99
 100         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 101                       MI_COM_PHY_ADDR_MASK);
 102         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 103                       MI_COM_REG_ADDR_MASK);
 104         frame_val |= (MI_COM_CMD_READ | MI_COM_START);
 105
 106         tw32_f(MAC_MI_COM, frame_val);
 107
 108         loops = PHY_BUSY_LOOPS;
 109         while (loops != 0) {
 110                 udelay(10);
 111                 frame_val = tr32(MAC_MI_COM);
 112
 113                 if ((frame_val & MI_COM_BUSY) == 0) {
 114                         udelay(5);
 115                         frame_val = tr32(MAC_MI_COM);
 116                         break;
 117                 }
 118                 loops -= 1;
 119         }
 120
 121         ret = -EBUSY;
 122         if (loops != 0) {
 123                 *val = frame_val & MI_COM_DATA_MASK;
 124                 ret = 0;
 125         }
 126
 127         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 128                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 129                 udelay(80);
 130         }
 131
 132         return ret;
 133 }
 134
 135 struct subsys_tbl_ent {
 136         u16 subsys_vendor, subsys_devid;
 137         u32 phy_id;
 138 };
 139
 140 static struct subsys_tbl_ent subsys_id_to_phy_id[] = {
 141         /* Broadcom boards. */
 142         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 143           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6, TG3_PHY_ID_BCM5401 },
 144         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 145           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5, TG3_PHY_ID_BCM5701 },
 146         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 147           TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6, TG3_PHY_ID_BCM8002 },
 148         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 149           TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9, 0 },
 150         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 151           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1, TG3_PHY_ID_BCM5701 },
 152         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 153           TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8, TG3_PHY_ID_BCM5701 },
 154         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 155           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7, 0 },
 156         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 157           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10, TG3_PHY_ID_BCM5701 },
 158         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 159           TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12, TG3_PHY_ID_BCM5701 },
 160         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 161           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1, TG3_PHY_ID_BCM5703 },
 162         { TG3PCI_SUBVENDOR_ID_BROADCOM,
 163           TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2, TG3_PHY_ID_BCM5703 },
 164
 165         /* 3com boards. */
 166         { TG3PCI_SUBVENDOR_ID_3COM,
 167           TG3PCI_SUBDEVICE_ID_3COM_3C996T, TG3_PHY_ID_BCM5401 },
 168         { TG3PCI_SUBVENDOR_ID_3COM,
 169           TG3PCI_SUBDEVICE_ID_3COM_3C996BT, TG3_PHY_ID_BCM5701 },
 170         { TG3PCI_SUBVENDOR_ID_3COM,
 171           TG3PCI_SUBDEVICE_ID_3COM_3C996SX, 0 },
 172         { TG3PCI_SUBVENDOR_ID_3COM,
 173           TG3PCI_SUBDEVICE_ID_3COM_3C1000T, TG3_PHY_ID_BCM5701 },
 174         { TG3PCI_SUBVENDOR_ID_3COM,
 175           TG3PCI_SUBDEVICE_ID_3COM_3C940BR01, TG3_PHY_ID_BCM5701 },
 176
 177         /* DELL boards. */
 178         { TG3PCI_SUBVENDOR_ID_DELL,
 179           TG3PCI_SUBDEVICE_ID_DELL_VIPER, TG3_PHY_ID_BCM5401 },
 180         { TG3PCI_SUBVENDOR_ID_DELL,
 181           TG3PCI_SUBDEVICE_ID_DELL_JAGUAR, TG3_PHY_ID_BCM5401 },
 182         { TG3PCI_SUBVENDOR_ID_DELL,
 183           TG3PCI_SUBDEVICE_ID_DELL_MERLOT, TG3_PHY_ID_BCM5411 },
 184         { TG3PCI_SUBVENDOR_ID_DELL,
 185           TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT, TG3_PHY_ID_BCM5411 },
 186
 187         /* Compaq boards. */
 188         { TG3PCI_SUBVENDOR_ID_COMPAQ,
 189           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE, TG3_PHY_ID_BCM5701 },
 190         { TG3PCI_SUBVENDOR_ID_COMPAQ,
 191           TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2, TG3_PHY_ID_BCM5701 },
 192         { TG3PCI_SUBVENDOR_ID_COMPAQ,
 193           TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING, 0 },
 194         { TG3PCI_SUBVENDOR_ID_COMPAQ,
 195           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780, TG3_PHY_ID_BCM5701 },
 196         { TG3PCI_SUBVENDOR_ID_COMPAQ,
 197           TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2, TG3_PHY_ID_BCM5701 },
 198
 199         /* IBM boards. */
 200         { TG3PCI_SUBVENDOR_ID_IBM,
 201           TG3PCI_SUBDEVICE_ID_IBM_5703SAX2, 0 }
 202 };
 203
 204 static struct subsys_tbl_ent *tg3_lookup_by_subsys(struct tg3 *tp)
 205 {       DBGP("%s\n", __func__);
 206
 207         int i;
 208
 209         DBGC(tp->dev, "Matching with: %x:%x\n", tp->subsystem_vendor, tp->subsystem_device);
 210
 211         for (i = 0; i < (int) ARRAY_SIZE(subsys_id_to_phy_id); i++) {
 212                 if ((subsys_id_to_phy_id[i].subsys_vendor ==
 213                      tp->subsystem_vendor) &&
 214                     (subsys_id_to_phy_id[i].subsys_devid ==
 215                      tp->subsystem_device))
 216                         return &subsys_id_to_phy_id[i];
 217         }
 218         return NULL;
 219 }
 220
 221 int tg3_writephy(struct tg3 *tp, int reg, u32 val)
 222 {       DBGP("%s\n", __func__);
 223
 224         u32 frame_val;
 225         unsigned int loops;
 226         int ret;
 227
 228         if ((tp->phy_flags & TG3_PHYFLG_IS_FET) &&
 229             (reg == MII_TG3_CTRL || reg == MII_TG3_AUX_CTRL))
 230                 return 0;
 231
 232         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 233                 tw32_f(MAC_MI_MODE,
 234                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
 235                 udelay(80);
 236         }
 237
 238         frame_val  = ((tp->phy_addr << MI_COM_PHY_ADDR_SHIFT) &
 239                       MI_COM_PHY_ADDR_MASK);
 240         frame_val |= ((reg << MI_COM_REG_ADDR_SHIFT) &
 241                       MI_COM_REG_ADDR_MASK);
 242         frame_val |= (val & MI_COM_DATA_MASK);
 243         frame_val |= (MI_COM_CMD_WRITE | MI_COM_START);
 244
 245         tw32_f(MAC_MI_COM, frame_val);
 246
 247         loops = PHY_BUSY_LOOPS;
 248         while (loops != 0) {
 249                 udelay(10);
 250                 frame_val = tr32(MAC_MI_COM);
 251                 if ((frame_val & MI_COM_BUSY) == 0) {
 252                         udelay(5);
 253                         frame_val = tr32(MAC_MI_COM);
 254                         break;
 255                 }
 256                 loops -= 1;
 257         }
 258
 259         ret = -EBUSY;
 260         if (loops != 0)
 261                 ret = 0;
 262
 263         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
 264                 tw32_f(MAC_MI_MODE, tp->mi_mode);
 265                 udelay(80);
 266         }
 267
 268         return ret;
 269 }
 270
 271 static int tg3_bmcr_reset(struct tg3 *tp)
 272 {       DBGP("%s\n", __func__);
 273
 274         u32 phy_control;
 275         int limit, err;
 276
 277         /* OK, reset it, and poll the BMCR_RESET bit until it
 278          * clears or we time out.
 279          */
 280         phy_control = BMCR_RESET;
 281         err = tg3_writephy(tp, MII_BMCR, phy_control);
 282         if (err != 0)
 283                 return -EBUSY;
 284
 285         limit = 5000;
 286         while (limit--) {
 287                 err = tg3_readphy(tp, MII_BMCR, &phy_control);
 288                 if (err != 0)
 289                         return -EBUSY;
 290
 291                 if ((phy_control & BMCR_RESET) == 0) {
 292                         udelay(40);
 293                         break;
 294                 }
 295                 udelay(10);
 296         }
 297         if (limit < 0)
 298                 return -EBUSY;
 299
 300         return 0;
 301 }
 302
 303 static int tg3_wait_macro_done(struct tg3 *tp)
 304 {       DBGP("%s\n", __func__);
 305
 306         int limit = 100;
 307
 308         while (limit--) {
 309                 u32 tmp32;
 310
 311                 if (!tg3_readphy(tp, MII_TG3_DSP_CONTROL, &tmp32)) {
 312                         if ((tmp32 & 0x1000) == 0)
 313                                 break;
 314                 }
 315         }
 316         if (limit < 0)
 317                 return -EBUSY;
 318
 319         return 0;
 320 }
 321
 322 static int tg3_phy_write_and_check_testpat(struct tg3 *tp, int *resetp)
 323 {       DBGP("%s\n", __func__);
 324
 325         static const u32 test_pat[4][6] = {
 326         { 0x00005555, 0x00000005, 0x00002aaa, 0x0000000a, 0x00003456, 0x00000003 },
 327         { 0x00002aaa, 0x0000000a, 0x00003333, 0x00000003, 0x0000789a, 0x00000005 },
 328         { 0x00005a5a, 0x00000005, 0x00002a6a, 0x0000000a, 0x00001bcd, 0x00000003 },
 329         { 0x00002a5a, 0x0000000a, 0x000033c3, 0x00000003, 0x00002ef1, 0x00000005 }
 330         };
 331         int chan;
 332
 333         for (chan = 0; chan < 4; chan++) {
 334                 int i;
 335
 336                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 337                              (chan * 0x2000) | 0x0200);
 338                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
 339
 340                 for (i = 0; i < 6; i++)
 341                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT,
 342                                      test_pat[chan][i]);
 343
 344                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
 345                 if (tg3_wait_macro_done(tp)) {
 346                         *resetp = 1;
 347                         return -EBUSY;
 348                 }
 349
 350                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 351                              (chan * 0x2000) | 0x0200);
 352                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0082);
 353                 if (tg3_wait_macro_done(tp)) {
 354                         *resetp = 1;
 355                         return -EBUSY;
 356                 }
 357
 358                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0802);
 359                 if (tg3_wait_macro_done(tp)) {
 360                         *resetp = 1;
 361                         return -EBUSY;
 362                 }
 363
 364                 for (i = 0; i < 6; i += 2) {
 365                         u32 low, high;
 366
 367                         if (tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &low) ||
 368                             tg3_readphy(tp, MII_TG3_DSP_RW_PORT, &high) ||
 369                             tg3_wait_macro_done(tp)) {
 370                                 *resetp = 1;
 371                                 return -EBUSY;
 372                         }
 373                         low &= 0x7fff;
 374                         high &= 0x000f;
 375                         if (low != test_pat[chan][i] ||
 376                             high != test_pat[chan][i+1]) {
 377                                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000b);
 378                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4001);
 379                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x4005);
 380
 381                                 return -EBUSY;
 382                         }
 383                 }
 384         }
 385
 386         return 0;
 387 }
 388
 389 static int tg3_phy_reset_chanpat(struct tg3 *tp)
 390 {       DBGP("%s\n", __func__);
 391
 392         int chan;
 393
 394         for (chan = 0; chan < 4; chan++) {
 395                 int i;
 396
 397                 tg3_writephy(tp, MII_TG3_DSP_ADDRESS,
 398                              (chan * 0x2000) | 0x0200);
 399                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0002);
 400                 for (i = 0; i < 6; i++)
 401                         tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x000);
 402                 tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0202);
 403                 if (tg3_wait_macro_done(tp))
 404                         return -EBUSY;
 405         }
 406
 407         return 0;
 408 }
 409
 410 static int tg3_phydsp_write(struct tg3 *tp, u32 reg, u32 val)
 411 {       DBGP("%s\n", __func__);
 412
 413         int err;
 414
 415         err = tg3_writephy(tp, MII_TG3_DSP_ADDRESS, reg);
 416         if (!err)
 417                 err = tg3_writephy(tp, MII_TG3_DSP_RW_PORT, val);
 418
 419         return err;
 420 }
 421
 422 static int tg3_phy_auxctl_write(struct tg3 *tp, int reg, u32 set)
 423 {       DBGP("%s\n", __func__);
 424
 425         if (reg == MII_TG3_AUXCTL_SHDWSEL_MISC)
 426                 set |= MII_TG3_AUXCTL_MISC_WREN;
 427
 428         return tg3_writephy(tp, MII_TG3_AUX_CTRL, set | reg);
 429 }
 430
 431 #define TG3_PHY_AUXCTL_SMDSP_ENABLE(tp) \
 432         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
 433                              MII_TG3_AUXCTL_ACTL_SMDSP_ENA | \
 434                              MII_TG3_AUXCTL_ACTL_TX_6DB)
 435
 436 #define TG3_PHY_AUXCTL_SMDSP_DISABLE(tp) \
 437         tg3_phy_auxctl_write((tp), MII_TG3_AUXCTL_SHDWSEL_AUXCTL, \
 438                              MII_TG3_AUXCTL_ACTL_TX_6DB);
 439
 440 static int tg3_phy_reset_5703_4_5(struct tg3 *tp)
 441 {       DBGP("%s\n", __func__);
 442
 443         u32 reg32, phy9_orig;
 444         int retries, do_phy_reset, err;
 445
 446         retries = 10;
 447         do_phy_reset = 1;
 448         do {
 449                 if (do_phy_reset) {
 450                         err = tg3_bmcr_reset(tp);
 451                         if (err)
 452                                 return err;
 453                         do_phy_reset = 0;
 454                 }
 455
 456                 /* Disable transmitter and interrupt.  */
 457                 if (tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32))
 458                         continue;
 459
 460                 reg32 |= 0x3000;
 461                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 462
 463                 /* Set full-duplex, 1000 mbps.  */
 464                 tg3_writephy(tp, MII_BMCR,
 465                              BMCR_FULLDPLX | TG3_BMCR_SPEED1000);
 466
 467                 /* Set to master mode.  */
 468                 if (tg3_readphy(tp, MII_TG3_CTRL, &phy9_orig))
 469                         continue;
 470
 471                 tg3_writephy(tp, MII_TG3_CTRL,
 472                              (MII_TG3_CTRL_AS_MASTER |
 473                               MII_TG3_CTRL_ENABLE_AS_MASTER));
 474
 475                 err = TG3_PHY_AUXCTL_SMDSP_ENABLE(tp);
 476                 if (err)
 477                         return err;
 478
 479                 /* Block the PHY control access.  */
 480                 tg3_phydsp_write(tp, 0x8005, 0x0800);
 481
 482                 err = tg3_phy_write_and_check_testpat(tp, &do_phy_reset);
 483                 if (!err)
 484                         break;
 485         } while (--retries);
 486
 487         err = tg3_phy_reset_chanpat(tp);
 488         if (err)
 489                 return err;
 490
 491         tg3_phydsp_write(tp, 0x8005, 0x0000);
 492
 493         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x8200);
 494         tg3_writephy(tp, MII_TG3_DSP_CONTROL, 0x0000);
 495
 496         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 497
 498         tg3_writephy(tp, MII_TG3_CTRL, phy9_orig);
 499
 500         if (!tg3_readphy(tp, MII_TG3_EXT_CTRL, &reg32)) {
 501                 reg32 &= ~0x3000;
 502                 tg3_writephy(tp, MII_TG3_EXT_CTRL, reg32);
 503         } else if (!err)
 504                 err = -EBUSY;
 505
 506         return err;
 507 }
 508
 509 static void tg3_phy_apply_otp(struct tg3 *tp)
 510 {       DBGP("%s\n", __func__);
 511
 512         u32 otp, phy;
 513
 514         if (!tp->phy_otp)
 515                 return;
 516
 517         otp = tp->phy_otp;
 518
 519         if (TG3_PHY_AUXCTL_SMDSP_ENABLE(tp))
 520                 return;
 521
 522         phy = ((otp & TG3_OTP_AGCTGT_MASK) >> TG3_OTP_AGCTGT_SHIFT);
 523         phy |= MII_TG3_DSP_TAP1_AGCTGT_DFLT;
 524         tg3_phydsp_write(tp, MII_TG3_DSP_TAP1, phy);
 525
 526         phy = ((otp & TG3_OTP_HPFFLTR_MASK) >> TG3_OTP_HPFFLTR_SHIFT) |
 527               ((otp & TG3_OTP_HPFOVER_MASK) >> TG3_OTP_HPFOVER_SHIFT);
 528         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH0, phy);
 529
 530         phy = ((otp & TG3_OTP_LPFDIS_MASK) >> TG3_OTP_LPFDIS_SHIFT);
 531         phy |= MII_TG3_DSP_AADJ1CH3_ADCCKADJ;
 532         tg3_phydsp_write(tp, MII_TG3_DSP_AADJ1CH3, phy);
 533
 534         phy = ((otp & TG3_OTP_VDAC_MASK) >> TG3_OTP_VDAC_SHIFT);
 535         tg3_phydsp_write(tp, MII_TG3_DSP_EXP75, phy);
 536
 537         phy = ((otp & TG3_OTP_10BTAMP_MASK) >> TG3_OTP_10BTAMP_SHIFT);
 538         tg3_phydsp_write(tp, MII_TG3_DSP_EXP96, phy);
 539
 540         phy = ((otp & TG3_OTP_ROFF_MASK) >> TG3_OTP_ROFF_SHIFT) |
 541               ((otp & TG3_OTP_RCOFF_MASK) >> TG3_OTP_RCOFF_SHIFT);
 542         tg3_phydsp_write(tp, MII_TG3_DSP_EXP97, phy);
 543
 544         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 545 }
 546
 547 static int tg3_phy_auxctl_read(struct tg3 *tp, int reg, u32 *val)
 548 {       DBGP("%s\n", __func__);
 549
 550         int err;
 551
 552         err = tg3_writephy(tp, MII_TG3_AUX_CTRL,
 553                            (reg << MII_TG3_AUXCTL_MISC_RDSEL_SHIFT) |
 554                            MII_TG3_AUXCTL_SHDWSEL_MISC);
 555         if (!err)
 556                 err = tg3_readphy(tp, MII_TG3_AUX_CTRL, val);
 557
 558         return err;
 559 }
 560
 561 static void tg3_phy_toggle_automdix(struct tg3 *tp, int enable)
 562 {       DBGP("%s\n", __func__);
 563
 564         u32 phy;
 565
 566         if (!tg3_flag(tp, 5705_PLUS) ||
 567             (tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
 568                 return;
 569
 570         if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
 571                 u32 ephy;
 572
 573                 if (!tg3_readphy(tp, MII_TG3_FET_TEST, &ephy)) {
 574                         u32 reg = MII_TG3_FET_SHDW_MISCCTRL;
 575
 576                         tg3_writephy(tp, MII_TG3_FET_TEST,
 577                                      ephy | MII_TG3_FET_SHADOW_EN);
 578                         if (!tg3_readphy(tp, reg, &phy)) {
 579                                 if (enable)
 580                                         phy |= MII_TG3_FET_SHDW_MISCCTRL_MDIX;
 581                                 else
 582                                         phy &= ~MII_TG3_FET_SHDW_MISCCTRL_MDIX;
 583                                 tg3_writephy(tp, reg, phy);
 584                         }
 585                         tg3_writephy(tp, MII_TG3_FET_TEST, ephy);
 586                 }
 587         } else {
 588                 int ret;
 589
 590                 ret = tg3_phy_auxctl_read(tp,
 591                                           MII_TG3_AUXCTL_SHDWSEL_MISC, &phy);
 592                 if (!ret) {
 593                         if (enable)
 594                                 phy |= MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 595                         else
 596                                 phy &= ~MII_TG3_AUXCTL_MISC_FORCE_AMDIX;
 597                         tg3_phy_auxctl_write(tp,
 598                                              MII_TG3_AUXCTL_SHDWSEL_MISC, phy);
 599                 }
 600         }
 601 }
 602
 603 static void tg3_phy_set_wirespeed(struct tg3 *tp)
 604 {       DBGP("%s\n", __func__);
 605
 606         int ret;
 607         u32 val;
 608
 609         if (tp->phy_flags & TG3_PHYFLG_NO_ETH_WIRE_SPEED)
 610                 return;
 611
 612         ret = tg3_phy_auxctl_read(tp, MII_TG3_AUXCTL_SHDWSEL_MISC, &val);
 613         if (!ret)
 614                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_MISC,
 615                                      val | MII_TG3_AUXCTL_MISC_WIRESPD_EN);
 616 }
 617
 618 /* This will reset the tigon3 PHY if there is no valid
 619  * link unless the FORCE argument is non-zero.
 620  */
 621 int tg3_phy_reset(struct tg3 *tp)
 622 {       DBGP("%s\n", __func__);
 623
 624         u32 val, cpmuctrl;
 625         int err;
 626
 627         DBGCP(&tp->pdev->dev, "%s\n", __func__);
 628
 629         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 630                 val = tr32(GRC_MISC_CFG);
 631                 tw32_f(GRC_MISC_CFG, val & ~GRC_MISC_CFG_EPHY_IDDQ);
 632                 udelay(40);
 633         }
 634         err  = tg3_readphy(tp, MII_BMSR, &val);
 635         err |= tg3_readphy(tp, MII_BMSR, &val);
 636         if (err != 0)
 637                 return -EBUSY;
 638
 639         netdev_link_down(tp->dev);
 640         tg3_link_report(tp);
 641
 642         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
 643             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
 644             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) {
 645                 err = tg3_phy_reset_5703_4_5(tp);
 646                 if (err)
 647                         return err;
 648                 goto out;
 649         }
 650
 651         cpmuctrl = 0;
 652         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5784 &&
 653             GET_CHIP_REV(tp->pci_chip_rev_id) != CHIPREV_5784_AX) {
 654                 cpmuctrl = tr32(TG3_CPMU_CTRL);
 655                 if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY)
 656                         tw32(TG3_CPMU_CTRL,
 657                              cpmuctrl & ~CPMU_CTRL_GPHY_10MB_RXONLY);
 658         }
 659
 660         err = tg3_bmcr_reset(tp);
 661         if (err)
 662                 return err;
 663
 664         if (cpmuctrl & CPMU_CTRL_GPHY_10MB_RXONLY) {
 665                 val = MII_TG3_DSP_EXP8_AEDW | MII_TG3_DSP_EXP8_REJ2MHz;
 666                 tg3_phydsp_write(tp, MII_TG3_DSP_EXP8, val);
 667
 668                 tw32(TG3_CPMU_CTRL, cpmuctrl);
 669         }
 670
 671         if (GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5784_AX ||
 672             GET_CHIP_REV(tp->pci_chip_rev_id) == CHIPREV_5761_AX) {
 673                 val = tr32(TG3_CPMU_LSPD_1000MB_CLK);
 674                 if ((val & CPMU_LSPD_1000MB_MACCLK_MASK) ==
 675                     CPMU_LSPD_1000MB_MACCLK_12_5) {
 676                         val &= ~CPMU_LSPD_1000MB_MACCLK_MASK;
 677                         udelay(40);
 678                         tw32_f(TG3_CPMU_LSPD_1000MB_CLK, val);
 679                 }
 680         }
 681
 682         if (tg3_flag(tp, 5717_PLUS) &&
 683             (tp->phy_flags & TG3_PHYFLG_MII_SERDES))
 684                 return 0;
 685
 686         tg3_phy_apply_otp(tp);
 687
 688 out:
 689         if ((tp->phy_flags & TG3_PHYFLG_ADC_BUG) &&
 690             !TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 691                 tg3_phydsp_write(tp, 0x201f, 0x2aaa);
 692                 tg3_phydsp_write(tp, 0x000a, 0x0323);
 693                 TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 694         }
 695
 696         if (tp->phy_flags & TG3_PHYFLG_5704_A0_BUG) {
 697                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
 698                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
 699         }
 700
 701         if (tp->phy_flags & TG3_PHYFLG_BER_BUG) {
 702                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 703                         tg3_phydsp_write(tp, 0x000a, 0x310b);
 704                         tg3_phydsp_write(tp, 0x201f, 0x9506);
 705                         tg3_phydsp_write(tp, 0x401f, 0x14e2);
 706                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 707                 }
 708         } else if (tp->phy_flags & TG3_PHYFLG_JITTER_BUG) {
 709                 if (!TG3_PHY_AUXCTL_SMDSP_ENABLE(tp)) {
 710                         tg3_writephy(tp, MII_TG3_DSP_ADDRESS, 0x000a);
 711                         if (tp->phy_flags & TG3_PHYFLG_ADJUST_TRIM) {
 712                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x110b);
 713                                 tg3_writephy(tp, MII_TG3_TEST1,
 714                                              MII_TG3_TEST1_TRIM_EN | 0x4);
 715                         } else
 716                                 tg3_writephy(tp, MII_TG3_DSP_RW_PORT, 0x010b);
 717
 718                         TG3_PHY_AUXCTL_SMDSP_DISABLE(tp);
 719                 }
 720         }
 721
 722         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
 723                 /* Cannot do read-modify-write on 5401 */
 724                 tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
 725         }
 726
 727         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5906) {
 728                 /* adjust output voltage */
 729                 tg3_writephy(tp, MII_TG3_FET_PTEST, 0x12);
 730         }
 731
 732         tg3_phy_toggle_automdix(tp, 1);
 733         tg3_phy_set_wirespeed(tp);
 734         return 0;
 735 }
 736
 737 static int tg3_copper_is_advertising_all(struct tg3 *tp, u32 mask)
 738 {       DBGP("%s\n", __func__);
 739
 740         u32 adv_reg, all_mask = 0;
 741
 742         if (mask & ADVERTISED_10baseT_Half)
 743                 all_mask |= ADVERTISE_10HALF;
 744         if (mask & ADVERTISED_10baseT_Full)
 745                 all_mask |= ADVERTISE_10FULL;
 746         if (mask & ADVERTISED_100baseT_Half)
 747                 all_mask |= ADVERTISE_100HALF;
 748         if (mask & ADVERTISED_100baseT_Full)
 749                 all_mask |= ADVERTISE_100FULL;
 750
 751         if (tg3_readphy(tp, MII_ADVERTISE, &adv_reg))
 752                 return 0;
 753
 754         if ((adv_reg & all_mask) != all_mask)
 755                 return 0;
 756         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY)) {
 757                 u32 tg3_ctrl;
 758
 759                 all_mask = 0;
 760                 if (mask & ADVERTISED_1000baseT_Half)
 761                         all_mask |= ADVERTISE_1000HALF;
 762                 if (mask & ADVERTISED_1000baseT_Full)
 763                         all_mask |= ADVERTISE_1000FULL;
 764
 765                 if (tg3_readphy(tp, MII_TG3_CTRL, &tg3_ctrl))
 766                         return 0;
 767
 768                 if ((tg3_ctrl & all_mask) != all_mask)
 769                         return 0;
 770         }
 771         return 1;
 772 }
 773
 774 static u16 tg3_advert_flowctrl_1000T(u8 flow_ctrl)
 775 {       DBGP("%s\n", __func__);
 776
 777         u16 miireg;
 778
 779         if ((flow_ctrl & FLOW_CTRL_TX) && (flow_ctrl & FLOW_CTRL_RX))
 780                 miireg = ADVERTISE_PAUSE_CAP;
 781         else if (flow_ctrl & FLOW_CTRL_TX)
 782                 miireg = ADVERTISE_PAUSE_ASYM;
 783         else if (flow_ctrl & FLOW_CTRL_RX)
 784                 miireg = ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM;
 785         else
 786                 miireg = 0;
 787
 788         return miireg;
 789 }
 790
 791 static int tg3_phy_autoneg_cfg(struct tg3 *tp, u32 advertise, u32 flowctrl)
 792 {       DBGP("%s\n", __func__);
 793
 794         int err = 0;
 795         u32 val __unused, new_adv;
 796
 797         new_adv = ADVERTISE_CSMA;
 798         if (advertise & ADVERTISED_10baseT_Half)
 799                 new_adv |= ADVERTISE_10HALF;
 800         if (advertise & ADVERTISED_10baseT_Full)
 801                 new_adv |= ADVERTISE_10FULL;
 802         if (advertise & ADVERTISED_100baseT_Half)
 803                 new_adv |= ADVERTISE_100HALF;
 804         if (advertise & ADVERTISED_100baseT_Full)
 805                 new_adv |= ADVERTISE_100FULL;
 806
 807         new_adv |= tg3_advert_flowctrl_1000T(flowctrl);
 808
 809         err = tg3_writephy(tp, MII_ADVERTISE, new_adv);
 810         if (err)
 811                 goto done;
 812
 813         if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
 814                 goto done;
 815
 816         new_adv = 0;
 817         if (advertise & ADVERTISED_1000baseT_Half)
 818                 new_adv |= MII_TG3_CTRL_ADV_1000_HALF;
 819         if (advertise & ADVERTISED_1000baseT_Full)
 820                 new_adv |= MII_TG3_CTRL_ADV_1000_FULL;
 821
 822         if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
 823             tp->pci_chip_rev_id == CHIPREV_ID_5701_B0)
 824                 new_adv |= (MII_TG3_CTRL_AS_MASTER |
 825                             MII_TG3_CTRL_ENABLE_AS_MASTER);
 826
 827         err = tg3_writephy(tp, MII_TG3_CTRL, new_adv);
 828         if (err)
 829                 goto done;
 830
 831         if (!(tp->phy_flags & TG3_PHYFLG_EEE_CAP))
 832                 goto done;
 833
 834 done:
 835         return err;
 836 }
 837
 838 static int tg3_init_5401phy_dsp(struct tg3 *tp)
 839 {       DBGP("%s\n", __func__);
 840
 841         int err;
 842
 843         /* Turn off tap power management. */
 844         /* Set Extended packet length bit */
 845         err = tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_AUXCTL, 0x4c20);
 846
 847         err |= tg3_phydsp_write(tp, 0x0012, 0x1804);
 848         err |= tg3_phydsp_write(tp, 0x0013, 0x1204);
 849         err |= tg3_phydsp_write(tp, 0x8006, 0x0132);
 850         err |= tg3_phydsp_write(tp, 0x8006, 0x0232);
 851         err |= tg3_phydsp_write(tp, 0x201f, 0x0a20);
 852
 853         udelay(40);
 854
 855         return err;
 856 }
 857
 858 #define ADVERTISED_Autoneg              (1 << 6)
 859 #define ADVERTISED_Pause                (1 << 13)
 860 #define ADVERTISED_TP                   (1 << 7)
 861 #define ADVERTISED_FIBRE                (1 << 10)
 862
 863 #define AUTONEG_ENABLE          0x01
 864
 865 static void tg3_phy_init_link_config(struct tg3 *tp)
 866 {       DBGP("%s\n", __func__);
 867
 868         u32 adv = ADVERTISED_Autoneg |
 869                   ADVERTISED_Pause;
 870
 871
 872         if (!(tp->phy_flags & TG3_PHYFLG_10_100_ONLY))
 873                 adv |= ADVERTISED_1000baseT_Half |
 874                        ADVERTISED_1000baseT_Full;
 875         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES))
 876                 adv |= ADVERTISED_100baseT_Half |
 877                        ADVERTISED_100baseT_Full |
 878                        ADVERTISED_10baseT_Half |
 879                        ADVERTISED_10baseT_Full |
 880                        ADVERTISED_TP;
 881         else
 882                 adv |= ADVERTISED_FIBRE;
 883
 884         tp->link_config.advertising = adv;
 885         tp->link_config.speed = SPEED_INVALID;
 886         tp->link_config.duplex = DUPLEX_INVALID;
 887         tp->link_config.autoneg = AUTONEG_ENABLE;
 888         tp->link_config.active_speed = SPEED_INVALID;
 889         tp->link_config.active_duplex = DUPLEX_INVALID;
 890         tp->link_config.orig_speed = SPEED_INVALID;
 891         tp->link_config.orig_duplex = DUPLEX_INVALID;
 892         tp->link_config.orig_autoneg = AUTONEG_INVALID;
 893 }
 894
 895 int tg3_phy_probe(struct tg3 *tp)
 896 {       DBGP("%s\n", __func__);
 897
 898         u32 hw_phy_id_1, hw_phy_id_2;
 899         u32 hw_phy_id, hw_phy_id_masked;
 900         int err;
 901
 902         /* flow control autonegotiation is default behavior */
 903         tg3_flag_set(tp, PAUSE_AUTONEG);
 904         tp->link_config.flowctrl = FLOW_CTRL_TX | FLOW_CTRL_RX;
 905
 906         /* Reading the PHY ID register can conflict with ASF
 907          * firmware access to the PHY hardware.
 908          */
 909         err = 0;
 910         if (tg3_flag(tp, ENABLE_ASF) || tg3_flag(tp, ENABLE_APE)) {
 911                 hw_phy_id = hw_phy_id_masked = TG3_PHY_ID_INVALID;
 912         } else {
 913                 /* Now read the physical PHY_ID from the chip and verify
 914                  * that it is sane.  If it doesn't look good, we fall back
 915                  * to either the hard-coded table based PHY_ID and failing
 916                  * that the value found in the eeprom area.
 917                  */
 918                 err |= tg3_readphy(tp, MII_PHYSID1, &hw_phy_id_1);
 919                 err |= tg3_readphy(tp, MII_PHYSID2, &hw_phy_id_2);
 920
 921                 hw_phy_id  = (hw_phy_id_1 & 0xffff) << 10;
 922                 hw_phy_id |= (hw_phy_id_2 & 0xfc00) << 16;
 923                 hw_phy_id |= (hw_phy_id_2 & 0x03ff) <<  0;
 924
 925                 hw_phy_id_masked = hw_phy_id & TG3_PHY_ID_MASK;
 926         }
 927
 928         if (!err && TG3_KNOWN_PHY_ID(hw_phy_id_masked)) {
 929                 tp->phy_id = hw_phy_id;
 930                 if (hw_phy_id_masked == TG3_PHY_ID_BCM8002)
 931                         tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
 932                 else
 933                         tp->phy_flags &= ~TG3_PHYFLG_PHY_SERDES;
 934         } else {
 935                 if (tp->phy_id != TG3_PHY_ID_INVALID) {
 936                         /* Do nothing, phy ID already set up in
 937                          * tg3_get_eeprom_hw_cfg().
 938                          */
 939                 } else {
 940                         struct subsys_tbl_ent *p;
 941
 942                         /* No eeprom signature?  Try the hardcoded
 943                          * subsys device table.
 944                          */
 945                         p = tg3_lookup_by_subsys(tp);
 946                         if (!p) {
 947                                 DBGC(&tp->pdev->dev, "lookup by subsys failed\n");
 948                                 return -ENODEV;
 949                         }
 950
 951                         tp->phy_id = p->phy_id;
 952                         if (!tp->phy_id ||
 953                             tp->phy_id == TG3_PHY_ID_BCM8002)
 954                                 tp->phy_flags |= TG3_PHYFLG_PHY_SERDES;
 955                 }
 956         }
 957
 958         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
 959             ((tp->pdev->device == TG3PCI_DEVICE_TIGON3_5718 &&
 960               tp->pci_chip_rev_id != CHIPREV_ID_5717_A0) ||
 961              (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_57765 &&
 962               tp->pci_chip_rev_id != CHIPREV_ID_57765_A0)))
 963                 tp->phy_flags |= TG3_PHYFLG_EEE_CAP;
 964
 965         tg3_phy_init_link_config(tp);
 966
 967         if (!(tp->phy_flags & TG3_PHYFLG_ANY_SERDES) &&
 968             !tg3_flag(tp, ENABLE_APE) &&
 969             !tg3_flag(tp, ENABLE_ASF)) {
 970                 u32 bmsr;
 971                 u32 mask;
 972
 973                 tg3_readphy(tp, MII_BMSR, &bmsr);
 974                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
 975                     (bmsr & BMSR_LSTATUS))
 976                         goto skip_phy_reset;
 977
 978                 err = tg3_phy_reset(tp);
 979                 if (err)
 980                         return err;
 981
 982                 tg3_phy_set_wirespeed(tp);
 983
 984                 mask = (ADVERTISED_10baseT_Half | ADVERTISED_10baseT_Full |
 985                         ADVERTISED_100baseT_Half | ADVERTISED_100baseT_Full |
 986                         ADVERTISED_1000baseT_Half | ADVERTISED_1000baseT_Full);
 987                 if (!tg3_copper_is_advertising_all(tp, mask)) {
 988                         tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
 989                                             tp->link_config.flowctrl);
 990
 991                         tg3_writephy(tp, MII_BMCR,
 992                                      BMCR_ANENABLE | BMCR_ANRESTART);
 993                 }
 994         }
 995
 996 skip_phy_reset:
 997         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
 998                 err = tg3_init_5401phy_dsp(tp);
 999                 if (err)
1000                         return err;
1001
1002                 err = tg3_init_5401phy_dsp(tp);
1003         }
1004
1005         return err;
1006 }
1007
1008 void tg3_poll_link(struct tg3 *tp)
1009 {       DBGP("%s\n", __func__);
1010
1011         if (tp->hw_status->status & SD_STATUS_LINK_CHG) {
1012                 DBGC(tp->dev,"link_changed\n");
1013                 tp->hw_status->status &= ~SD_STATUS_LINK_CHG;
1014                 tg3_setup_phy(tp, 0);
1015         }
1016 }
1017
1018 static void tg3_aux_stat_to_speed_duplex(struct tg3 *tp, u32 val, u16 *speed, u8 *duplex)
1019 {       DBGP("%s\n", __func__);
1020
1021         switch (val & MII_TG3_AUX_STAT_SPDMASK) {
1022         case MII_TG3_AUX_STAT_10HALF:
1023                 *speed = SPEED_10;
1024                 *duplex = DUPLEX_HALF;
1025                 break;
1026
1027         case MII_TG3_AUX_STAT_10FULL:
1028                 *speed = SPEED_10;
1029                 *duplex = DUPLEX_FULL;
1030                 break;
1031
1032         case MII_TG3_AUX_STAT_100HALF:
1033                 *speed = SPEED_100;
1034                 *duplex = DUPLEX_HALF;
1035                 break;
1036
1037         case MII_TG3_AUX_STAT_100FULL:
1038                 *speed = SPEED_100;
1039                 *duplex = DUPLEX_FULL;
1040                 break;
1041
1042         case MII_TG3_AUX_STAT_1000HALF:
1043                 *speed = SPEED_1000;
1044                 *duplex = DUPLEX_HALF;
1045                 break;
1046
1047         case MII_TG3_AUX_STAT_1000FULL:
1048                 *speed = SPEED_1000;
1049                 *duplex = DUPLEX_FULL;
1050                 break;
1051
1052         default:
1053                 if (tp->phy_flags & TG3_PHYFLG_IS_FET) {
1054                         *speed = (val & MII_TG3_AUX_STAT_100) ? SPEED_100 :
1055                                  SPEED_10;
1056                         *duplex = (val & MII_TG3_AUX_STAT_FULL) ? DUPLEX_FULL :
1057                                   DUPLEX_HALF;
1058                         break;
1059                 }
1060                 *speed = SPEED_INVALID;
1061                 *duplex = DUPLEX_INVALID;
1062                 break;
1063         }
1064 }
1065
1066 static int tg3_adv_1000T_flowctrl_ok(struct tg3 *tp, u32 *lcladv, u32 *rmtadv)
1067 {       DBGP("%s\n", __func__);
1068
1069         u32 curadv, reqadv;
1070
1071         if (tg3_readphy(tp, MII_ADVERTISE, lcladv))
1072                 return 1;
1073
1074         curadv = *lcladv & (ADVERTISE_PAUSE_CAP | ADVERTISE_PAUSE_ASYM);
1075         reqadv = tg3_advert_flowctrl_1000T(tp->link_config.flowctrl);
1076
1077         if (tp->link_config.active_duplex == DUPLEX_FULL) {
1078                 if (curadv != reqadv)
1079                         return 0;
1080
1081                 if (tg3_flag(tp, PAUSE_AUTONEG))
1082                         tg3_readphy(tp, MII_LPA, rmtadv);
1083         } else {
1084                 /* Reprogram the advertisement register, even if it
1085                  * does not affect the current link.  If the link
1086                  * gets renegotiated in the future, we can save an
1087                  * additional renegotiation cycle by advertising
1088                  * it correctly in the first place.
1089                  */
1090                 if (curadv != reqadv) {
1091                         *lcladv &= ~(ADVERTISE_PAUSE_CAP |
1092                                      ADVERTISE_PAUSE_ASYM);
1093                         tg3_writephy(tp, MII_ADVERTISE, *lcladv | reqadv);
1094                 }
1095         }
1096
1097         return 1;
1098 }
1099
1100 static u8 tg3_resolve_flowctrl_1000X(u16 lcladv, u16 rmtadv)
1101 {       DBGP("%s\n", __func__);
1102
1103         u8 cap = 0;
1104
1105         if (lcladv & ADVERTISE_1000XPAUSE) {
1106                 if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1107                         if (rmtadv & LPA_1000XPAUSE)
1108                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1109                         else if (rmtadv & LPA_1000XPAUSE_ASYM)
1110                                 cap = FLOW_CTRL_RX;
1111                 } else {
1112                         if (rmtadv & LPA_1000XPAUSE)
1113                                 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
1114                 }
1115         } else if (lcladv & ADVERTISE_1000XPSE_ASYM) {
1116                 if ((rmtadv & LPA_1000XPAUSE) && (rmtadv & LPA_1000XPAUSE_ASYM))
1117                         cap = FLOW_CTRL_TX;
1118         }
1119
1120         return cap;
1121 }
1122
1123 static void tg3_setup_flow_control(struct tg3 *tp, u32 lcladv, u32 rmtadv)
1124 {       DBGP("%s\n", __func__);
1125
1126         u8 flowctrl = 0;
1127         u32 old_rx_mode = tp->rx_mode;
1128         u32 old_tx_mode = tp->tx_mode;
1129
1130         if (tg3_flag(tp, PAUSE_AUTONEG)) {
1131                 if (tp->phy_flags & TG3_PHYFLG_ANY_SERDES)
1132                         flowctrl = tg3_resolve_flowctrl_1000X(lcladv, rmtadv);
1133                 else
1134                         flowctrl = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1135         } else
1136                 flowctrl = tp->link_config.flowctrl;
1137
1138         tp->link_config.active_flowctrl = flowctrl;
1139
1140         if (flowctrl & FLOW_CTRL_RX)
1141                 tp->rx_mode |= RX_MODE_FLOW_CTRL_ENABLE;
1142         else
1143                 tp->rx_mode &= ~RX_MODE_FLOW_CTRL_ENABLE;
1144
1145         if (old_rx_mode != tp->rx_mode)
1146                 tw32_f(MAC_RX_MODE, tp->rx_mode);
1147
1148         if (flowctrl & FLOW_CTRL_TX)
1149                 tp->tx_mode |= TX_MODE_FLOW_CTRL_ENABLE;
1150         else
1151                 tp->tx_mode &= ~TX_MODE_FLOW_CTRL_ENABLE;
1152
1153         if (old_tx_mode != tp->tx_mode)
1154                 tw32_f(MAC_TX_MODE, tp->tx_mode);
1155 }
1156
1157 static void tg3_phy_copper_begin(struct tg3 *tp)
1158 {       DBGP("%s\n", __func__);
1159
1160         u32 new_adv;
1161
1162         if (tp->link_config.speed == SPEED_INVALID) {
1163                 if (tp->phy_flags & TG3_PHYFLG_10_100_ONLY)
1164                         tp->link_config.advertising &=
1165                                 ~(ADVERTISED_1000baseT_Half |
1166                                   ADVERTISED_1000baseT_Full);
1167
1168                 tg3_phy_autoneg_cfg(tp, tp->link_config.advertising,
1169                                     tp->link_config.flowctrl);
1170         } else {
1171                 /* Asking for a specific link mode. */
1172                 if (tp->link_config.speed == SPEED_1000) {
1173                         if (tp->link_config.duplex == DUPLEX_FULL)
1174                                 new_adv = ADVERTISED_1000baseT_Full;
1175                         else
1176                                 new_adv = ADVERTISED_1000baseT_Half;
1177                 } else if (tp->link_config.speed == SPEED_100) {
1178                         if (tp->link_config.duplex == DUPLEX_FULL)
1179                                 new_adv = ADVERTISED_100baseT_Full;
1180                         else
1181                                 new_adv = ADVERTISED_100baseT_Half;
1182                 } else {
1183                         if (tp->link_config.duplex == DUPLEX_FULL)
1184                                 new_adv = ADVERTISED_10baseT_Full;
1185                         else
1186                                 new_adv = ADVERTISED_10baseT_Half;
1187                 }
1188
1189                 tg3_phy_autoneg_cfg(tp, new_adv,
1190                                     tp->link_config.flowctrl);
1191         }
1192
1193         tg3_writephy(tp, MII_BMCR, BMCR_ANENABLE | BMCR_ANRESTART);
1194 }
1195
1196 static int tg3_5700_link_polarity(struct tg3 *tp, u32 speed)
1197 {       DBGP("%s\n", __func__);
1198
1199         if (tp->led_ctrl == LED_CTRL_MODE_PHY_2)
1200                 return 1;
1201         else if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411) {
1202                 if (speed != SPEED_10)
1203                         return 1;
1204         } else if (speed == SPEED_10)
1205                 return 1;
1206
1207         return 0;
1208 }
1209
1210 #if 1
1211
1212 static void tg3_ump_link_report(struct tg3 *tp)
1213 {       DBGP("%s\n", __func__);
1214
1215         u32 reg;
1216         u32 val;
1217
1218         if (!tg3_flag(tp, 5780_CLASS) || !tg3_flag(tp, ENABLE_ASF))
1219                 return;
1220
1221         tg3_wait_for_event_ack(tp);
1222
1223         tg3_write_mem(tp, NIC_SRAM_FW_CMD_MBOX, FWCMD_NICDRV_LINK_UPDATE);
1224
1225         tg3_write_mem(tp, NIC_SRAM_FW_CMD_LEN_MBOX, 14);
1226
1227         val = 0;
1228         if (!tg3_readphy(tp, MII_BMCR, &reg))
1229                 val = reg << 16;
1230         if (!tg3_readphy(tp, MII_BMSR, &reg))
1231                 val |= (reg & 0xffff);
1232         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX, val);
1233
1234         val = 0;
1235         if (!tg3_readphy(tp, MII_ADVERTISE, &reg))
1236                 val = reg << 16;
1237         if (!tg3_readphy(tp, MII_LPA, &reg))
1238                 val |= (reg & 0xffff);
1239         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 4, val);
1240
1241         val = 0;
1242         if (!(tp->phy_flags & TG3_PHYFLG_MII_SERDES)) {
1243                 if (!tg3_readphy(tp, MII_CTRL1000, &reg))
1244                         val = reg << 16;
1245                 if (!tg3_readphy(tp, MII_STAT1000, &reg))
1246                         val |= (reg & 0xffff);
1247         }
1248         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 8, val);
1249
1250         if (!tg3_readphy(tp, MII_PHYADDR, &reg))
1251                 val = reg << 16;
1252         else
1253                 val = 0;
1254         tg3_write_mem(tp, NIC_SRAM_FW_CMD_DATA_MBOX + 12, val);
1255
1256         tg3_generate_fw_event(tp);
1257 }
1258
1259 /* NOTE: Debugging only code */
1260 static void tg3_link_report(struct tg3 *tp)
1261 {       DBGP("%s\n", __func__);
1262
1263         if (!netdev_link_ok(tp->dev)) {
1264                 DBGC(tp->dev, "Link is down\n");
1265                 tg3_ump_link_report(tp);
1266         } else {
1267                 DBGC(tp->dev, "Link is up at %d Mbps, %s duplex\n",
1268                             (tp->link_config.active_speed == SPEED_1000 ?
1269                              1000 :
1270                              (tp->link_config.active_speed == SPEED_100 ?
1271                               100 : 10)),
1272                             (tp->link_config.active_duplex == DUPLEX_FULL ?
1273                              "full" : "half"));
1274
1275                 DBGC(tp->dev, "Flow control is %s for TX and %s for RX\n",
1276                             (tp->link_config.active_flowctrl & FLOW_CTRL_TX) ?
1277                             "on" : "off",
1278                             (tp->link_config.active_flowctrl & FLOW_CTRL_RX) ?
1279                             "on" : "off");
1280
1281                 if (tp->phy_flags & TG3_PHYFLG_EEE_CAP)
1282                         DBGC(tp->dev, "EEE is %s\n",
1283                                     tp->setlpicnt ? "enabled" : "disabled");
1284
1285                 tg3_ump_link_report(tp);
1286         }
1287 }
1288 #endif
1289
1290 static int tg3_setup_copper_phy(struct tg3 *tp, int force_reset)
1291 {       DBGP("%s\n", __func__);
1292
1293         int current_link_up;
1294         u32 bmsr, val;
1295         u32 lcl_adv, rmt_adv;
1296         u16 current_speed;
1297         u8 current_duplex;
1298         int i, err;
1299
1300         tw32(MAC_EVENT, 0);
1301
1302         tw32_f(MAC_STATUS,
1303              (MAC_STATUS_SYNC_CHANGED |
1304               MAC_STATUS_CFG_CHANGED |
1305               MAC_STATUS_MI_COMPLETION |
1306               MAC_STATUS_LNKSTATE_CHANGED));
1307         udelay(40);
1308
1309         if ((tp->mi_mode & MAC_MI_MODE_AUTO_POLL) != 0) {
1310                 tw32_f(MAC_MI_MODE,
1311                      (tp->mi_mode & ~MAC_MI_MODE_AUTO_POLL));
1312                 udelay(80);
1313         }
1314
1315         tg3_phy_auxctl_write(tp, MII_TG3_AUXCTL_SHDWSEL_PWRCTL, 0);
1316
1317         /* Some third-party PHYs need to be reset on link going
1318          * down.
1319          */
1320         if ((GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5703 ||
1321              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5704 ||
1322              GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5705) &&
1323             netdev_link_ok(tp->dev)) {
1324                 tg3_readphy(tp, MII_BMSR, &bmsr);
1325                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1326                     !(bmsr & BMSR_LSTATUS))
1327                         force_reset = 1;
1328         }
1329         if (force_reset)
1330                 tg3_phy_reset(tp);
1331
1332         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5401) {
1333                 tg3_readphy(tp, MII_BMSR, &bmsr);
1334                 if (tg3_readphy(tp, MII_BMSR, &bmsr) ||
1335                     !tg3_flag(tp, INIT_COMPLETE))
1336                         bmsr = 0;
1337
1338                 if (!(bmsr & BMSR_LSTATUS)) {
1339                         err = tg3_init_5401phy_dsp(tp);
1340                         if (err)
1341                                 return err;
1342
1343                         tg3_readphy(tp, MII_BMSR, &bmsr);
1344                         for (i = 0; i < 1000; i++) {
1345                                 udelay(10);
1346                                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1347                                     (bmsr & BMSR_LSTATUS)) {
1348                                         udelay(40);
1349                                         break;
1350                                 }
1351                         }
1352
1353                         if ((tp->phy_id & TG3_PHY_ID_REV_MASK) ==
1354                             TG3_PHY_REV_BCM5401_B0 &&
1355                             !(bmsr & BMSR_LSTATUS) &&
1356                             tp->link_config.active_speed == SPEED_1000) {
1357                                 err = tg3_phy_reset(tp);
1358                                 if (!err)
1359                                         err = tg3_init_5401phy_dsp(tp);
1360                                 if (err)
1361                                         return err;
1362                         }
1363                 }
1364         } else if (tp->pci_chip_rev_id == CHIPREV_ID_5701_A0 ||
1365                    tp->pci_chip_rev_id == CHIPREV_ID_5701_B0) {
1366                 /* 5701 {A0,B0} CRC bug workaround */
1367                 tg3_writephy(tp, 0x15, 0x0a75);
1368                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1369                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8d68);
1370                 tg3_writephy(tp, MII_TG3_MISC_SHDW, 0x8c68);
1371         }
1372
1373         /* Clear pending interrupts... */
1374         tg3_readphy(tp, MII_TG3_ISTAT, &val);
1375         tg3_readphy(tp, MII_TG3_ISTAT, &val);
1376
1377         if (tp->phy_flags & TG3_PHYFLG_USE_MI_INTERRUPT)
1378                 tg3_writephy(tp, MII_TG3_IMASK, ~MII_TG3_INT_LINKCHG);
1379         else if (!(tp->phy_flags & TG3_PHYFLG_IS_FET))
1380                 tg3_writephy(tp, MII_TG3_IMASK, ~0);
1381
1382         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 ||
1383             GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5701) {
1384                 if (tp->led_ctrl == LED_CTRL_MODE_PHY_1)
1385                         tg3_writephy(tp, MII_TG3_EXT_CTRL,
1386                                      MII_TG3_EXT_CTRL_LNK3_LED_MODE);
1387                 else
1388                         tg3_writephy(tp, MII_TG3_EXT_CTRL, 0);
1389         }
1390
1391         current_link_up = 0;
1392         current_speed = SPEED_INVALID;
1393         current_duplex = DUPLEX_INVALID;
1394
1395         if (tp->phy_flags & TG3_PHYFLG_CAPACITIVE_COUPLING) {
1396                 err = tg3_phy_auxctl_read(tp,
1397                                           MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
1398                                           &val);
1399                 if (!err && !(val & (1 << 10))) {
1400                         tg3_phy_auxctl_write(tp,
1401                                              MII_TG3_AUXCTL_SHDWSEL_MISCTEST,
1402                                              val | (1 << 10));
1403                         goto relink;
1404                 }
1405         }
1406
1407         bmsr = 0;
1408         for (i = 0; i < 100; i++) {
1409                 tg3_readphy(tp, MII_BMSR, &bmsr);
1410                 if (!tg3_readphy(tp, MII_BMSR, &bmsr) &&
1411                     (bmsr & BMSR_LSTATUS))
1412                         break;
1413                 udelay(40);
1414         }
1415
1416         if (bmsr & BMSR_LSTATUS) {
1417                 u32 aux_stat, bmcr;
1418
1419                 tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat);
1420                 for (i = 0; i < 2000; i++) {
1421                         udelay(10);
1422                         if (!tg3_readphy(tp, MII_TG3_AUX_STAT, &aux_stat) &&
1423                             aux_stat)
1424                                 break;
1425                 }
1426
1427                 tg3_aux_stat_to_speed_duplex(tp, aux_stat,
1428                                              &current_speed,
1429                                              &current_duplex);
1430
1431                 bmcr = 0;
1432                 for (i = 0; i < 200; i++) {
1433                         tg3_readphy(tp, MII_BMCR, &bmcr);
1434                         if (tg3_readphy(tp, MII_BMCR, &bmcr))
1435                                 continue;
1436                         if (bmcr && bmcr != 0x7fff)
1437                                 break;
1438                         udelay(10);
1439                 }
1440
1441                 lcl_adv = 0;
1442                 rmt_adv = 0;
1443
1444                 tp->link_config.active_speed = current_speed;
1445                 tp->link_config.active_duplex = current_duplex;
1446
1447                 if ((bmcr & BMCR_ANENABLE) &&
1448                     tg3_copper_is_advertising_all(tp,
1449                                         tp->link_config.advertising)) {
1450                         if (tg3_adv_1000T_flowctrl_ok(tp, &lcl_adv,
1451                                                           &rmt_adv)) {
1452                                 current_link_up = 1;
1453                         }
1454                 }
1455
1456                 if (current_link_up == 1 &&
1457                     tp->link_config.active_duplex == DUPLEX_FULL)
1458                         tg3_setup_flow_control(tp, lcl_adv, rmt_adv);
1459         }
1460
1461 relink:
1462         if (current_link_up == 0) {
1463                 tg3_phy_copper_begin(tp);
1464
1465                 tg3_readphy(tp, MII_BMSR, &bmsr);
1466                 if ((!tg3_readphy(tp, MII_BMSR, &bmsr) && (bmsr & BMSR_LSTATUS)) ||
1467                     (tp->mac_mode & MAC_MODE_PORT_INT_LPBACK))
1468                         current_link_up = 1;
1469         }
1470
1471         tp->mac_mode &= ~MAC_MODE_PORT_MODE_MASK;
1472         if (current_link_up == 1) {
1473                 if (tp->link_config.active_speed == SPEED_100 ||
1474                     tp->link_config.active_speed == SPEED_10)
1475                         tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1476                 else
1477                         tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1478         } else if (tp->phy_flags & TG3_PHYFLG_IS_FET)
1479                 tp->mac_mode |= MAC_MODE_PORT_MODE_MII;
1480         else
1481                 tp->mac_mode |= MAC_MODE_PORT_MODE_GMII;
1482
1483         tp->mac_mode &= ~MAC_MODE_HALF_DUPLEX;
1484         if (tp->link_config.active_duplex == DUPLEX_HALF)
1485                 tp->mac_mode |= MAC_MODE_HALF_DUPLEX;
1486
1487         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700) {
1488                 if (current_link_up == 1 &&
1489                     tg3_5700_link_polarity(tp, tp->link_config.active_speed))
1490                         tp->mac_mode |= MAC_MODE_LINK_POLARITY;
1491                 else
1492                         tp->mac_mode &= ~MAC_MODE_LINK_POLARITY;
1493         }
1494
1495         /* ??? Without this setting Netgear GA302T PHY does not
1496          * ??? send/receive packets...
1497          */
1498         if ((tp->phy_id & TG3_PHY_ID_MASK) == TG3_PHY_ID_BCM5411 &&
1499             tp->pci_chip_rev_id == CHIPREV_ID_5700_ALTIMA) {
1500                 tp->mi_mode |= MAC_MI_MODE_AUTO_POLL;
1501                 tw32_f(MAC_MI_MODE, tp->mi_mode);
1502                 udelay(80);
1503         }
1504
1505         tw32_f(MAC_MODE, tp->mac_mode);
1506         udelay(40);
1507
1508         /* Enabled attention when the link has changed state. */
1509         tw32_f(MAC_EVENT, MAC_EVENT_LNKSTATE_CHANGED);
1510         udelay(40);
1511
1512         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5700 &&
1513             current_link_up == 1 &&
1514             tp->link_config.active_speed == SPEED_1000 &&
1515             (tg3_flag(tp, PCIX_MODE) || tg3_flag(tp, PCI_HIGH_SPEED))) {
1516                 udelay(120);
1517                 /* NOTE: this freezes for mdc? */
1518                 tw32_f(MAC_STATUS,
1519                      (MAC_STATUS_SYNC_CHANGED |
1520                       MAC_STATUS_CFG_CHANGED));
1521                 udelay(40);
1522                 tg3_write_mem(tp,
1523                               NIC_SRAM_FIRMWARE_MBOX,
1524                               NIC_SRAM_FIRMWARE_MBOX_MAGIC2);
1525         }
1526
1527         /* Prevent send BD corruption. */
1528         if (tg3_flag(tp, CLKREQ_BUG)) {
1529                 u16 oldlnkctl, newlnkctl;
1530
1531                 pci_read_config_word(tp->pdev,
1532                                      tp->pcie_cap + PCI_EXP_LNKCTL,
1533                                      &oldlnkctl);
1534                 if (tp->link_config.active_speed == SPEED_100 ||
1535                     tp->link_config.active_speed == SPEED_10)
1536                         newlnkctl = oldlnkctl & ~PCI_EXP_LNKCTL_CLKREQ_EN;
1537                 else
1538                         newlnkctl = oldlnkctl | PCI_EXP_LNKCTL_CLKREQ_EN;
1539                 if (newlnkctl != oldlnkctl)
1540                         pci_write_config_word(tp->pdev,
1541                                               tp->pcie_cap + PCI_EXP_LNKCTL,
1542                                               newlnkctl);
1543         }
1544
1545         if (current_link_up != netdev_link_ok(tp->dev)) {
1546                 if (current_link_up)
1547                         netdev_link_up(tp->dev);
1548                 else
1549                         netdev_link_down(tp->dev);
1550                 tg3_link_report(tp);
1551         }
1552
1553         return 0;
1554 }
1555
1556 int tg3_setup_phy(struct tg3 *tp, int force_reset)
1557 {       DBGP("%s\n", __func__);
1558
1559         u32 val;
1560         int err;
1561
1562 #if 0
1563         if (tp->phy_flags & TG3_PHYFLG_PHY_SERDES)
1564                 err = tg3_setup_fiber_phy(tp, force_reset);
1565         else if (tp->phy_flags & TG3_PHYFLG_MII_SERDES)
1566                 err = tg3_setup_fiber_mii_phy(tp, force_reset);
1567         else
1568 #endif
1569         /* FIXME: add only copper phy variants for now */
1570         err = tg3_setup_copper_phy(tp, force_reset);
1571
1572         val = (2 << TX_LENGTHS_IPG_CRS_SHIFT) |
1573               (6 << TX_LENGTHS_IPG_SHIFT);
1574         if (GET_ASIC_REV(tp->pci_chip_rev_id) == ASIC_REV_5720)
1575                 val |= tr32(MAC_TX_LENGTHS) &
1576                        (TX_LENGTHS_JMB_FRM_LEN_MSK |
1577                         TX_LENGTHS_CNT_DWN_VAL_MSK);
1578
1579         if (tp->link_config.active_speed == SPEED_1000 &&
1580             tp->link_config.active_duplex == DUPLEX_HALF)
1581                 tw32(MAC_TX_LENGTHS, val |
1582                      (0xff << TX_LENGTHS_SLOT_TIME_SHIFT));
1583         else
1584                 tw32(MAC_TX_LENGTHS, val |
1585                      (32 << TX_LENGTHS_SLOT_TIME_SHIFT));
1586
1587         if (!tg3_flag(tp, 5705_PLUS)) {
1588                 if (netdev_link_ok(tp->dev)) {
1589                         tw32(HOSTCC_STAT_COAL_TICKS, DEFAULT_STAT_COAL_TICKS);
1590                 } else {
1591                         tw32(HOSTCC_STAT_COAL_TICKS, 0);
1592                 }
1593         }
1594
1595         val = tr32(PCIE_PWR_MGMT_THRESH);
1596         if (!netdev_link_ok(tp->dev))
1597                 val = (val & ~PCIE_PWR_MGMT_L1_THRESH_MSK);
1598         else
1599                 val |= PCIE_PWR_MGMT_L1_THRESH_MSK;
1600         tw32(PCIE_PWR_MGMT_THRESH, val);
1601
1602         return err;
1603 }