1 /* $Id: tg3.h,v 1.37.2.32 2002/03/11 12:18:18 davem Exp $
2 * tg3.h: Definitions for Broadcom Tigon3 ethernet driver.
4 * Copyright (C) 2001, 2002, 2003, 2004 David S. Miller (davem@redhat.com)
5 * Copyright (C) 2001 Jeff Garzik (jgarzik@pobox.com)
6 * Copyright (C) 2004 Sun Microsystems Inc.
7 * Copyright (C) 2007-2011 Broadcom Corporation.
14 #define ERRFILE ERRFILE_tg3
16 /* From linux/include/linux/pci_regs.h: */
17 #define PCI_EXP_LNKCTL 16 /* Link Control */
18 #define PCI_EXP_LNKCTL_CLKREQ_EN 0x100 /* Enable clkreq */
19 #define PCI_CAP_ID_PCIX 0x07 /* PCI-X */
21 #define PCI_X_CMD_READ_2K 0x0008 /* 2Kbyte maximum read byte count */
22 #define PCI_X_CMD_MAX_READ 0x000c /* Max Memory Read Byte Count */
24 #define PCI_X_CMD_MAX_SPLIT 0x0070 /* Max Outstanding Split Transactions */
28 #define ADVERTISED_10baseT_Half (1 << 0)
29 #define ADVERTISED_10baseT_Full (1 << 1)
30 #define ADVERTISED_100baseT_Half (1 << 2)
31 #define ADVERTISED_100baseT_Full (1 << 3)
32 #define ADVERTISED_1000baseT_Half (1 << 4)
33 #define ADVERTISED_1000baseT_Full (1 << 5)
34 #define ADVERTISED_Autoneg (1 << 6)
38 #define MDIO_AN_EEE_ADV 60 /* EEE advertisement */
40 #define MDIO_MMD_AN 7 /* Auto-Negotiation */
42 #define MDIO_AN_EEE_ADV_100TX 0x0002 /* Advertise 100TX EEE cap */
43 #define MDIO_AN_EEE_ADV_1000T 0x0004 /* Advertise 1000T EEE cap */
47 #define FLOW_CTRL_TX 0x01
48 #define FLOW_CTRL_RX 0x02
52 #define PCI_X_CMD 2 /* Modes & Features */
53 #define PCI_X_CMD_ERO 0x0002 /* Enable Relaxed Ordering */
55 #define PCI_EXP_DEVCTL 8 /* Device Control */
56 #define PCI_EXP_DEVCTL_RELAX_EN 0x0010 /* Enable relaxed ordering */
57 #define PCI_EXP_DEVCTL_NOSNOOP_EN 0x0800 /* Enable No Snoop */
58 #define PCI_EXP_DEVCTL_PAYLOAD 0x00e0 /* Max_Payload_Size */
59 #define PCI_EXP_DEVSTA 10 /* Device Status */
60 #define PCI_EXP_DEVSTA_CED 0x01 /* Correctable Error Detected */
61 #define PCI_EXP_DEVSTA_NFED 0x02 /* Non-Fatal Error Detected */
62 #define PCI_EXP_DEVSTA_FED 0x04 /* Fatal Error Detected */
63 #define PCI_EXP_DEVSTA_URD 0x08 /* Unsupported Request Detected */
67 #define PCI_VENDOR_ID_BROADCOM 0x14e4
68 #define PCI_DEVICE_ID_TIGON3_5752 0x1600
69 #define PCI_DEVICE_ID_TIGON3_5752M 0x1601
70 #define PCI_DEVICE_ID_NX2_5709 0x1639
71 #define PCI_DEVICE_ID_NX2_5709S 0x163a
72 #define PCI_DEVICE_ID_TIGON3_5700 0x1644
73 #define PCI_DEVICE_ID_TIGON3_5701 0x1645
74 #define PCI_DEVICE_ID_TIGON3_5702 0x1646
75 #define PCI_DEVICE_ID_TIGON3_5703 0x1647
76 #define PCI_DEVICE_ID_TIGON3_5704 0x1648
77 #define PCI_DEVICE_ID_TIGON3_5704S_2 0x1649
78 #define PCI_DEVICE_ID_NX2_5706 0x164a
79 #define PCI_DEVICE_ID_NX2_5708 0x164c
80 #define PCI_DEVICE_ID_TIGON3_5702FE 0x164d
81 #define PCI_DEVICE_ID_NX2_57710 0x164e
82 #define PCI_DEVICE_ID_NX2_57711 0x164f
83 #define PCI_DEVICE_ID_NX2_57711E 0x1650
84 #define PCI_DEVICE_ID_TIGON3_5705 0x1653
85 #define PCI_DEVICE_ID_TIGON3_5705_2 0x1654
86 #define PCI_DEVICE_ID_TIGON3_5721 0x1659
87 #define PCI_DEVICE_ID_TIGON3_5722 0x165a
88 #define PCI_DEVICE_ID_TIGON3_5723 0x165b
89 #define PCI_DEVICE_ID_TIGON3_5705M 0x165d
90 #define PCI_DEVICE_ID_TIGON3_5705M_2 0x165e
91 #define PCI_DEVICE_ID_NX2_57712 0x1662
92 #define PCI_DEVICE_ID_NX2_57712E 0x1663
93 #define PCI_DEVICE_ID_TIGON3_5714 0x1668
94 #define PCI_DEVICE_ID_TIGON3_5714S 0x1669
95 #define PCI_DEVICE_ID_TIGON3_5780 0x166a
96 #define PCI_DEVICE_ID_TIGON3_5780S 0x166b
97 #define PCI_DEVICE_ID_TIGON3_5705F 0x166e
98 #define PCI_DEVICE_ID_TIGON3_5754M 0x1672
99 #define PCI_DEVICE_ID_TIGON3_5755M 0x1673
100 #define PCI_DEVICE_ID_TIGON3_5756 0x1674
101 #define PCI_DEVICE_ID_TIGON3_5751 0x1677
102 #define PCI_DEVICE_ID_TIGON3_5715 0x1678
103 #define PCI_DEVICE_ID_TIGON3_5715S 0x1679
104 #define PCI_DEVICE_ID_TIGON3_5754 0x167a
105 #define PCI_DEVICE_ID_TIGON3_5755 0x167b
106 #define PCI_DEVICE_ID_TIGON3_5751M 0x167d
107 #define PCI_DEVICE_ID_TIGON3_5751F 0x167e
108 #define PCI_DEVICE_ID_TIGON3_5787F 0x167f
109 #define PCI_DEVICE_ID_TIGON3_5761E 0x1680
110 #define PCI_DEVICE_ID_TIGON3_5761 0x1681
111 #define PCI_DEVICE_ID_TIGON3_5764 0x1684
112 #define PCI_DEVICE_ID_TIGON3_5787M 0x1693
113 #define PCI_DEVICE_ID_TIGON3_5782 0x1696
114 #define PCI_DEVICE_ID_TIGON3_5784 0x1698
115 #define PCI_DEVICE_ID_TIGON3_5786 0x169a
116 #define PCI_DEVICE_ID_TIGON3_5787 0x169b
117 #define PCI_DEVICE_ID_TIGON3_5788 0x169c
118 #define PCI_DEVICE_ID_TIGON3_5789 0x169d
119 #define PCI_DEVICE_ID_TIGON3_5702X 0x16a6
120 #define PCI_DEVICE_ID_TIGON3_5703X 0x16a7
121 #define PCI_DEVICE_ID_TIGON3_5704S 0x16a8
122 #define PCI_DEVICE_ID_NX2_5706S 0x16aa
123 #define PCI_DEVICE_ID_NX2_5708S 0x16ac
124 #define PCI_DEVICE_ID_TIGON3_5702A3 0x16c6
125 #define PCI_DEVICE_ID_TIGON3_5703A3 0x16c7
126 #define PCI_DEVICE_ID_TIGON3_5781 0x16dd
127 #define PCI_DEVICE_ID_TIGON3_5753 0x16f7
128 #define PCI_DEVICE_ID_TIGON3_5753M 0x16fd
129 #define PCI_DEVICE_ID_TIGON3_5753F 0x16fe
130 #define PCI_DEVICE_ID_TIGON3_5901 0x170d
131 #define PCI_DEVICE_ID_TIGON3_5901_2 0x170e
132 #define PCI_DEVICE_ID_TIGON3_5906 0x1712
133 #define PCI_DEVICE_ID_TIGON3_5906M 0x1713
137 #define SPEED_100 100
138 #define SPEED_1000 1000
140 #define DUPLEX_HALF 0x00
141 #define DUPLEX_FULL 0x01
143 #define TG3_64BIT_REG_HIGH 0x00UL
144 #define TG3_64BIT_REG_LOW 0x04UL
146 /* Descriptor block info. */
147 #define TG3_BDINFO_HOST_ADDR 0x0UL /* 64-bit */
148 #define TG3_BDINFO_MAXLEN_FLAGS 0x8UL /* 32-bit */
149 #define BDINFO_FLAGS_USE_EXT_RECV 0x00000001 /* ext rx_buffer_desc */
150 #define BDINFO_FLAGS_DISABLED 0x00000002
151 #define BDINFO_FLAGS_MAXLEN_MASK 0xffff0000
152 #define BDINFO_FLAGS_MAXLEN_SHIFT 16
153 #define TG3_BDINFO_NIC_ADDR 0xcUL /* 32-bit */
154 #define TG3_BDINFO_SIZE 0x10UL
156 #define RX_STD_MAX_SIZE 1536
157 #define TG3_RX_STD_MAX_SIZE_5700 512
158 #define TG3_RX_STD_MAX_SIZE_5717 2048
159 #define TG3_RX_JMB_MAX_SIZE_5700 256
160 #define TG3_RX_JMB_MAX_SIZE_5717 1024
161 #define TG3_RX_RET_MAX_SIZE_5700 1024
162 #define TG3_RX_RET_MAX_SIZE_5705 512
163 #define TG3_RX_RET_MAX_SIZE_5717 4096
165 /* First 256 bytes are a mirror of PCI config space. */
166 #define TG3PCI_VENDOR 0x00000000
167 #define TG3PCI_VENDOR_BROADCOM 0x14e4
168 #define TG3PCI_DEVICE 0x00000002
169 #define TG3PCI_DEVICE_TIGON3_1 0x1644 /* BCM5700 */
170 #define TG3PCI_DEVICE_TIGON3_2 0x1645 /* BCM5701 */
171 #define TG3PCI_DEVICE_TIGON3_3 0x1646 /* BCM5702 */
172 #define TG3PCI_DEVICE_TIGON3_4 0x1647 /* BCM5703 */
173 #define TG3PCI_DEVICE_TIGON3_5761S 0x1688
174 #define TG3PCI_DEVICE_TIGON3_5761SE 0x1689
175 #define TG3PCI_DEVICE_TIGON3_57780 0x1692
176 #define TG3PCI_DEVICE_TIGON3_57760 0x1690
177 #define TG3PCI_DEVICE_TIGON3_57790 0x1694
178 #define TG3PCI_DEVICE_TIGON3_57788 0x1691
179 #define TG3PCI_DEVICE_TIGON3_5785_G 0x1699 /* GPHY */
180 #define TG3PCI_DEVICE_TIGON3_5785_F 0x16a0 /* 10/100 only */
181 #define TG3PCI_DEVICE_TIGON3_5717 0x1655
182 #define TG3PCI_DEVICE_TIGON3_5718 0x1656
183 #define TG3PCI_DEVICE_TIGON3_57781 0x16b1
184 #define TG3PCI_DEVICE_TIGON3_57785 0x16b5
185 #define TG3PCI_DEVICE_TIGON3_57761 0x16b0
186 #define TG3PCI_DEVICE_TIGON3_57762 0x1682
187 #define TG3PCI_DEVICE_TIGON3_57765 0x16b4
188 #define TG3PCI_DEVICE_TIGON3_57791 0x16b2
189 #define TG3PCI_DEVICE_TIGON3_57795 0x16b6
190 #define TG3PCI_DEVICE_TIGON3_5719 0x1657
191 #define TG3PCI_DEVICE_TIGON3_5720 0x165f
192 /* 0x04 --> 0x2c unused */
193 #define TG3PCI_SUBVENDOR_ID_BROADCOM PCI_VENDOR_ID_BROADCOM
194 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A6 0x1644
195 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A5 0x0001
196 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700T6 0x0002
197 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95700A9 0x0003
198 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T1 0x0005
199 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701T8 0x0006
200 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A7 0x0007
201 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A10 0x0008
202 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95701A12 0x8008
203 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX1 0x0009
204 #define TG3PCI_SUBDEVICE_ID_BROADCOM_95703AX2 0x8009
205 #define TG3PCI_SUBVENDOR_ID_3COM PCI_VENDOR_ID_3COM
206 #define TG3PCI_SUBDEVICE_ID_3COM_3C996T 0x1000
207 #define TG3PCI_SUBDEVICE_ID_3COM_3C996BT 0x1006
208 #define TG3PCI_SUBDEVICE_ID_3COM_3C996SX 0x1004
209 #define TG3PCI_SUBDEVICE_ID_3COM_3C1000T 0x1007
210 #define TG3PCI_SUBDEVICE_ID_3COM_3C940BR01 0x1008
211 #define TG3PCI_SUBVENDOR_ID_DELL PCI_VENDOR_ID_DELL
212 #define TG3PCI_SUBDEVICE_ID_DELL_VIPER 0x00d1
213 #define TG3PCI_SUBDEVICE_ID_DELL_JAGUAR 0x0106
214 #define TG3PCI_SUBDEVICE_ID_DELL_MERLOT 0x0109
215 #define TG3PCI_SUBDEVICE_ID_DELL_SLIM_MERLOT 0x010a
216 #define TG3PCI_SUBVENDOR_ID_COMPAQ PCI_VENDOR_ID_COMPAQ
217 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE 0x007c
218 #define TG3PCI_SUBDEVICE_ID_COMPAQ_BANSHEE_2 0x009a
219 #define TG3PCI_SUBDEVICE_ID_COMPAQ_CHANGELING 0x007d
220 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780 0x0085
221 #define TG3PCI_SUBDEVICE_ID_COMPAQ_NC7780_2 0x0099
222 #define TG3PCI_SUBVENDOR_ID_IBM PCI_VENDOR_ID_IBM
223 #define TG3PCI_SUBDEVICE_ID_IBM_5703SAX2 0x0281
224 /* 0x30 --> 0x64 unused */
225 #define TG3PCI_MSI_DATA 0x00000064
226 /* 0x66 --> 0x68 unused */
227 #define TG3PCI_MISC_HOST_CTRL 0x00000068
228 #define MISC_HOST_CTRL_CLEAR_INT 0x00000001
229 #define MISC_HOST_CTRL_MASK_PCI_INT 0x00000002
230 #define MISC_HOST_CTRL_BYTE_SWAP 0x00000004
231 #define MISC_HOST_CTRL_WORD_SWAP 0x00000008
232 #define MISC_HOST_CTRL_PCISTATE_RW 0x00000010
233 #define MISC_HOST_CTRL_CLKREG_RW 0x00000020
234 #define MISC_HOST_CTRL_REGWORD_SWAP 0x00000040
235 #define MISC_HOST_CTRL_INDIR_ACCESS 0x00000080
236 #define MISC_HOST_CTRL_IRQ_MASK_MODE 0x00000100
237 #define MISC_HOST_CTRL_TAGGED_STATUS 0x00000200
238 #define MISC_HOST_CTRL_CHIPREV 0xffff0000
239 #define MISC_HOST_CTRL_CHIPREV_SHIFT 16
240 #define GET_CHIP_REV_ID(MISC_HOST_CTRL) \
241 (((MISC_HOST_CTRL) & MISC_HOST_CTRL_CHIPREV) >> \
242 MISC_HOST_CTRL_CHIPREV_SHIFT)
243 #define CHIPREV_ID_5700_A0 0x7000
244 #define CHIPREV_ID_5700_A1 0x7001
245 #define CHIPREV_ID_5700_B0 0x7100
246 #define CHIPREV_ID_5700_B1 0x7101
247 #define CHIPREV_ID_5700_B3 0x7102
248 #define CHIPREV_ID_5700_ALTIMA 0x7104
249 #define CHIPREV_ID_5700_C0 0x7200
250 #define CHIPREV_ID_5701_A0 0x0000
251 #define CHIPREV_ID_5701_B0 0x0100
252 #define CHIPREV_ID_5701_B2 0x0102
253 #define CHIPREV_ID_5701_B5 0x0105
254 #define CHIPREV_ID_5703_A0 0x1000
255 #define CHIPREV_ID_5703_A1 0x1001
256 #define CHIPREV_ID_5703_A2 0x1002
257 #define CHIPREV_ID_5703_A3 0x1003
258 #define CHIPREV_ID_5704_A0 0x2000
259 #define CHIPREV_ID_5704_A1 0x2001
260 #define CHIPREV_ID_5704_A2 0x2002
261 #define CHIPREV_ID_5704_A3 0x2003
262 #define CHIPREV_ID_5705_A0 0x3000
263 #define CHIPREV_ID_5705_A1 0x3001
264 #define CHIPREV_ID_5705_A2 0x3002
265 #define CHIPREV_ID_5705_A3 0x3003
266 #define CHIPREV_ID_5750_A0 0x4000
267 #define CHIPREV_ID_5750_A1 0x4001
268 #define CHIPREV_ID_5750_A3 0x4003
269 #define CHIPREV_ID_5750_C2 0x4202
270 #define CHIPREV_ID_5752_A0_HW 0x5000
271 #define CHIPREV_ID_5752_A0 0x6000
272 #define CHIPREV_ID_5752_A1 0x6001
273 #define CHIPREV_ID_5714_A2 0x9002
274 #define CHIPREV_ID_5906_A1 0xc001
275 #define CHIPREV_ID_57780_A0 0x57780000
276 #define CHIPREV_ID_57780_A1 0x57780001
277 #define CHIPREV_ID_5717_A0 0x05717000
278 #define CHIPREV_ID_57765_A0 0x57785000
279 #define CHIPREV_ID_5719_A0 0x05719000
280 #define CHIPREV_ID_5720_A0 0x05720000
281 #define GET_ASIC_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 12)
282 #define ASIC_REV_5700 0x07
283 #define ASIC_REV_5701 0x00
284 #define ASIC_REV_5703 0x01
285 #define ASIC_REV_5704 0x02
286 #define ASIC_REV_5705 0x03
287 #define ASIC_REV_5750 0x04
288 #define ASIC_REV_5752 0x06
289 #define ASIC_REV_5780 0x08
290 #define ASIC_REV_5714 0x09
291 #define ASIC_REV_5755 0x0a
292 #define ASIC_REV_5787 0x0b
293 #define ASIC_REV_5906 0x0c
294 #define ASIC_REV_USE_PROD_ID_REG 0x0f
295 #define ASIC_REV_5784 0x5784
296 #define ASIC_REV_5761 0x5761
297 #define ASIC_REV_5785 0x5785
298 #define ASIC_REV_57780 0x57780
299 #define ASIC_REV_5717 0x5717
300 #define ASIC_REV_57765 0x57785
301 #define ASIC_REV_57766 0x57766
302 #define ASIC_REV_5719 0x5719
303 #define ASIC_REV_5720 0x5720
304 #define GET_CHIP_REV(CHIP_REV_ID) ((CHIP_REV_ID) >> 8)
305 #define CHIPREV_5700_AX 0x70
306 #define CHIPREV_5700_BX 0x71
307 #define CHIPREV_5700_CX 0x72
308 #define CHIPREV_5701_AX 0x00
309 #define CHIPREV_5703_AX 0x10
310 #define CHIPREV_5704_AX 0x20
311 #define CHIPREV_5704_BX 0x21
312 #define CHIPREV_5750_AX 0x40
313 #define CHIPREV_5750_BX 0x41
314 #define CHIPREV_5784_AX 0x57840
315 #define CHIPREV_5761_AX 0x57610
316 #define CHIPREV_57765_AX 0x577650
317 #define GET_METAL_REV(CHIP_REV_ID) ((CHIP_REV_ID) & 0xff)
318 #define METAL_REV_A0 0x00
319 #define METAL_REV_A1 0x01
320 #define METAL_REV_B0 0x00
321 #define METAL_REV_B1 0x01
322 #define METAL_REV_B2 0x02
323 #define TG3PCI_DMA_RW_CTRL 0x0000006c
324 #define DMA_RWCTRL_DIS_CACHE_ALIGNMENT 0x00000001
325 #define DMA_RWCTRL_TAGGED_STAT_WA 0x00000080
326 #define DMA_RWCTRL_CRDRDR_RDMA_MRRS_MSK 0x00000380
327 #define DMA_RWCTRL_READ_BNDRY_MASK 0x00000700
328 #define DMA_RWCTRL_READ_BNDRY_DISAB 0x00000000
329 #define DMA_RWCTRL_READ_BNDRY_16 0x00000100
330 #define DMA_RWCTRL_READ_BNDRY_128_PCIX 0x00000100
331 #define DMA_RWCTRL_READ_BNDRY_32 0x00000200
332 #define DMA_RWCTRL_READ_BNDRY_256_PCIX 0x00000200
333 #define DMA_RWCTRL_READ_BNDRY_64 0x00000300
334 #define DMA_RWCTRL_READ_BNDRY_384_PCIX 0x00000300
335 #define DMA_RWCTRL_READ_BNDRY_128 0x00000400
336 #define DMA_RWCTRL_READ_BNDRY_256 0x00000500
337 #define DMA_RWCTRL_READ_BNDRY_512 0x00000600
338 #define DMA_RWCTRL_READ_BNDRY_1024 0x00000700
339 #define DMA_RWCTRL_WRITE_BNDRY_MASK 0x00003800
340 #define DMA_RWCTRL_WRITE_BNDRY_DISAB 0x00000000
341 #define DMA_RWCTRL_WRITE_BNDRY_16 0x00000800
342 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIX 0x00000800
343 #define DMA_RWCTRL_WRITE_BNDRY_32 0x00001000
344 #define DMA_RWCTRL_WRITE_BNDRY_256_PCIX 0x00001000
345 #define DMA_RWCTRL_WRITE_BNDRY_64 0x00001800
346 #define DMA_RWCTRL_WRITE_BNDRY_384_PCIX 0x00001800
347 #define DMA_RWCTRL_WRITE_BNDRY_128 0x00002000
348 #define DMA_RWCTRL_WRITE_BNDRY_256 0x00002800
349 #define DMA_RWCTRL_WRITE_BNDRY_512 0x00003000
350 #define DMA_RWCTRL_WRITE_BNDRY_1024 0x00003800
351 #define DMA_RWCTRL_ONE_DMA 0x00004000
352 #define DMA_RWCTRL_READ_WATER 0x00070000
353 #define DMA_RWCTRL_READ_WATER_SHIFT 16
354 #define DMA_RWCTRL_WRITE_WATER 0x00380000
355 #define DMA_RWCTRL_WRITE_WATER_SHIFT 19
356 #define DMA_RWCTRL_USE_MEM_READ_MULT 0x00400000
357 #define DMA_RWCTRL_ASSERT_ALL_BE 0x00800000
358 #define DMA_RWCTRL_PCI_READ_CMD 0x0f000000
359 #define DMA_RWCTRL_PCI_READ_CMD_SHIFT 24
360 #define DMA_RWCTRL_PCI_WRITE_CMD 0xf0000000
361 #define DMA_RWCTRL_PCI_WRITE_CMD_SHIFT 28
362 #define DMA_RWCTRL_WRITE_BNDRY_64_PCIE 0x10000000
363 #define DMA_RWCTRL_WRITE_BNDRY_128_PCIE 0x30000000
364 #define DMA_RWCTRL_WRITE_BNDRY_DISAB_PCIE 0x70000000
365 #define TG3PCI_PCISTATE 0x00000070
366 #define PCISTATE_FORCE_RESET 0x00000001
367 #define PCISTATE_INT_NOT_ACTIVE 0x00000002
368 #define PCISTATE_CONV_PCI_MODE 0x00000004
369 #define PCISTATE_BUS_SPEED_HIGH 0x00000008
370 #define PCISTATE_BUS_32BIT 0x00000010
371 #define PCISTATE_ROM_ENABLE 0x00000020
372 #define PCISTATE_ROM_RETRY_ENABLE 0x00000040
373 #define PCISTATE_FLAT_VIEW 0x00000100
374 #define PCISTATE_RETRY_SAME_DMA 0x00002000
375 #define PCISTATE_ALLOW_APE_CTLSPC_WR 0x00010000
376 #define PCISTATE_ALLOW_APE_SHMEM_WR 0x00020000
377 #define PCISTATE_ALLOW_APE_PSPACE_WR 0x00040000
378 #define TG3PCI_CLOCK_CTRL 0x00000074
379 #define CLOCK_CTRL_CORECLK_DISABLE 0x00000200
380 #define CLOCK_CTRL_RXCLK_DISABLE 0x00000400
381 #define CLOCK_CTRL_TXCLK_DISABLE 0x00000800
382 #define CLOCK_CTRL_ALTCLK 0x00001000
383 #define CLOCK_CTRL_PWRDOWN_PLL133 0x00008000
384 #define CLOCK_CTRL_44MHZ_CORE 0x00040000
385 #define CLOCK_CTRL_625_CORE 0x00100000
386 #define CLOCK_CTRL_FORCE_CLKRUN 0x00200000
387 #define CLOCK_CTRL_CLKRUN_OENABLE 0x00400000
388 #define CLOCK_CTRL_DELAY_PCI_GRANT 0x80000000
389 #define TG3PCI_REG_BASE_ADDR 0x00000078
390 #define TG3PCI_MEM_WIN_BASE_ADDR 0x0000007c
391 #define TG3PCI_REG_DATA 0x00000080
392 #define TG3PCI_MEM_WIN_DATA 0x00000084
393 #define TG3PCI_MISC_LOCAL_CTRL 0x00000090
394 /* 0x94 --> 0x98 unused */
395 #define TG3PCI_STD_RING_PROD_IDX 0x00000098 /* 64-bit */
396 #define TG3PCI_RCV_RET_RING_CON_IDX 0x000000a0 /* 64-bit */
397 /* 0xa8 --> 0xb8 unused */
398 #define TG3PCI_DUAL_MAC_CTRL 0x000000b8
399 #define DUAL_MAC_CTRL_CH_MASK 0x00000003
400 #define DUAL_MAC_CTRL_ID 0x00000004
401 #define TG3PCI_PRODID_ASICREV 0x000000bc
402 #define PROD_ID_ASIC_REV_MASK 0x0fffffff
403 /* 0xc0 --> 0xf4 unused */
405 #define TG3PCI_GEN2_PRODID_ASICREV 0x000000f4
406 #define TG3PCI_GEN15_PRODID_ASICREV 0x000000fc
407 /* 0xf8 --> 0x200 unused */
409 #define TG3_CORR_ERR_STAT 0x00000110
410 #define TG3_CORR_ERR_STAT_CLEAR 0xffffffff
411 /* 0x114 --> 0x200 unused */
413 /* Mailbox registers */
414 #define MAILBOX_INTERRUPT_0 0x00000200 /* 64-bit */
415 #define MAILBOX_INTERRUPT_1 0x00000208 /* 64-bit */
416 #define MAILBOX_INTERRUPT_2 0x00000210 /* 64-bit */
417 #define MAILBOX_INTERRUPT_3 0x00000218 /* 64-bit */
418 #define MAILBOX_GENERAL_0 0x00000220 /* 64-bit */
419 #define MAILBOX_GENERAL_1 0x00000228 /* 64-bit */
420 #define MAILBOX_GENERAL_2 0x00000230 /* 64-bit */
421 #define MAILBOX_GENERAL_3 0x00000238 /* 64-bit */
422 #define MAILBOX_GENERAL_4 0x00000240 /* 64-bit */
423 #define MAILBOX_GENERAL_5 0x00000248 /* 64-bit */
424 #define MAILBOX_GENERAL_6 0x00000250 /* 64-bit */
425 #define MAILBOX_GENERAL_7 0x00000258 /* 64-bit */
426 #define MAILBOX_RELOAD_STAT 0x00000260 /* 64-bit */
427 #define MAILBOX_RCV_STD_PROD_IDX 0x00000268 /* 64-bit */
428 #define TG3_RX_STD_PROD_IDX_REG (MAILBOX_RCV_STD_PROD_IDX + \
430 #define MAILBOX_RCV_JUMBO_PROD_IDX 0x00000270 /* 64-bit */
431 #define TG3_RX_JMB_PROD_IDX_REG (MAILBOX_RCV_JUMBO_PROD_IDX + \
433 #define MAILBOX_RCV_MINI_PROD_IDX 0x00000278 /* 64-bit */
434 #define MAILBOX_RCVRET_CON_IDX_0 0x00000280 /* 64-bit */
435 #define MAILBOX_RCVRET_CON_IDX_1 0x00000288 /* 64-bit */
436 #define MAILBOX_RCVRET_CON_IDX_2 0x00000290 /* 64-bit */
437 #define MAILBOX_RCVRET_CON_IDX_3 0x00000298 /* 64-bit */
438 #define MAILBOX_RCVRET_CON_IDX_4 0x000002a0 /* 64-bit */
439 #define MAILBOX_RCVRET_CON_IDX_5 0x000002a8 /* 64-bit */
440 #define MAILBOX_RCVRET_CON_IDX_6 0x000002b0 /* 64-bit */
441 #define MAILBOX_RCVRET_CON_IDX_7 0x000002b8 /* 64-bit */
442 #define MAILBOX_RCVRET_CON_IDX_8 0x000002c0 /* 64-bit */
443 #define MAILBOX_RCVRET_CON_IDX_9 0x000002c8 /* 64-bit */
444 #define MAILBOX_RCVRET_CON_IDX_10 0x000002d0 /* 64-bit */
445 #define MAILBOX_RCVRET_CON_IDX_11 0x000002d8 /* 64-bit */
446 #define MAILBOX_RCVRET_CON_IDX_12 0x000002e0 /* 64-bit */
447 #define MAILBOX_RCVRET_CON_IDX_13 0x000002e8 /* 64-bit */
448 #define MAILBOX_RCVRET_CON_IDX_14 0x000002f0 /* 64-bit */
449 #define MAILBOX_RCVRET_CON_IDX_15 0x000002f8 /* 64-bit */
450 #define MAILBOX_SNDHOST_PROD_IDX_0 0x00000300 /* 64-bit */
451 #define MAILBOX_SNDHOST_PROD_IDX_1 0x00000308 /* 64-bit */
452 #define MAILBOX_SNDHOST_PROD_IDX_2 0x00000310 /* 64-bit */
453 #define MAILBOX_SNDHOST_PROD_IDX_3 0x00000318 /* 64-bit */
454 #define MAILBOX_SNDHOST_PROD_IDX_4 0x00000320 /* 64-bit */
455 #define MAILBOX_SNDHOST_PROD_IDX_5 0x00000328 /* 64-bit */
456 #define MAILBOX_SNDHOST_PROD_IDX_6 0x00000330 /* 64-bit */
457 #define MAILBOX_SNDHOST_PROD_IDX_7 0x00000338 /* 64-bit */
458 #define MAILBOX_SNDHOST_PROD_IDX_8 0x00000340 /* 64-bit */
459 #define MAILBOX_SNDHOST_PROD_IDX_9 0x00000348 /* 64-bit */
460 #define MAILBOX_SNDHOST_PROD_IDX_10 0x00000350 /* 64-bit */
461 #define MAILBOX_SNDHOST_PROD_IDX_11 0x00000358 /* 64-bit */
462 #define MAILBOX_SNDHOST_PROD_IDX_12 0x00000360 /* 64-bit */
463 #define MAILBOX_SNDHOST_PROD_IDX_13 0x00000368 /* 64-bit */
464 #define MAILBOX_SNDHOST_PROD_IDX_14 0x00000370 /* 64-bit */
465 #define MAILBOX_SNDHOST_PROD_IDX_15 0x00000378 /* 64-bit */
466 #define MAILBOX_SNDNIC_PROD_IDX_0 0x00000380 /* 64-bit */
467 #define MAILBOX_SNDNIC_PROD_IDX_1 0x00000388 /* 64-bit */
468 #define MAILBOX_SNDNIC_PROD_IDX_2 0x00000390 /* 64-bit */
469 #define MAILBOX_SNDNIC_PROD_IDX_3 0x00000398 /* 64-bit */
470 #define MAILBOX_SNDNIC_PROD_IDX_4 0x000003a0 /* 64-bit */
471 #define MAILBOX_SNDNIC_PROD_IDX_5 0x000003a8 /* 64-bit */
472 #define MAILBOX_SNDNIC_PROD_IDX_6 0x000003b0 /* 64-bit */
473 #define MAILBOX_SNDNIC_PROD_IDX_7 0x000003b8 /* 64-bit */
474 #define MAILBOX_SNDNIC_PROD_IDX_8 0x000003c0 /* 64-bit */
475 #define MAILBOX_SNDNIC_PROD_IDX_9 0x000003c8 /* 64-bit */
476 #define MAILBOX_SNDNIC_PROD_IDX_10 0x000003d0 /* 64-bit */
477 #define MAILBOX_SNDNIC_PROD_IDX_11 0x000003d8 /* 64-bit */
478 #define MAILBOX_SNDNIC_PROD_IDX_12 0x000003e0 /* 64-bit */
479 #define MAILBOX_SNDNIC_PROD_IDX_13 0x000003e8 /* 64-bit */
480 #define MAILBOX_SNDNIC_PROD_IDX_14 0x000003f0 /* 64-bit */
481 #define MAILBOX_SNDNIC_PROD_IDX_15 0x000003f8 /* 64-bit */
483 /* MAC control registers */
484 #define MAC_MODE 0x00000400
485 #define MAC_MODE_RESET 0x00000001
486 #define MAC_MODE_HALF_DUPLEX 0x00000002
487 #define MAC_MODE_PORT_MODE_MASK 0x0000000c
488 #define MAC_MODE_PORT_MODE_TBI 0x0000000c
489 #define MAC_MODE_PORT_MODE_GMII 0x00000008
490 #define MAC_MODE_PORT_MODE_MII 0x00000004
491 #define MAC_MODE_PORT_MODE_NONE 0x00000000
492 #define MAC_MODE_PORT_INT_LPBACK 0x00000010
493 #define MAC_MODE_TAGGED_MAC_CTRL 0x00000080
494 #define MAC_MODE_TX_BURSTING 0x00000100
495 #define MAC_MODE_MAX_DEFER 0x00000200
496 #define MAC_MODE_LINK_POLARITY 0x00000400
497 #define MAC_MODE_RXSTAT_ENABLE 0x00000800
498 #define MAC_MODE_RXSTAT_CLEAR 0x00001000
499 #define MAC_MODE_RXSTAT_FLUSH 0x00002000
500 #define MAC_MODE_TXSTAT_ENABLE 0x00004000
501 #define MAC_MODE_TXSTAT_CLEAR 0x00008000
502 #define MAC_MODE_TXSTAT_FLUSH 0x00010000
503 #define MAC_MODE_SEND_CONFIGS 0x00020000
504 #define MAC_MODE_MAGIC_PKT_ENABLE 0x00040000
505 #define MAC_MODE_ACPI_ENABLE 0x00080000
506 #define MAC_MODE_MIP_ENABLE 0x00100000
507 #define MAC_MODE_TDE_ENABLE 0x00200000
508 #define MAC_MODE_RDE_ENABLE 0x00400000
509 #define MAC_MODE_FHDE_ENABLE 0x00800000
510 #define MAC_MODE_KEEP_FRAME_IN_WOL 0x01000000
511 #define MAC_MODE_APE_RX_EN 0x08000000
512 #define MAC_MODE_APE_TX_EN 0x10000000
513 #define MAC_STATUS 0x00000404
514 #define MAC_STATUS_PCS_SYNCED 0x00000001
515 #define MAC_STATUS_SIGNAL_DET 0x00000002
516 #define MAC_STATUS_RCVD_CFG 0x00000004
517 #define MAC_STATUS_CFG_CHANGED 0x00000008
518 #define MAC_STATUS_SYNC_CHANGED 0x00000010
519 #define MAC_STATUS_PORT_DEC_ERR 0x00000400
520 #define MAC_STATUS_LNKSTATE_CHANGED 0x00001000
521 #define MAC_STATUS_MI_COMPLETION 0x00400000
522 #define MAC_STATUS_MI_INTERRUPT 0x00800000
523 #define MAC_STATUS_AP_ERROR 0x01000000
524 #define MAC_STATUS_ODI_ERROR 0x02000000
525 #define MAC_STATUS_RXSTAT_OVERRUN 0x04000000
526 #define MAC_STATUS_TXSTAT_OVERRUN 0x08000000
527 #define MAC_EVENT 0x00000408
528 #define MAC_EVENT_PORT_DECODE_ERR 0x00000400
529 #define MAC_EVENT_LNKSTATE_CHANGED 0x00001000
530 #define MAC_EVENT_MI_COMPLETION 0x00400000
531 #define MAC_EVENT_MI_INTERRUPT 0x00800000
532 #define MAC_EVENT_AP_ERROR 0x01000000
533 #define MAC_EVENT_ODI_ERROR 0x02000000
534 #define MAC_EVENT_RXSTAT_OVERRUN 0x04000000
535 #define MAC_EVENT_TXSTAT_OVERRUN 0x08000000
536 #define MAC_LED_CTRL 0x0000040c
537 #define LED_CTRL_LNKLED_OVERRIDE 0x00000001
538 #define LED_CTRL_1000MBPS_ON 0x00000002
539 #define LED_CTRL_100MBPS_ON 0x00000004
540 #define LED_CTRL_10MBPS_ON 0x00000008
541 #define LED_CTRL_TRAFFIC_OVERRIDE 0x00000010
542 #define LED_CTRL_TRAFFIC_BLINK 0x00000020
543 #define LED_CTRL_TRAFFIC_LED 0x00000040
544 #define LED_CTRL_1000MBPS_STATUS 0x00000080
545 #define LED_CTRL_100MBPS_STATUS 0x00000100
546 #define LED_CTRL_10MBPS_STATUS 0x00000200
547 #define LED_CTRL_TRAFFIC_STATUS 0x00000400
548 #define LED_CTRL_MODE_MAC 0x00000000
549 #define LED_CTRL_MODE_PHY_1 0x00000800
550 #define LED_CTRL_MODE_PHY_2 0x00001000
551 #define LED_CTRL_MODE_SHASTA_MAC 0x00002000
552 #define LED_CTRL_MODE_SHARED 0x00004000
553 #define LED_CTRL_MODE_COMBO 0x00008000
554 #define LED_CTRL_BLINK_RATE_MASK 0x7ff80000
555 #define LED_CTRL_BLINK_RATE_SHIFT 19
556 #define LED_CTRL_BLINK_PER_OVERRIDE 0x00080000
557 #define LED_CTRL_BLINK_RATE_OVERRIDE 0x80000000
558 #define MAC_ADDR_0_HIGH 0x00000410 /* upper 2 bytes */
559 #define MAC_ADDR_0_LOW 0x00000414 /* lower 4 bytes */
560 #define MAC_ADDR_1_HIGH 0x00000418 /* upper 2 bytes */
561 #define MAC_ADDR_1_LOW 0x0000041c /* lower 4 bytes */
562 #define MAC_ADDR_2_HIGH 0x00000420 /* upper 2 bytes */
563 #define MAC_ADDR_2_LOW 0x00000424 /* lower 4 bytes */
564 #define MAC_ADDR_3_HIGH 0x00000428 /* upper 2 bytes */
565 #define MAC_ADDR_3_LOW 0x0000042c /* lower 4 bytes */
566 #define MAC_ACPI_MBUF_PTR 0x00000430
567 #define MAC_ACPI_LEN_OFFSET 0x00000434
568 #define ACPI_LENOFF_LEN_MASK 0x0000ffff
569 #define ACPI_LENOFF_LEN_SHIFT 0
570 #define ACPI_LENOFF_OFF_MASK 0x0fff0000
571 #define ACPI_LENOFF_OFF_SHIFT 16
572 #define MAC_TX_BACKOFF_SEED 0x00000438
573 #define TX_BACKOFF_SEED_MASK 0x000003ff
574 #define MAC_RX_MTU_SIZE 0x0000043c
575 #define RX_MTU_SIZE_MASK 0x0000ffff
576 #define MAC_PCS_TEST 0x00000440
577 #define PCS_TEST_PATTERN_MASK 0x000fffff
578 #define PCS_TEST_PATTERN_SHIFT 0
579 #define PCS_TEST_ENABLE 0x00100000
580 #define MAC_TX_AUTO_NEG 0x00000444
581 #define TX_AUTO_NEG_MASK 0x0000ffff
582 #define TX_AUTO_NEG_SHIFT 0
583 #define MAC_RX_AUTO_NEG 0x00000448
584 #define RX_AUTO_NEG_MASK 0x0000ffff
585 #define RX_AUTO_NEG_SHIFT 0
586 #define MAC_MI_COM 0x0000044c
587 #define MI_COM_CMD_MASK 0x0c000000
588 #define MI_COM_CMD_WRITE 0x04000000
589 #define MI_COM_CMD_READ 0x08000000
590 #define MI_COM_READ_FAILED 0x10000000
591 #define MI_COM_START 0x20000000
592 #define MI_COM_BUSY 0x20000000
593 #define MI_COM_PHY_ADDR_MASK 0x03e00000
594 #define MI_COM_PHY_ADDR_SHIFT 21
595 #define MI_COM_REG_ADDR_MASK 0x001f0000
596 #define MI_COM_REG_ADDR_SHIFT 16
597 #define MI_COM_DATA_MASK 0x0000ffff
598 #define MAC_MI_STAT 0x00000450
599 #define MAC_MI_STAT_LNKSTAT_ATTN_ENAB 0x00000001
600 #define MAC_MI_STAT_10MBPS_MODE 0x00000002
601 #define MAC_MI_MODE 0x00000454
602 #define MAC_MI_MODE_CLK_10MHZ 0x00000001
603 #define MAC_MI_MODE_SHORT_PREAMBLE 0x00000002
604 #define MAC_MI_MODE_AUTO_POLL 0x00000010
605 #define MAC_MI_MODE_500KHZ_CONST 0x00008000
606 #define MAC_MI_MODE_BASE 0x000c0000 /* XXX magic values XXX */
607 #define MAC_AUTO_POLL_STATUS 0x00000458
608 #define MAC_AUTO_POLL_ERROR 0x00000001
609 #define MAC_TX_MODE 0x0000045c
610 #define TX_MODE_RESET 0x00000001
611 #define TX_MODE_ENABLE 0x00000002
612 #define TX_MODE_FLOW_CTRL_ENABLE 0x00000010
613 #define TX_MODE_BIG_BCKOFF_ENABLE 0x00000020
614 #define TX_MODE_LONG_PAUSE_ENABLE 0x00000040
615 #define TX_MODE_MBUF_LOCKUP_FIX 0x00000100
616 #define TX_MODE_JMB_FRM_LEN 0x00400000
617 #define TX_MODE_CNT_DN_MODE 0x00800000
618 #define MAC_TX_STATUS 0x00000460
619 #define TX_STATUS_XOFFED 0x00000001
620 #define TX_STATUS_SENT_XOFF 0x00000002
621 #define TX_STATUS_SENT_XON 0x00000004
622 #define TX_STATUS_LINK_UP 0x00000008
623 #define TX_STATUS_ODI_UNDERRUN 0x00000010
624 #define TX_STATUS_ODI_OVERRUN 0x00000020
625 #define MAC_TX_LENGTHS 0x00000464
626 #define TX_LENGTHS_SLOT_TIME_MASK 0x000000ff
627 #define TX_LENGTHS_SLOT_TIME_SHIFT 0
628 #define TX_LENGTHS_IPG_MASK 0x00000f00
629 #define TX_LENGTHS_IPG_SHIFT 8
630 #define TX_LENGTHS_IPG_CRS_MASK 0x00003000
631 #define TX_LENGTHS_IPG_CRS_SHIFT 12
632 #define TX_LENGTHS_JMB_FRM_LEN_MSK 0x00ff0000
633 #define TX_LENGTHS_CNT_DWN_VAL_MSK 0xff000000
634 #define MAC_RX_MODE 0x00000468
635 #define RX_MODE_RESET 0x00000001
636 #define RX_MODE_ENABLE 0x00000002
637 #define RX_MODE_FLOW_CTRL_ENABLE 0x00000004
638 #define RX_MODE_KEEP_MAC_CTRL 0x00000008
639 #define RX_MODE_KEEP_PAUSE 0x00000010
640 #define RX_MODE_ACCEPT_OVERSIZED 0x00000020
641 #define RX_MODE_ACCEPT_RUNTS 0x00000040
642 #define RX_MODE_LEN_CHECK 0x00000080
643 #define RX_MODE_PROMISC 0x00000100
644 #define RX_MODE_NO_CRC_CHECK 0x00000200
645 #define RX_MODE_KEEP_VLAN_TAG 0x00000400
646 #define RX_MODE_RSS_IPV4_HASH_EN 0x00010000
647 #define RX_MODE_RSS_TCP_IPV4_HASH_EN 0x00020000
648 #define RX_MODE_RSS_IPV6_HASH_EN 0x00040000
649 #define RX_MODE_RSS_TCP_IPV6_HASH_EN 0x00080000
650 #define RX_MODE_RSS_ITBL_HASH_BITS_7 0x00700000
651 #define RX_MODE_RSS_ENABLE 0x00800000
652 #define RX_MODE_IPV6_CSUM_ENABLE 0x01000000
653 #define MAC_RX_STATUS 0x0000046c
654 #define RX_STATUS_REMOTE_TX_XOFFED 0x00000001
655 #define RX_STATUS_XOFF_RCVD 0x00000002
656 #define RX_STATUS_XON_RCVD 0x00000004
657 #define MAC_HASH_REG_0 0x00000470
658 #define MAC_HASH_REG_1 0x00000474
659 #define MAC_HASH_REG_2 0x00000478
660 #define MAC_HASH_REG_3 0x0000047c
661 #define MAC_RCV_RULE_0 0x00000480
662 #define MAC_RCV_VALUE_0 0x00000484
663 #define MAC_RCV_RULE_1 0x00000488
664 #define MAC_RCV_VALUE_1 0x0000048c
665 #define MAC_RCV_RULE_2 0x00000490
666 #define MAC_RCV_VALUE_2 0x00000494
667 #define MAC_RCV_RULE_3 0x00000498
668 #define MAC_RCV_VALUE_3 0x0000049c
669 #define MAC_RCV_RULE_4 0x000004a0
670 #define MAC_RCV_VALUE_4 0x000004a4
671 #define MAC_RCV_RULE_5 0x000004a8
672 #define MAC_RCV_VALUE_5 0x000004ac
673 #define MAC_RCV_RULE_6 0x000004b0
674 #define MAC_RCV_VALUE_6 0x000004b4
675 #define MAC_RCV_RULE_7 0x000004b8
676 #define MAC_RCV_VALUE_7 0x000004bc
677 #define MAC_RCV_RULE_8 0x000004c0
678 #define MAC_RCV_VALUE_8 0x000004c4
679 #define MAC_RCV_RULE_9 0x000004c8
680 #define MAC_RCV_VALUE_9 0x000004cc
681 #define MAC_RCV_RULE_10 0x000004d0
682 #define MAC_RCV_VALUE_10 0x000004d4
683 #define MAC_RCV_RULE_11 0x000004d8
684 #define MAC_RCV_VALUE_11 0x000004dc
685 #define MAC_RCV_RULE_12 0x000004e0
686 #define MAC_RCV_VALUE_12 0x000004e4
687 #define MAC_RCV_RULE_13 0x000004e8
688 #define MAC_RCV_VALUE_13 0x000004ec
689 #define MAC_RCV_RULE_14 0x000004f0
690 #define MAC_RCV_VALUE_14 0x000004f4
691 #define MAC_RCV_RULE_15 0x000004f8
692 #define MAC_RCV_VALUE_15 0x000004fc
693 #define RCV_RULE_DISABLE_MASK 0x7fffffff
694 #define MAC_RCV_RULE_CFG 0x00000500
695 #define RCV_RULE_CFG_DEFAULT_CLASS 0x00000008
696 #define MAC_LOW_WMARK_MAX_RX_FRAME 0x00000504
697 /* 0x508 --> 0x520 unused */
698 #define MAC_HASHREGU_0 0x00000520
699 #define MAC_HASHREGU_1 0x00000524
700 #define MAC_HASHREGU_2 0x00000528
701 #define MAC_HASHREGU_3 0x0000052c
702 #define MAC_EXTADDR_0_HIGH 0x00000530
703 #define MAC_EXTADDR_0_LOW 0x00000534
704 #define MAC_EXTADDR_1_HIGH 0x00000538
705 #define MAC_EXTADDR_1_LOW 0x0000053c
706 #define MAC_EXTADDR_2_HIGH 0x00000540
707 #define MAC_EXTADDR_2_LOW 0x00000544
708 #define MAC_EXTADDR_3_HIGH 0x00000548
709 #define MAC_EXTADDR_3_LOW 0x0000054c
710 #define MAC_EXTADDR_4_HIGH 0x00000550
711 #define MAC_EXTADDR_4_LOW 0x00000554
712 #define MAC_EXTADDR_5_HIGH 0x00000558
713 #define MAC_EXTADDR_5_LOW 0x0000055c
714 #define MAC_EXTADDR_6_HIGH 0x00000560
715 #define MAC_EXTADDR_6_LOW 0x00000564
716 #define MAC_EXTADDR_7_HIGH 0x00000568
717 #define MAC_EXTADDR_7_LOW 0x0000056c
718 #define MAC_EXTADDR_8_HIGH 0x00000570
719 #define MAC_EXTADDR_8_LOW 0x00000574
720 #define MAC_EXTADDR_9_HIGH 0x00000578
721 #define MAC_EXTADDR_9_LOW 0x0000057c
722 #define MAC_EXTADDR_10_HIGH 0x00000580
723 #define MAC_EXTADDR_10_LOW 0x00000584
724 #define MAC_EXTADDR_11_HIGH 0x00000588
725 #define MAC_EXTADDR_11_LOW 0x0000058c
726 #define MAC_SERDES_CFG 0x00000590
727 #define MAC_SERDES_CFG_EDGE_SELECT 0x00001000
728 #define MAC_SERDES_STAT 0x00000594
729 /* 0x598 --> 0x5a0 unused */
730 #define MAC_PHYCFG1 0x000005a0
731 #define MAC_PHYCFG1_RGMII_INT 0x00000001
732 #define MAC_PHYCFG1_RXCLK_TO_MASK 0x00001ff0
733 #define MAC_PHYCFG1_RXCLK_TIMEOUT 0x00001000
734 #define MAC_PHYCFG1_TXCLK_TO_MASK 0x01ff0000
735 #define MAC_PHYCFG1_TXCLK_TIMEOUT 0x01000000
736 #define MAC_PHYCFG1_RGMII_EXT_RX_DEC 0x02000000
737 #define MAC_PHYCFG1_RGMII_SND_STAT_EN 0x04000000
738 #define MAC_PHYCFG1_TXC_DRV 0x20000000
739 #define MAC_PHYCFG2 0x000005a4
740 #define MAC_PHYCFG2_INBAND_ENABLE 0x00000001
741 #define MAC_PHYCFG2_EMODE_MASK_MASK 0x000001c0
742 #define MAC_PHYCFG2_EMODE_MASK_AC131 0x000000c0
743 #define MAC_PHYCFG2_EMODE_MASK_50610 0x00000100
744 #define MAC_PHYCFG2_EMODE_MASK_RT8211 0x00000000
745 #define MAC_PHYCFG2_EMODE_MASK_RT8201 0x000001c0
746 #define MAC_PHYCFG2_EMODE_COMP_MASK 0x00000e00
747 #define MAC_PHYCFG2_EMODE_COMP_AC131 0x00000600
748 #define MAC_PHYCFG2_EMODE_COMP_50610 0x00000400
749 #define MAC_PHYCFG2_EMODE_COMP_RT8211 0x00000800
750 #define MAC_PHYCFG2_EMODE_COMP_RT8201 0x00000000
751 #define MAC_PHYCFG2_FMODE_MASK_MASK 0x00007000
752 #define MAC_PHYCFG2_FMODE_MASK_AC131 0x00006000
753 #define MAC_PHYCFG2_FMODE_MASK_50610 0x00004000
754 #define MAC_PHYCFG2_FMODE_MASK_RT8211 0x00000000
755 #define MAC_PHYCFG2_FMODE_MASK_RT8201 0x00007000
756 #define MAC_PHYCFG2_FMODE_COMP_MASK 0x00038000
757 #define MAC_PHYCFG2_FMODE_COMP_AC131 0x00030000
758 #define MAC_PHYCFG2_FMODE_COMP_50610 0x00008000
759 #define MAC_PHYCFG2_FMODE_COMP_RT8211 0x00038000
760 #define MAC_PHYCFG2_FMODE_COMP_RT8201 0x00000000
761 #define MAC_PHYCFG2_GMODE_MASK_MASK 0x001c0000
762 #define MAC_PHYCFG2_GMODE_MASK_AC131 0x001c0000
763 #define MAC_PHYCFG2_GMODE_MASK_50610 0x00100000
764 #define MAC_PHYCFG2_GMODE_MASK_RT8211 0x00000000
765 #define MAC_PHYCFG2_GMODE_MASK_RT8201 0x001c0000
766 #define MAC_PHYCFG2_GMODE_COMP_MASK 0x00e00000
767 #define MAC_PHYCFG2_GMODE_COMP_AC131 0x00e00000
768 #define MAC_PHYCFG2_GMODE_COMP_50610 0x00000000
769 #define MAC_PHYCFG2_GMODE_COMP_RT8211 0x00200000
770 #define MAC_PHYCFG2_GMODE_COMP_RT8201 0x00000000
771 #define MAC_PHYCFG2_ACT_MASK_MASK 0x03000000
772 #define MAC_PHYCFG2_ACT_MASK_AC131 0x03000000
773 #define MAC_PHYCFG2_ACT_MASK_50610 0x01000000
774 #define MAC_PHYCFG2_ACT_MASK_RT8211 0x03000000
775 #define MAC_PHYCFG2_ACT_MASK_RT8201 0x01000000
776 #define MAC_PHYCFG2_ACT_COMP_MASK 0x0c000000
777 #define MAC_PHYCFG2_ACT_COMP_AC131 0x00000000
778 #define MAC_PHYCFG2_ACT_COMP_50610 0x00000000
779 #define MAC_PHYCFG2_ACT_COMP_RT8211 0x00000000
780 #define MAC_PHYCFG2_ACT_COMP_RT8201 0x08000000
781 #define MAC_PHYCFG2_QUAL_MASK_MASK 0x30000000
782 #define MAC_PHYCFG2_QUAL_MASK_AC131 0x30000000
783 #define MAC_PHYCFG2_QUAL_MASK_50610 0x30000000
784 #define MAC_PHYCFG2_QUAL_MASK_RT8211 0x30000000
785 #define MAC_PHYCFG2_QUAL_MASK_RT8201 0x30000000
786 #define MAC_PHYCFG2_QUAL_COMP_MASK 0xc0000000
787 #define MAC_PHYCFG2_QUAL_COMP_AC131 0x00000000
788 #define MAC_PHYCFG2_QUAL_COMP_50610 0x00000000
789 #define MAC_PHYCFG2_QUAL_COMP_RT8211 0x00000000
790 #define MAC_PHYCFG2_QUAL_COMP_RT8201 0x00000000
791 #define MAC_PHYCFG2_50610_LED_MODES \
792 (MAC_PHYCFG2_EMODE_MASK_50610 | \
793 MAC_PHYCFG2_EMODE_COMP_50610 | \
794 MAC_PHYCFG2_FMODE_MASK_50610 | \
795 MAC_PHYCFG2_FMODE_COMP_50610 | \
796 MAC_PHYCFG2_GMODE_MASK_50610 | \
797 MAC_PHYCFG2_GMODE_COMP_50610 | \
798 MAC_PHYCFG2_ACT_MASK_50610 | \
799 MAC_PHYCFG2_ACT_COMP_50610 | \
800 MAC_PHYCFG2_QUAL_MASK_50610 | \
801 MAC_PHYCFG2_QUAL_COMP_50610)
802 #define MAC_PHYCFG2_AC131_LED_MODES \
803 (MAC_PHYCFG2_EMODE_MASK_AC131 | \
804 MAC_PHYCFG2_EMODE_COMP_AC131 | \
805 MAC_PHYCFG2_FMODE_MASK_AC131 | \
806 MAC_PHYCFG2_FMODE_COMP_AC131 | \
807 MAC_PHYCFG2_GMODE_MASK_AC131 | \
808 MAC_PHYCFG2_GMODE_COMP_AC131 | \
809 MAC_PHYCFG2_ACT_MASK_AC131 | \
810 MAC_PHYCFG2_ACT_COMP_AC131 | \
811 MAC_PHYCFG2_QUAL_MASK_AC131 | \
812 MAC_PHYCFG2_QUAL_COMP_AC131)
813 #define MAC_PHYCFG2_RTL8211C_LED_MODES \
814 (MAC_PHYCFG2_EMODE_MASK_RT8211 | \
815 MAC_PHYCFG2_EMODE_COMP_RT8211 | \
816 MAC_PHYCFG2_FMODE_MASK_RT8211 | \
817 MAC_PHYCFG2_FMODE_COMP_RT8211 | \
818 MAC_PHYCFG2_GMODE_MASK_RT8211 | \
819 MAC_PHYCFG2_GMODE_COMP_RT8211 | \
820 MAC_PHYCFG2_ACT_MASK_RT8211 | \
821 MAC_PHYCFG2_ACT_COMP_RT8211 | \
822 MAC_PHYCFG2_QUAL_MASK_RT8211 | \
823 MAC_PHYCFG2_QUAL_COMP_RT8211)
824 #define MAC_PHYCFG2_RTL8201E_LED_MODES \
825 (MAC_PHYCFG2_EMODE_MASK_RT8201 | \
826 MAC_PHYCFG2_EMODE_COMP_RT8201 | \
827 MAC_PHYCFG2_FMODE_MASK_RT8201 | \
828 MAC_PHYCFG2_FMODE_COMP_RT8201 | \
829 MAC_PHYCFG2_GMODE_MASK_RT8201 | \
830 MAC_PHYCFG2_GMODE_COMP_RT8201 | \
831 MAC_PHYCFG2_ACT_MASK_RT8201 | \
832 MAC_PHYCFG2_ACT_COMP_RT8201 | \
833 MAC_PHYCFG2_QUAL_MASK_RT8201 | \
834 MAC_PHYCFG2_QUAL_COMP_RT8201)
835 #define MAC_EXT_RGMII_MODE 0x000005a8
836 #define MAC_RGMII_MODE_TX_ENABLE 0x00000001
837 #define MAC_RGMII_MODE_TX_LOWPWR 0x00000002
838 #define MAC_RGMII_MODE_TX_RESET 0x00000004
839 #define MAC_RGMII_MODE_RX_INT_B 0x00000100
840 #define MAC_RGMII_MODE_RX_QUALITY 0x00000200
841 #define MAC_RGMII_MODE_RX_ACTIVITY 0x00000400
842 #define MAC_RGMII_MODE_RX_ENG_DET 0x00000800
843 /* 0x5ac --> 0x5b0 unused */
844 #define SERDES_RX_CTRL 0x000005b0 /* 5780/5714 only */
845 #define SERDES_RX_SIG_DETECT 0x00000400
846 #define SG_DIG_CTRL 0x000005b0
847 #define SG_DIG_USING_HW_AUTONEG 0x80000000
848 #define SG_DIG_SOFT_RESET 0x40000000
849 #define SG_DIG_DISABLE_LINKRDY 0x20000000
850 #define SG_DIG_CRC16_CLEAR_N 0x01000000
851 #define SG_DIG_EN10B 0x00800000
852 #define SG_DIG_CLEAR_STATUS 0x00400000
853 #define SG_DIG_LOCAL_DUPLEX_STATUS 0x00200000
854 #define SG_DIG_LOCAL_LINK_STATUS 0x00100000
855 #define SG_DIG_SPEED_STATUS_MASK 0x000c0000
856 #define SG_DIG_SPEED_STATUS_SHIFT 18
857 #define SG_DIG_JUMBO_PACKET_DISABLE 0x00020000
858 #define SG_DIG_RESTART_AUTONEG 0x00010000
859 #define SG_DIG_FIBER_MODE 0x00008000
860 #define SG_DIG_REMOTE_FAULT_MASK 0x00006000
861 #define SG_DIG_PAUSE_MASK 0x00001800
862 #define SG_DIG_PAUSE_CAP 0x00000800
863 #define SG_DIG_ASYM_PAUSE 0x00001000
864 #define SG_DIG_GBIC_ENABLE 0x00000400
865 #define SG_DIG_CHECK_END_ENABLE 0x00000200
866 #define SG_DIG_SGMII_AUTONEG_TIMER 0x00000100
867 #define SG_DIG_CLOCK_PHASE_SELECT 0x00000080
868 #define SG_DIG_GMII_INPUT_SELECT 0x00000040
869 #define SG_DIG_MRADV_CRC16_SELECT 0x00000020
870 #define SG_DIG_COMMA_DETECT_ENABLE 0x00000010
871 #define SG_DIG_AUTONEG_TIMER_REDUCE 0x00000008
872 #define SG_DIG_AUTONEG_LOW_ENABLE 0x00000004
873 #define SG_DIG_REMOTE_LOOPBACK 0x00000002
874 #define SG_DIG_LOOPBACK 0x00000001
875 #define SG_DIG_COMMON_SETUP (SG_DIG_CRC16_CLEAR_N | \
876 SG_DIG_LOCAL_DUPLEX_STATUS | \
877 SG_DIG_LOCAL_LINK_STATUS | \
878 (0x2 << SG_DIG_SPEED_STATUS_SHIFT) | \
879 SG_DIG_FIBER_MODE | SG_DIG_GBIC_ENABLE)
880 #define SG_DIG_STATUS 0x000005b4
881 #define SG_DIG_CRC16_BUS_MASK 0xffff0000
882 #define SG_DIG_PARTNER_FAULT_MASK 0x00600000 /* If !MRADV_CRC16_SELECT */
883 #define SG_DIG_PARTNER_ASYM_PAUSE 0x00100000 /* If !MRADV_CRC16_SELECT */
884 #define SG_DIG_PARTNER_PAUSE_CAPABLE 0x00080000 /* If !MRADV_CRC16_SELECT */
885 #define SG_DIG_PARTNER_HALF_DUPLEX 0x00040000 /* If !MRADV_CRC16_SELECT */
886 #define SG_DIG_PARTNER_FULL_DUPLEX 0x00020000 /* If !MRADV_CRC16_SELECT */
887 #define SG_DIG_PARTNER_NEXT_PAGE 0x00010000 /* If !MRADV_CRC16_SELECT */
888 #define SG_DIG_AUTONEG_STATE_MASK 0x00000ff0
889 #define SG_DIG_IS_SERDES 0x00000100
890 #define SG_DIG_COMMA_DETECTOR 0x00000008
891 #define SG_DIG_MAC_ACK_STATUS 0x00000004
892 #define SG_DIG_AUTONEG_COMPLETE 0x00000002
893 #define SG_DIG_AUTONEG_ERROR 0x00000001
894 /* 0x5b8 --> 0x600 unused */
895 #define MAC_TX_MAC_STATE_BASE 0x00000600 /* 16 bytes */
896 #define MAC_RX_MAC_STATE_BASE 0x00000610 /* 20 bytes */
897 /* 0x624 --> 0x670 unused */
899 #define MAC_RSS_INDIR_TBL_0 0x00000630
901 #define MAC_RSS_HASH_KEY_0 0x00000670
902 #define MAC_RSS_HASH_KEY_1 0x00000674
903 #define MAC_RSS_HASH_KEY_2 0x00000678
904 #define MAC_RSS_HASH_KEY_3 0x0000067c
905 #define MAC_RSS_HASH_KEY_4 0x00000680
906 #define MAC_RSS_HASH_KEY_5 0x00000684
907 #define MAC_RSS_HASH_KEY_6 0x00000688
908 #define MAC_RSS_HASH_KEY_7 0x0000068c
909 #define MAC_RSS_HASH_KEY_8 0x00000690
910 #define MAC_RSS_HASH_KEY_9 0x00000694
911 /* 0x698 --> 0x800 unused */
913 #define MAC_TX_STATS_OCTETS 0x00000800
914 #define MAC_TX_STATS_RESV1 0x00000804
915 #define MAC_TX_STATS_COLLISIONS 0x00000808
916 #define MAC_TX_STATS_XON_SENT 0x0000080c
917 #define MAC_TX_STATS_XOFF_SENT 0x00000810
918 #define MAC_TX_STATS_RESV2 0x00000814
919 #define MAC_TX_STATS_MAC_ERRORS 0x00000818
920 #define MAC_TX_STATS_SINGLE_COLLISIONS 0x0000081c
921 #define MAC_TX_STATS_MULT_COLLISIONS 0x00000820
922 #define MAC_TX_STATS_DEFERRED 0x00000824
923 #define MAC_TX_STATS_RESV3 0x00000828
924 #define MAC_TX_STATS_EXCESSIVE_COL 0x0000082c
925 #define MAC_TX_STATS_LATE_COL 0x00000830
926 #define MAC_TX_STATS_RESV4_1 0x00000834
927 #define MAC_TX_STATS_RESV4_2 0x00000838
928 #define MAC_TX_STATS_RESV4_3 0x0000083c
929 #define MAC_TX_STATS_RESV4_4 0x00000840
930 #define MAC_TX_STATS_RESV4_5 0x00000844
931 #define MAC_TX_STATS_RESV4_6 0x00000848
932 #define MAC_TX_STATS_RESV4_7 0x0000084c
933 #define MAC_TX_STATS_RESV4_8 0x00000850
934 #define MAC_TX_STATS_RESV4_9 0x00000854
935 #define MAC_TX_STATS_RESV4_10 0x00000858
936 #define MAC_TX_STATS_RESV4_11 0x0000085c
937 #define MAC_TX_STATS_RESV4_12 0x00000860
938 #define MAC_TX_STATS_RESV4_13 0x00000864
939 #define MAC_TX_STATS_RESV4_14 0x00000868
940 #define MAC_TX_STATS_UCAST 0x0000086c
941 #define MAC_TX_STATS_MCAST 0x00000870
942 #define MAC_TX_STATS_BCAST 0x00000874
943 #define MAC_TX_STATS_RESV5_1 0x00000878
944 #define MAC_TX_STATS_RESV5_2 0x0000087c
945 #define MAC_RX_STATS_OCTETS 0x00000880
946 #define MAC_RX_STATS_RESV1 0x00000884
947 #define MAC_RX_STATS_FRAGMENTS 0x00000888
948 #define MAC_RX_STATS_UCAST 0x0000088c
949 #define MAC_RX_STATS_MCAST 0x00000890
950 #define MAC_RX_STATS_BCAST 0x00000894
951 #define MAC_RX_STATS_FCS_ERRORS 0x00000898
952 #define MAC_RX_STATS_ALIGN_ERRORS 0x0000089c
953 #define MAC_RX_STATS_XON_PAUSE_RECVD 0x000008a0
954 #define MAC_RX_STATS_XOFF_PAUSE_RECVD 0x000008a4
955 #define MAC_RX_STATS_MAC_CTRL_RECVD 0x000008a8
956 #define MAC_RX_STATS_XOFF_ENTERED 0x000008ac
957 #define MAC_RX_STATS_FRAME_TOO_LONG 0x000008b0
958 #define MAC_RX_STATS_JABBERS 0x000008b4
959 #define MAC_RX_STATS_UNDERSIZE 0x000008b8
960 /* 0x8bc --> 0xc00 unused */
962 /* Send data initiator control registers */
963 #define SNDDATAI_MODE 0x00000c00
964 #define SNDDATAI_MODE_RESET 0x00000001
965 #define SNDDATAI_MODE_ENABLE 0x00000002
966 #define SNDDATAI_MODE_STAT_OFLOW_ENAB 0x00000004
967 #define SNDDATAI_STATUS 0x00000c04
968 #define SNDDATAI_STATUS_STAT_OFLOW 0x00000004
969 #define SNDDATAI_STATSCTRL 0x00000c08
970 #define SNDDATAI_SCTRL_ENABLE 0x00000001
971 #define SNDDATAI_SCTRL_FASTUPD 0x00000002
972 #define SNDDATAI_SCTRL_CLEAR 0x00000004
973 #define SNDDATAI_SCTRL_FLUSH 0x00000008
974 #define SNDDATAI_SCTRL_FORCE_ZERO 0x00000010
975 #define SNDDATAI_STATSENAB 0x00000c0c
976 #define SNDDATAI_STATSINCMASK 0x00000c10
977 #define ISO_PKT_TX 0x00000c20
978 /* 0xc24 --> 0xc80 unused */
979 #define SNDDATAI_COS_CNT_0 0x00000c80
980 #define SNDDATAI_COS_CNT_1 0x00000c84
981 #define SNDDATAI_COS_CNT_2 0x00000c88
982 #define SNDDATAI_COS_CNT_3 0x00000c8c
983 #define SNDDATAI_COS_CNT_4 0x00000c90
984 #define SNDDATAI_COS_CNT_5 0x00000c94
985 #define SNDDATAI_COS_CNT_6 0x00000c98
986 #define SNDDATAI_COS_CNT_7 0x00000c9c
987 #define SNDDATAI_COS_CNT_8 0x00000ca0
988 #define SNDDATAI_COS_CNT_9 0x00000ca4
989 #define SNDDATAI_COS_CNT_10 0x00000ca8
990 #define SNDDATAI_COS_CNT_11 0x00000cac
991 #define SNDDATAI_COS_CNT_12 0x00000cb0
992 #define SNDDATAI_COS_CNT_13 0x00000cb4
993 #define SNDDATAI_COS_CNT_14 0x00000cb8
994 #define SNDDATAI_COS_CNT_15 0x00000cbc
995 #define SNDDATAI_DMA_RDQ_FULL_CNT 0x00000cc0
996 #define SNDDATAI_DMA_PRIO_RDQ_FULL_CNT 0x00000cc4
997 #define SNDDATAI_SDCQ_FULL_CNT 0x00000cc8
998 #define SNDDATAI_NICRNG_SSND_PIDX_CNT 0x00000ccc
999 #define SNDDATAI_STATS_UPDATED_CNT 0x00000cd0
1000 #define SNDDATAI_INTERRUPTS_CNT 0x00000cd4
1001 #define SNDDATAI_AVOID_INTERRUPTS_CNT 0x00000cd8
1002 #define SNDDATAI_SND_THRESH_HIT_CNT 0x00000cdc
1003 /* 0xce0 --> 0x1000 unused */
1005 /* Send data completion control registers */
1006 #define SNDDATAC_MODE 0x00001000
1007 #define SNDDATAC_MODE_RESET 0x00000001
1008 #define SNDDATAC_MODE_ENABLE 0x00000002
1009 #define SNDDATAC_MODE_CDELAY 0x00000010
1010 /* 0x1004 --> 0x1400 unused */
1012 /* Send BD ring selector */
1013 #define SNDBDS_MODE 0x00001400
1014 #define SNDBDS_MODE_RESET 0x00000001
1015 #define SNDBDS_MODE_ENABLE 0x00000002
1016 #define SNDBDS_MODE_ATTN_ENABLE 0x00000004
1017 #define SNDBDS_STATUS 0x00001404
1018 #define SNDBDS_STATUS_ERROR_ATTN 0x00000004
1019 #define SNDBDS_HWDIAG 0x00001408
1020 /* 0x140c --> 0x1440 */
1021 #define SNDBDS_SEL_CON_IDX_0 0x00001440
1022 #define SNDBDS_SEL_CON_IDX_1 0x00001444
1023 #define SNDBDS_SEL_CON_IDX_2 0x00001448
1024 #define SNDBDS_SEL_CON_IDX_3 0x0000144c
1025 #define SNDBDS_SEL_CON_IDX_4 0x00001450
1026 #define SNDBDS_SEL_CON_IDX_5 0x00001454
1027 #define SNDBDS_SEL_CON_IDX_6 0x00001458
1028 #define SNDBDS_SEL_CON_IDX_7 0x0000145c
1029 #define SNDBDS_SEL_CON_IDX_8 0x00001460
1030 #define SNDBDS_SEL_CON_IDX_9 0x00001464
1031 #define SNDBDS_SEL_CON_IDX_10 0x00001468
1032 #define SNDBDS_SEL_CON_IDX_11 0x0000146c
1033 #define SNDBDS_SEL_CON_IDX_12 0x00001470
1034 #define SNDBDS_SEL_CON_IDX_13 0x00001474
1035 #define SNDBDS_SEL_CON_IDX_14 0x00001478
1036 #define SNDBDS_SEL_CON_IDX_15 0x0000147c
1037 /* 0x1480 --> 0x1800 unused */
1039 /* Send BD initiator control registers */
1040 #define SNDBDI_MODE 0x00001800
1041 #define SNDBDI_MODE_RESET 0x00000001
1042 #define SNDBDI_MODE_ENABLE 0x00000002
1043 #define SNDBDI_MODE_ATTN_ENABLE 0x00000004
1044 #define SNDBDI_MODE_MULTI_TXQ_EN 0x00000020
1045 #define SNDBDI_STATUS 0x00001804
1046 #define SNDBDI_STATUS_ERROR_ATTN 0x00000004
1047 #define SNDBDI_IN_PROD_IDX_0 0x00001808
1048 #define SNDBDI_IN_PROD_IDX_1 0x0000180c
1049 #define SNDBDI_IN_PROD_IDX_2 0x00001810
1050 #define SNDBDI_IN_PROD_IDX_3 0x00001814
1051 #define SNDBDI_IN_PROD_IDX_4 0x00001818
1052 #define SNDBDI_IN_PROD_IDX_5 0x0000181c
1053 #define SNDBDI_IN_PROD_IDX_6 0x00001820
1054 #define SNDBDI_IN_PROD_IDX_7 0x00001824
1055 #define SNDBDI_IN_PROD_IDX_8 0x00001828
1056 #define SNDBDI_IN_PROD_IDX_9 0x0000182c
1057 #define SNDBDI_IN_PROD_IDX_10 0x00001830
1058 #define SNDBDI_IN_PROD_IDX_11 0x00001834
1059 #define SNDBDI_IN_PROD_IDX_12 0x00001838
1060 #define SNDBDI_IN_PROD_IDX_13 0x0000183c
1061 #define SNDBDI_IN_PROD_IDX_14 0x00001840
1062 #define SNDBDI_IN_PROD_IDX_15 0x00001844
1063 /* 0x1848 --> 0x1c00 unused */
1065 /* Send BD completion control registers */
1066 #define SNDBDC_MODE 0x00001c00
1067 #define SNDBDC_MODE_RESET 0x00000001
1068 #define SNDBDC_MODE_ENABLE 0x00000002
1069 #define SNDBDC_MODE_ATTN_ENABLE 0x00000004
1070 /* 0x1c04 --> 0x2000 unused */
1072 /* Receive list placement control registers */
1073 #define RCVLPC_MODE 0x00002000
1074 #define RCVLPC_MODE_RESET 0x00000001
1075 #define RCVLPC_MODE_ENABLE 0x00000002
1076 #define RCVLPC_MODE_CLASS0_ATTN_ENAB 0x00000004
1077 #define RCVLPC_MODE_MAPOOR_AATTN_ENAB 0x00000008
1078 #define RCVLPC_MODE_STAT_OFLOW_ENAB 0x00000010
1079 #define RCVLPC_STATUS 0x00002004
1080 #define RCVLPC_STATUS_CLASS0 0x00000004
1081 #define RCVLPC_STATUS_MAPOOR 0x00000008
1082 #define RCVLPC_STATUS_STAT_OFLOW 0x00000010
1083 #define RCVLPC_LOCK 0x00002008
1084 #define RCVLPC_LOCK_REQ_MASK 0x0000ffff
1085 #define RCVLPC_LOCK_REQ_SHIFT 0
1086 #define RCVLPC_LOCK_GRANT_MASK 0xffff0000
1087 #define RCVLPC_LOCK_GRANT_SHIFT 16
1088 #define RCVLPC_NON_EMPTY_BITS 0x0000200c
1089 #define RCVLPC_NON_EMPTY_BITS_MASK 0x0000ffff
1090 #define RCVLPC_CONFIG 0x00002010
1091 #define RCVLPC_STATSCTRL 0x00002014
1092 #define RCVLPC_STATSCTRL_ENABLE 0x00000001
1093 #define RCVLPC_STATSCTRL_FASTUPD 0x00000002
1094 #define RCVLPC_STATS_ENABLE 0x00002018
1095 #define RCVLPC_STATSENAB_ASF_FIX 0x00000002
1096 #define RCVLPC_STATSENAB_DACK_FIX 0x00040000
1097 #define RCVLPC_STATSENAB_LNGBRST_RFIX 0x00400000
1098 #define RCVLPC_STATS_INCMASK 0x0000201c
1099 /* 0x2020 --> 0x2100 unused */
1100 #define RCVLPC_SELLST_BASE 0x00002100 /* 16 16-byte entries */
1101 #define SELLST_TAIL 0x00000004
1102 #define SELLST_CONT 0x00000008
1103 #define SELLST_UNUSED 0x0000000c
1104 #define RCVLPC_COS_CNTL_BASE 0x00002200 /* 16 4-byte entries */
1105 #define RCVLPC_DROP_FILTER_CNT 0x00002240
1106 #define RCVLPC_DMA_WQ_FULL_CNT 0x00002244
1107 #define RCVLPC_DMA_HIPRIO_WQ_FULL_CNT 0x00002248
1108 #define RCVLPC_NO_RCV_BD_CNT 0x0000224c
1109 #define RCVLPC_IN_DISCARDS_CNT 0x00002250
1110 #define RCVLPC_IN_ERRORS_CNT 0x00002254
1111 #define RCVLPC_RCV_THRESH_HIT_CNT 0x00002258
1112 /* 0x225c --> 0x2400 unused */
1114 /* Receive Data and Receive BD Initiator Control */
1115 #define RCVDBDI_MODE 0x00002400
1116 #define RCVDBDI_MODE_RESET 0x00000001
1117 #define RCVDBDI_MODE_ENABLE 0x00000002
1118 #define RCVDBDI_MODE_JUMBOBD_NEEDED 0x00000004
1119 #define RCVDBDI_MODE_FRM_TOO_BIG 0x00000008
1120 #define RCVDBDI_MODE_INV_RING_SZ 0x00000010
1121 #define RCVDBDI_MODE_LRG_RING_SZ 0x00010000
1122 #define RCVDBDI_STATUS 0x00002404
1123 #define RCVDBDI_STATUS_JUMBOBD_NEEDED 0x00000004
1124 #define RCVDBDI_STATUS_FRM_TOO_BIG 0x00000008
1125 #define RCVDBDI_STATUS_INV_RING_SZ 0x00000010
1126 #define RCVDBDI_SPLIT_FRAME_MINSZ 0x00002408
1127 /* 0x240c --> 0x2440 unused */
1128 #define RCVDBDI_JUMBO_BD 0x00002440 /* TG3_BDINFO_... */
1129 #define RCVDBDI_STD_BD 0x00002450 /* TG3_BDINFO_... */
1130 #define RCVDBDI_MINI_BD 0x00002460 /* TG3_BDINFO_... */
1131 #define RCVDBDI_JUMBO_CON_IDX 0x00002470
1132 #define RCVDBDI_STD_CON_IDX 0x00002474
1133 #define RCVDBDI_MINI_CON_IDX 0x00002478
1134 /* 0x247c --> 0x2480 unused */
1135 #define RCVDBDI_BD_PROD_IDX_0 0x00002480
1136 #define RCVDBDI_BD_PROD_IDX_1 0x00002484
1137 #define RCVDBDI_BD_PROD_IDX_2 0x00002488
1138 #define RCVDBDI_BD_PROD_IDX_3 0x0000248c
1139 #define RCVDBDI_BD_PROD_IDX_4 0x00002490
1140 #define RCVDBDI_BD_PROD_IDX_5 0x00002494
1141 #define RCVDBDI_BD_PROD_IDX_6 0x00002498
1142 #define RCVDBDI_BD_PROD_IDX_7 0x0000249c
1143 #define RCVDBDI_BD_PROD_IDX_8 0x000024a0
1144 #define RCVDBDI_BD_PROD_IDX_9 0x000024a4
1145 #define RCVDBDI_BD_PROD_IDX_10 0x000024a8
1146 #define RCVDBDI_BD_PROD_IDX_11 0x000024ac
1147 #define RCVDBDI_BD_PROD_IDX_12 0x000024b0
1148 #define RCVDBDI_BD_PROD_IDX_13 0x000024b4
1149 #define RCVDBDI_BD_PROD_IDX_14 0x000024b8
1150 #define RCVDBDI_BD_PROD_IDX_15 0x000024bc
1151 #define RCVDBDI_HWDIAG 0x000024c0
1152 /* 0x24c4 --> 0x2800 unused */
1154 /* Receive Data Completion Control */
1155 #define RCVDCC_MODE 0x00002800
1156 #define RCVDCC_MODE_RESET 0x00000001
1157 #define RCVDCC_MODE_ENABLE 0x00000002
1158 #define RCVDCC_MODE_ATTN_ENABLE 0x00000004
1159 /* 0x2804 --> 0x2c00 unused */
1161 /* Receive BD Initiator Control Registers */
1162 #define RCVBDI_MODE 0x00002c00
1163 #define RCVBDI_MODE_RESET 0x00000001
1164 #define RCVBDI_MODE_ENABLE 0x00000002
1165 #define RCVBDI_MODE_RCB_ATTN_ENAB 0x00000004
1166 #define RCVBDI_STATUS 0x00002c04
1167 #define RCVBDI_STATUS_RCB_ATTN 0x00000004
1168 #define RCVBDI_JUMBO_PROD_IDX 0x00002c08
1169 #define RCVBDI_STD_PROD_IDX 0x00002c0c
1170 #define RCVBDI_MINI_PROD_IDX 0x00002c10
1171 #define RCVBDI_MINI_THRESH 0x00002c14
1172 #define RCVBDI_STD_THRESH 0x00002c18
1173 #define RCVBDI_JUMBO_THRESH 0x00002c1c
1174 /* 0x2c20 --> 0x2d00 unused */
1176 #define STD_REPLENISH_LWM 0x00002d00
1177 #define JMB_REPLENISH_LWM 0x00002d04
1178 /* 0x2d08 --> 0x3000 unused */
1180 /* Receive BD Completion Control Registers */
1181 #define RCVCC_MODE 0x00003000
1182 #define RCVCC_MODE_RESET 0x00000001
1183 #define RCVCC_MODE_ENABLE 0x00000002
1184 #define RCVCC_MODE_ATTN_ENABLE 0x00000004
1185 #define RCVCC_STATUS 0x00003004
1186 #define RCVCC_STATUS_ERROR_ATTN 0x00000004
1187 #define RCVCC_JUMP_PROD_IDX 0x00003008
1188 #define RCVCC_STD_PROD_IDX 0x0000300c
1189 #define RCVCC_MINI_PROD_IDX 0x00003010
1190 /* 0x3014 --> 0x3400 unused */
1192 /* Receive list selector control registers */
1193 #define RCVLSC_MODE 0x00003400
1194 #define RCVLSC_MODE_RESET 0x00000001
1195 #define RCVLSC_MODE_ENABLE 0x00000002
1196 #define RCVLSC_MODE_ATTN_ENABLE 0x00000004
1197 #define RCVLSC_STATUS 0x00003404
1198 #define RCVLSC_STATUS_ERROR_ATTN 0x00000004
1199 /* 0x3408 --> 0x3600 unused */
1201 /* CPMU registers */
1202 #define TG3_CPMU_CTRL 0x00003600
1203 #define CPMU_CTRL_LINK_IDLE_MODE 0x00000200
1204 #define CPMU_CTRL_LINK_AWARE_MODE 0x00000400
1205 #define CPMU_CTRL_LINK_SPEED_MODE 0x00004000
1206 #define CPMU_CTRL_GPHY_10MB_RXONLY 0x00010000
1207 #define TG3_CPMU_LSPD_10MB_CLK 0x00003604
1208 #define CPMU_LSPD_10MB_MACCLK_MASK 0x001f0000
1209 #define CPMU_LSPD_10MB_MACCLK_6_25 0x00130000
1210 /* 0x3608 --> 0x360c unused */
1212 #define TG3_CPMU_LSPD_1000MB_CLK 0x0000360c
1213 #define CPMU_LSPD_1000MB_MACCLK_62_5 0x00000000
1214 #define CPMU_LSPD_1000MB_MACCLK_12_5 0x00110000
1215 #define CPMU_LSPD_1000MB_MACCLK_MASK 0x001f0000
1216 #define TG3_CPMU_LNK_AWARE_PWRMD 0x00003610
1217 #define CPMU_LNK_AWARE_MACCLK_MASK 0x001f0000
1218 #define CPMU_LNK_AWARE_MACCLK_6_25 0x00130000
1220 #define TG3_CPMU_D0_CLCK_POLICY 0x00003614
1221 /* 0x3614 --> 0x361c unused */
1223 #define TG3_CPMU_HST_ACC 0x0000361c
1224 #define CPMU_HST_ACC_MACCLK_MASK 0x001f0000
1225 #define CPMU_HST_ACC_MACCLK_6_25 0x00130000
1226 /* 0x3620 --> 0x3630 unused */
1228 #define TG3_CPMU_CLCK_ORIDE 0x00003624
1229 #define CPMU_CLCK_ORIDE_MAC_ORIDE_EN 0x80000000
1231 #define TG3_CPMU_CLCK_ORIDE_EN 0x00003628
1232 #define CPMU_CLCK_ORIDE_MAC_CLCK_ORIDE_EN 0x00002000
1234 #define TG3_CPMU_CLCK_STAT 0x00003630
1235 #define CPMU_CLCK_STAT_MAC_CLCK_MASK 0x001f0000
1236 #define CPMU_CLCK_STAT_MAC_CLCK_62_5 0x00000000
1237 #define CPMU_CLCK_STAT_MAC_CLCK_12_5 0x00110000
1238 #define CPMU_CLCK_STAT_MAC_CLCK_6_25 0x00130000
1239 /* 0x3634 --> 0x365c unused */
1241 #define TG3_CPMU_MUTEX_REQ 0x0000365c
1242 #define CPMU_MUTEX_REQ_DRIVER 0x00001000
1243 #define TG3_CPMU_MUTEX_GNT 0x00003660
1244 #define CPMU_MUTEX_GNT_DRIVER 0x00001000
1245 #define TG3_CPMU_PHY_STRAP 0x00003664
1246 #define TG3_CPMU_PHY_STRAP_IS_SERDES 0x00000020
1247 /* 0x3664 --> 0x36b0 unused */
1249 #define TG3_CPMU_EEE_MODE 0x000036b0
1250 #define TG3_CPMU_EEEMD_APE_TX_DET_EN 0x00000004
1251 #define TG3_CPMU_EEEMD_ERLY_L1_XIT_DET 0x00000008
1252 #define TG3_CPMU_EEEMD_SND_IDX_DET_EN 0x00000040
1253 #define TG3_CPMU_EEEMD_LPI_ENABLE 0x00000080
1254 #define TG3_CPMU_EEEMD_LPI_IN_TX 0x00000100
1255 #define TG3_CPMU_EEEMD_LPI_IN_RX 0x00000200
1256 #define TG3_CPMU_EEEMD_EEE_ENABLE 0x00100000
1257 #define TG3_CPMU_EEE_DBTMR1 0x000036b4
1258 #define TG3_CPMU_DBTMR1_PCIEXIT_2047US 0x07ff0000
1259 #define TG3_CPMU_DBTMR1_LNKIDLE_2047US 0x000070ff
1260 #define TG3_CPMU_EEE_DBTMR2 0x000036b8
1261 #define TG3_CPMU_DBTMR2_APE_TX_2047US 0x07ff0000
1262 #define TG3_CPMU_DBTMR2_TXIDXEQ_2047US 0x000070ff
1263 #define TG3_CPMU_EEE_LNKIDL_CTRL 0x000036bc
1264 #define TG3_CPMU_EEE_LNKIDL_PCIE_NL0 0x01000000
1265 #define TG3_CPMU_EEE_LNKIDL_UART_IDL 0x00000004
1266 /* 0x36c0 --> 0x36d0 unused */
1268 #define TG3_CPMU_EEE_CTRL 0x000036d0
1269 #define TG3_CPMU_EEE_CTRL_EXIT_16_5_US 0x0000019d
1270 #define TG3_CPMU_EEE_CTRL_EXIT_36_US 0x00000384
1271 #define TG3_CPMU_EEE_CTRL_EXIT_20_1_US 0x000001f8
1272 /* 0x36d4 --> 0x3800 unused */
1274 /* Mbuf cluster free registers */
1275 #define MBFREE_MODE 0x00003800
1276 #define MBFREE_MODE_RESET 0x00000001
1277 #define MBFREE_MODE_ENABLE 0x00000002
1278 #define MBFREE_STATUS 0x00003804
1279 /* 0x3808 --> 0x3c00 unused */
1281 /* Host coalescing control registers */
1282 #define HOSTCC_MODE 0x00003c00
1283 #define HOSTCC_MODE_RESET 0x00000001
1284 #define HOSTCC_MODE_ENABLE 0x00000002
1285 #define HOSTCC_MODE_ATTN 0x00000004
1286 #define HOSTCC_MODE_NOW 0x00000008
1287 #define HOSTCC_MODE_FULL_STATUS 0x00000000
1288 #define HOSTCC_MODE_64BYTE 0x00000080
1289 #define HOSTCC_MODE_32BYTE 0x00000100
1290 #define HOSTCC_MODE_CLRTICK_RXBD 0x00000200
1291 #define HOSTCC_MODE_CLRTICK_TXBD 0x00000400
1292 #define HOSTCC_MODE_NOINT_ON_NOW 0x00000800
1293 #define HOSTCC_MODE_NOINT_ON_FORCE 0x00001000
1294 #define HOSTCC_MODE_COAL_VEC1_NOW 0x00002000
1295 #define HOSTCC_STATUS 0x00003c04
1296 #define HOSTCC_STATUS_ERROR_ATTN 0x00000004
1297 #define HOSTCC_RXCOL_TICKS 0x00003c08
1298 #define LOW_RXCOL_TICKS 0x00000032
1299 #define LOW_RXCOL_TICKS_CLRTCKS 0x00000014
1300 #define DEFAULT_RXCOL_TICKS 0x00000048
1301 #define HIGH_RXCOL_TICKS 0x00000096
1302 #define MAX_RXCOL_TICKS 0x000003ff
1303 #define HOSTCC_TXCOL_TICKS 0x00003c0c
1304 #define LOW_TXCOL_TICKS 0x00000096
1305 #define LOW_TXCOL_TICKS_CLRTCKS 0x00000048
1306 #define DEFAULT_TXCOL_TICKS 0x0000012c
1307 #define HIGH_TXCOL_TICKS 0x00000145
1308 #define MAX_TXCOL_TICKS 0x000003ff
1309 #define HOSTCC_RXMAX_FRAMES 0x00003c10
1310 #define LOW_RXMAX_FRAMES 0x00000005
1311 #define DEFAULT_RXMAX_FRAMES 0x00000008
1312 #define HIGH_RXMAX_FRAMES 0x00000012
1313 #define MAX_RXMAX_FRAMES 0x000000ff
1314 #define HOSTCC_TXMAX_FRAMES 0x00003c14
1315 #define LOW_TXMAX_FRAMES 0x00000035
1316 #define DEFAULT_TXMAX_FRAMES 0x0000004b
1317 #define HIGH_TXMAX_FRAMES 0x00000052
1318 #define MAX_TXMAX_FRAMES 0x000000ff
1319 #define HOSTCC_RXCOAL_TICK_INT 0x00003c18
1320 #define DEFAULT_RXCOAL_TICK_INT 0x00000019
1321 #define DEFAULT_RXCOAL_TICK_INT_CLRTCKS 0x00000014
1322 #define MAX_RXCOAL_TICK_INT 0x000003ff
1323 #define HOSTCC_TXCOAL_TICK_INT 0x00003c1c
1324 #define DEFAULT_TXCOAL_TICK_INT 0x00000019
1325 #define DEFAULT_TXCOAL_TICK_INT_CLRTCKS 0x00000014
1326 #define MAX_TXCOAL_TICK_INT 0x000003ff
1327 #define HOSTCC_RXCOAL_MAXF_INT 0x00003c20
1328 #define DEFAULT_RXCOAL_MAXF_INT 0x00000005
1329 #define MAX_RXCOAL_MAXF_INT 0x000000ff
1330 #define HOSTCC_TXCOAL_MAXF_INT 0x00003c24
1331 #define DEFAULT_TXCOAL_MAXF_INT 0x00000005
1332 #define MAX_TXCOAL_MAXF_INT 0x000000ff
1333 #define HOSTCC_STAT_COAL_TICKS 0x00003c28
1334 #define DEFAULT_STAT_COAL_TICKS 0x000f4240
1335 #define MAX_STAT_COAL_TICKS 0xd693d400
1336 #define MIN_STAT_COAL_TICKS 0x00000064
1337 /* 0x3c2c --> 0x3c30 unused */
1338 #define HOSTCC_STATS_BLK_HOST_ADDR 0x00003c30 /* 64-bit */
1339 #define HOSTCC_STATUS_BLK_HOST_ADDR 0x00003c38 /* 64-bit */
1340 #define HOSTCC_STATS_BLK_NIC_ADDR 0x00003c40
1341 #define HOSTCC_STATUS_BLK_NIC_ADDR 0x00003c44
1342 #define HOSTCC_FLOW_ATTN 0x00003c48
1343 #define HOSTCC_FLOW_ATTN_MBUF_LWM 0x00000040
1344 /* 0x3c4c --> 0x3c50 unused */
1345 #define HOSTCC_JUMBO_CON_IDX 0x00003c50
1346 #define HOSTCC_STD_CON_IDX 0x00003c54
1347 #define HOSTCC_MINI_CON_IDX 0x00003c58
1348 /* 0x3c5c --> 0x3c80 unused */
1349 #define HOSTCC_RET_PROD_IDX_0 0x00003c80
1350 #define HOSTCC_RET_PROD_IDX_1 0x00003c84
1351 #define HOSTCC_RET_PROD_IDX_2 0x00003c88
1352 #define HOSTCC_RET_PROD_IDX_3 0x00003c8c
1353 #define HOSTCC_RET_PROD_IDX_4 0x00003c90
1354 #define HOSTCC_RET_PROD_IDX_5 0x00003c94
1355 #define HOSTCC_RET_PROD_IDX_6 0x00003c98
1356 #define HOSTCC_RET_PROD_IDX_7 0x00003c9c
1357 #define HOSTCC_RET_PROD_IDX_8 0x00003ca0
1358 #define HOSTCC_RET_PROD_IDX_9 0x00003ca4
1359 #define HOSTCC_RET_PROD_IDX_10 0x00003ca8
1360 #define HOSTCC_RET_PROD_IDX_11 0x00003cac
1361 #define HOSTCC_RET_PROD_IDX_12 0x00003cb0
1362 #define HOSTCC_RET_PROD_IDX_13 0x00003cb4
1363 #define HOSTCC_RET_PROD_IDX_14 0x00003cb8
1364 #define HOSTCC_RET_PROD_IDX_15 0x00003cbc
1365 #define HOSTCC_SND_CON_IDX_0 0x00003cc0
1366 #define HOSTCC_SND_CON_IDX_1 0x00003cc4
1367 #define HOSTCC_SND_CON_IDX_2 0x00003cc8
1368 #define HOSTCC_SND_CON_IDX_3 0x00003ccc
1369 #define HOSTCC_SND_CON_IDX_4 0x00003cd0
1370 #define HOSTCC_SND_CON_IDX_5 0x00003cd4
1371 #define HOSTCC_SND_CON_IDX_6 0x00003cd8
1372 #define HOSTCC_SND_CON_IDX_7 0x00003cdc
1373 #define HOSTCC_SND_CON_IDX_8 0x00003ce0
1374 #define HOSTCC_SND_CON_IDX_9 0x00003ce4
1375 #define HOSTCC_SND_CON_IDX_10 0x00003ce8
1376 #define HOSTCC_SND_CON_IDX_11 0x00003cec
1377 #define HOSTCC_SND_CON_IDX_12 0x00003cf0
1378 #define HOSTCC_SND_CON_IDX_13 0x00003cf4
1379 #define HOSTCC_SND_CON_IDX_14 0x00003cf8
1380 #define HOSTCC_SND_CON_IDX_15 0x00003cfc
1381 #define HOSTCC_STATBLCK_RING1 0x00003d00
1382 /* 0x3d00 --> 0x3d80 unused */
1384 #define HOSTCC_RXCOL_TICKS_VEC1 0x00003d80
1385 #define HOSTCC_TXCOL_TICKS_VEC1 0x00003d84
1386 #define HOSTCC_RXMAX_FRAMES_VEC1 0x00003d88
1387 #define HOSTCC_TXMAX_FRAMES_VEC1 0x00003d8c
1388 #define HOSTCC_RXCOAL_MAXF_INT_VEC1 0x00003d90
1389 #define HOSTCC_TXCOAL_MAXF_INT_VEC1 0x00003d94
1390 /* 0x3d98 --> 0x4000 unused */
1392 /* Memory arbiter control registers */
1393 #define MEMARB_MODE 0x00004000
1394 #define MEMARB_MODE_RESET 0x00000001
1395 #define MEMARB_MODE_ENABLE 0x00000002
1396 #define MEMARB_STATUS 0x00004004
1397 #define MEMARB_TRAP_ADDR_LOW 0x00004008
1398 #define MEMARB_TRAP_ADDR_HIGH 0x0000400c
1399 /* 0x4010 --> 0x4400 unused */
1401 /* Buffer manager control registers */
1402 #define BUFMGR_MODE 0x00004400
1403 #define BUFMGR_MODE_RESET 0x00000001
1404 #define BUFMGR_MODE_ENABLE 0x00000002
1405 #define BUFMGR_MODE_ATTN_ENABLE 0x00000004
1406 #define BUFMGR_MODE_BM_TEST 0x00000008
1407 #define BUFMGR_MODE_MBLOW_ATTN_ENAB 0x00000010
1408 #define BUFMGR_MODE_NO_TX_UNDERRUN 0x80000000
1409 #define BUFMGR_STATUS 0x00004404
1410 #define BUFMGR_STATUS_ERROR 0x00000004
1411 #define BUFMGR_STATUS_MBLOW 0x00000010
1412 #define BUFMGR_MB_POOL_ADDR 0x00004408
1413 #define BUFMGR_MB_POOL_SIZE 0x0000440c
1414 #define BUFMGR_MB_RDMA_LOW_WATER 0x00004410
1415 #define DEFAULT_MB_RDMA_LOW_WATER 0x00000050
1416 #define DEFAULT_MB_RDMA_LOW_WATER_5705 0x00000000
1417 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO 0x00000130
1418 #define DEFAULT_MB_RDMA_LOW_WATER_JUMBO_5780 0x00000000
1419 #define BUFMGR_MB_MACRX_LOW_WATER 0x00004414
1420 #define DEFAULT_MB_MACRX_LOW_WATER 0x00000020
1421 #define DEFAULT_MB_MACRX_LOW_WATER_5705 0x00000010
1422 #define DEFAULT_MB_MACRX_LOW_WATER_5906 0x00000004
1423 #define DEFAULT_MB_MACRX_LOW_WATER_57765 0x0000002a
1424 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO 0x00000098
1425 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_5780 0x0000004b
1426 #define DEFAULT_MB_MACRX_LOW_WATER_JUMBO_57765 0x0000007e
1427 #define BUFMGR_MB_HIGH_WATER 0x00004418
1428 #define DEFAULT_MB_HIGH_WATER 0x00000060
1429 #define DEFAULT_MB_HIGH_WATER_5705 0x00000060
1430 #define DEFAULT_MB_HIGH_WATER_5906 0x00000010
1431 #define DEFAULT_MB_HIGH_WATER_57765 0x000000a0
1432 #define DEFAULT_MB_HIGH_WATER_JUMBO 0x0000017c
1433 #define DEFAULT_MB_HIGH_WATER_JUMBO_5780 0x00000096
1434 #define DEFAULT_MB_HIGH_WATER_JUMBO_57765 0x000000ea
1435 #define BUFMGR_RX_MB_ALLOC_REQ 0x0000441c
1436 #define BUFMGR_MB_ALLOC_BIT 0x10000000
1437 #define BUFMGR_RX_MB_ALLOC_RESP 0x00004420
1438 #define BUFMGR_TX_MB_ALLOC_REQ 0x00004424
1439 #define BUFMGR_TX_MB_ALLOC_RESP 0x00004428
1440 #define BUFMGR_DMA_DESC_POOL_ADDR 0x0000442c
1441 #define BUFMGR_DMA_DESC_POOL_SIZE 0x00004430
1442 #define BUFMGR_DMA_LOW_WATER 0x00004434
1443 #define DEFAULT_DMA_LOW_WATER 0x00000005
1444 #define BUFMGR_DMA_HIGH_WATER 0x00004438
1445 #define DEFAULT_DMA_HIGH_WATER 0x0000000a
1446 #define BUFMGR_RX_DMA_ALLOC_REQ 0x0000443c
1447 #define BUFMGR_RX_DMA_ALLOC_RESP 0x00004440
1448 #define BUFMGR_TX_DMA_ALLOC_REQ 0x00004444
1449 #define BUFMGR_TX_DMA_ALLOC_RESP 0x00004448
1450 #define BUFMGR_HWDIAG_0 0x0000444c
1451 #define BUFMGR_HWDIAG_1 0x00004450
1452 #define BUFMGR_HWDIAG_2 0x00004454
1453 /* 0x4458 --> 0x4800 unused */
1455 /* Read DMA control registers */
1456 #define RDMAC_MODE 0x00004800
1457 #define RDMAC_MODE_RESET 0x00000001
1458 #define RDMAC_MODE_ENABLE 0x00000002
1459 #define RDMAC_MODE_TGTABORT_ENAB 0x00000004
1460 #define RDMAC_MODE_MSTABORT_ENAB 0x00000008
1461 #define RDMAC_MODE_PARITYERR_ENAB 0x00000010
1462 #define RDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1463 #define RDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1464 #define RDMAC_MODE_FIFOURUN_ENAB 0x00000080
1465 #define RDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1466 #define RDMAC_MODE_LNGREAD_ENAB 0x00000200
1467 #define RDMAC_MODE_SPLIT_ENABLE 0x00000800
1468 #define RDMAC_MODE_BD_SBD_CRPT_ENAB 0x00000800
1469 #define RDMAC_MODE_SPLIT_RESET 0x00001000
1470 #define RDMAC_MODE_MBUF_RBD_CRPT_ENAB 0x00001000
1471 #define RDMAC_MODE_MBUF_SBD_CRPT_ENAB 0x00002000
1472 #define RDMAC_MODE_FIFO_SIZE_128 0x00020000
1473 #define RDMAC_MODE_FIFO_LONG_BURST 0x00030000
1474 #define RDMAC_MODE_MULT_DMA_RD_DIS 0x01000000
1475 #define RDMAC_MODE_IPV4_LSO_EN 0x08000000
1476 #define RDMAC_MODE_IPV6_LSO_EN 0x10000000
1477 #define RDMAC_MODE_H2BNC_VLAN_DET 0x20000000
1478 #define RDMAC_STATUS 0x00004804
1479 #define RDMAC_STATUS_TGTABORT 0x00000004
1480 #define RDMAC_STATUS_MSTABORT 0x00000008
1481 #define RDMAC_STATUS_PARITYERR 0x00000010
1482 #define RDMAC_STATUS_ADDROFLOW 0x00000020
1483 #define RDMAC_STATUS_FIFOOFLOW 0x00000040
1484 #define RDMAC_STATUS_FIFOURUN 0x00000080
1485 #define RDMAC_STATUS_FIFOOREAD 0x00000100
1486 #define RDMAC_STATUS_LNGREAD 0x00000200
1487 /* 0x4808 --> 0x4900 unused */
1489 #define TG3_RDMA_RSRVCTRL_REG 0x00004900
1490 #define TG3_RDMA_RSRVCTRL_FIFO_OFLW_FIX 0x00000004
1491 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_1_5K 0x00000c00
1492 #define TG3_RDMA_RSRVCTRL_FIFO_LWM_MASK 0x00000ff0
1493 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_1_5K 0x000c0000
1494 #define TG3_RDMA_RSRVCTRL_FIFO_HWM_MASK 0x000ff000
1495 #define TG3_RDMA_RSRVCTRL_TXMRGN_320B 0x28000000
1496 #define TG3_RDMA_RSRVCTRL_TXMRGN_MASK 0xffe00000
1497 /* 0x4904 --> 0x4910 unused */
1499 #define TG3_LSO_RD_DMA_CRPTEN_CTRL 0x00004910
1500 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_BD_4K 0x00030000
1501 #define TG3_LSO_RD_DMA_CRPTEN_CTRL_BLEN_LSO_4K 0x000c0000
1502 /* 0x4914 --> 0x4c00 unused */
1504 /* Write DMA control registers */
1505 #define WDMAC_MODE 0x00004c00
1506 #define WDMAC_MODE_RESET 0x00000001
1507 #define WDMAC_MODE_ENABLE 0x00000002
1508 #define WDMAC_MODE_TGTABORT_ENAB 0x00000004
1509 #define WDMAC_MODE_MSTABORT_ENAB 0x00000008
1510 #define WDMAC_MODE_PARITYERR_ENAB 0x00000010
1511 #define WDMAC_MODE_ADDROFLOW_ENAB 0x00000020
1512 #define WDMAC_MODE_FIFOOFLOW_ENAB 0x00000040
1513 #define WDMAC_MODE_FIFOURUN_ENAB 0x00000080
1514 #define WDMAC_MODE_FIFOOREAD_ENAB 0x00000100
1515 #define WDMAC_MODE_LNGREAD_ENAB 0x00000200
1516 #define WDMAC_MODE_RX_ACCEL 0x00000400
1517 #define WDMAC_MODE_STATUS_TAG_FIX 0x20000000
1518 #define WDMAC_MODE_BURST_ALL_DATA 0xc0000000
1519 #define WDMAC_STATUS 0x00004c04
1520 #define WDMAC_STATUS_TGTABORT 0x00000004
1521 #define WDMAC_STATUS_MSTABORT 0x00000008
1522 #define WDMAC_STATUS_PARITYERR 0x00000010
1523 #define WDMAC_STATUS_ADDROFLOW 0x00000020
1524 #define WDMAC_STATUS_FIFOOFLOW 0x00000040
1525 #define WDMAC_STATUS_FIFOURUN 0x00000080
1526 #define WDMAC_STATUS_FIFOOREAD 0x00000100
1527 #define WDMAC_STATUS_LNGREAD 0x00000200
1528 /* 0x4c08 --> 0x5000 unused */
1530 /* Per-cpu register offsets (arm9) */
1531 #define CPU_MODE 0x00000000
1532 #define CPU_MODE_RESET 0x00000001
1533 #define CPU_MODE_HALT 0x00000400
1534 #define CPU_STATE 0x00000004
1535 #define CPU_EVTMASK 0x00000008
1536 /* 0xc --> 0x1c reserved */
1537 #define CPU_PC 0x0000001c
1538 #define CPU_INSN 0x00000020
1539 #define CPU_SPAD_UFLOW 0x00000024
1540 #define CPU_WDOG_CLEAR 0x00000028
1541 #define CPU_WDOG_VECTOR 0x0000002c
1542 #define CPU_WDOG_PC 0x00000030
1543 #define CPU_HW_BP 0x00000034
1544 /* 0x38 --> 0x44 unused */
1545 #define CPU_WDOG_SAVED_STATE 0x00000044
1546 #define CPU_LAST_BRANCH_ADDR 0x00000048
1547 #define CPU_SPAD_UFLOW_SET 0x0000004c
1548 /* 0x50 --> 0x200 unused */
1549 #define CPU_R0 0x00000200
1550 #define CPU_R1 0x00000204
1551 #define CPU_R2 0x00000208
1552 #define CPU_R3 0x0000020c
1553 #define CPU_R4 0x00000210
1554 #define CPU_R5 0x00000214
1555 #define CPU_R6 0x00000218
1556 #define CPU_R7 0x0000021c
1557 #define CPU_R8 0x00000220
1558 #define CPU_R9 0x00000224
1559 #define CPU_R10 0x00000228
1560 #define CPU_R11 0x0000022c
1561 #define CPU_R12 0x00000230
1562 #define CPU_R13 0x00000234
1563 #define CPU_R14 0x00000238
1564 #define CPU_R15 0x0000023c
1565 #define CPU_R16 0x00000240
1566 #define CPU_R17 0x00000244
1567 #define CPU_R18 0x00000248
1568 #define CPU_R19 0x0000024c
1569 #define CPU_R20 0x00000250
1570 #define CPU_R21 0x00000254
1571 #define CPU_R22 0x00000258
1572 #define CPU_R23 0x0000025c
1573 #define CPU_R24 0x00000260
1574 #define CPU_R25 0x00000264
1575 #define CPU_R26 0x00000268
1576 #define CPU_R27 0x0000026c
1577 #define CPU_R28 0x00000270
1578 #define CPU_R29 0x00000274
1579 #define CPU_R30 0x00000278
1580 #define CPU_R31 0x0000027c
1581 /* 0x280 --> 0x400 unused */
1583 #define RX_CPU_BASE 0x00005000
1584 #define RX_CPU_MODE 0x00005000
1585 #define RX_CPU_STATE 0x00005004
1586 #define RX_CPU_PGMCTR 0x0000501c
1587 #define RX_CPU_HWBKPT 0x00005034
1588 #define TX_CPU_BASE 0x00005400
1589 #define TX_CPU_MODE 0x00005400
1590 #define TX_CPU_STATE 0x00005404
1591 #define TX_CPU_PGMCTR 0x0000541c
1593 #define VCPU_STATUS 0x00005100
1594 #define VCPU_STATUS_INIT_DONE 0x04000000
1595 #define VCPU_STATUS_DRV_RESET 0x08000000
1597 #define VCPU_CFGSHDW 0x00005104
1598 #define VCPU_CFGSHDW_WOL_ENABLE 0x00000001
1599 #define VCPU_CFGSHDW_WOL_MAGPKT 0x00000004
1600 #define VCPU_CFGSHDW_ASPM_DBNC 0x00001000
1603 #define GRCMBOX_BASE 0x00005600
1604 #define GRCMBOX_INTERRUPT_0 0x00005800 /* 64-bit */
1605 #define GRCMBOX_INTERRUPT_1 0x00005808 /* 64-bit */
1606 #define GRCMBOX_INTERRUPT_2 0x00005810 /* 64-bit */
1607 #define GRCMBOX_INTERRUPT_3 0x00005818 /* 64-bit */
1608 #define GRCMBOX_GENERAL_0 0x00005820 /* 64-bit */
1609 #define GRCMBOX_GENERAL_1 0x00005828 /* 64-bit */
1610 #define GRCMBOX_GENERAL_2 0x00005830 /* 64-bit */
1611 #define GRCMBOX_GENERAL_3 0x00005838 /* 64-bit */
1612 #define GRCMBOX_GENERAL_4 0x00005840 /* 64-bit */
1613 #define GRCMBOX_GENERAL_5 0x00005848 /* 64-bit */
1614 #define GRCMBOX_GENERAL_6 0x00005850 /* 64-bit */
1615 #define GRCMBOX_GENERAL_7 0x00005858 /* 64-bit */
1616 #define GRCMBOX_RELOAD_STAT 0x00005860 /* 64-bit */
1617 #define GRCMBOX_RCVSTD_PROD_IDX 0x00005868 /* 64-bit */
1618 #define GRCMBOX_RCVJUMBO_PROD_IDX 0x00005870 /* 64-bit */
1619 #define GRCMBOX_RCVMINI_PROD_IDX 0x00005878 /* 64-bit */
1620 #define GRCMBOX_RCVRET_CON_IDX_0 0x00005880 /* 64-bit */
1621 #define GRCMBOX_RCVRET_CON_IDX_1 0x00005888 /* 64-bit */
1622 #define GRCMBOX_RCVRET_CON_IDX_2 0x00005890 /* 64-bit */
1623 #define GRCMBOX_RCVRET_CON_IDX_3 0x00005898 /* 64-bit */
1624 #define GRCMBOX_RCVRET_CON_IDX_4 0x000058a0 /* 64-bit */
1625 #define GRCMBOX_RCVRET_CON_IDX_5 0x000058a8 /* 64-bit */
1626 #define GRCMBOX_RCVRET_CON_IDX_6 0x000058b0 /* 64-bit */
1627 #define GRCMBOX_RCVRET_CON_IDX_7 0x000058b8 /* 64-bit */
1628 #define GRCMBOX_RCVRET_CON_IDX_8 0x000058c0 /* 64-bit */
1629 #define GRCMBOX_RCVRET_CON_IDX_9 0x000058c8 /* 64-bit */
1630 #define GRCMBOX_RCVRET_CON_IDX_10 0x000058d0 /* 64-bit */
1631 #define GRCMBOX_RCVRET_CON_IDX_11 0x000058d8 /* 64-bit */
1632 #define GRCMBOX_RCVRET_CON_IDX_12 0x000058e0 /* 64-bit */
1633 #define GRCMBOX_RCVRET_CON_IDX_13 0x000058e8 /* 64-bit */
1634 #define GRCMBOX_RCVRET_CON_IDX_14 0x000058f0 /* 64-bit */
1635 #define GRCMBOX_RCVRET_CON_IDX_15 0x000058f8 /* 64-bit */
1636 #define GRCMBOX_SNDHOST_PROD_IDX_0 0x00005900 /* 64-bit */
1637 #define GRCMBOX_SNDHOST_PROD_IDX_1 0x00005908 /* 64-bit */
1638 #define GRCMBOX_SNDHOST_PROD_IDX_2 0x00005910 /* 64-bit */
1639 #define GRCMBOX_SNDHOST_PROD_IDX_3 0x00005918 /* 64-bit */
1640 #define GRCMBOX_SNDHOST_PROD_IDX_4 0x00005920 /* 64-bit */
1641 #define GRCMBOX_SNDHOST_PROD_IDX_5 0x00005928 /* 64-bit */
1642 #define GRCMBOX_SNDHOST_PROD_IDX_6 0x00005930 /* 64-bit */
1643 #define GRCMBOX_SNDHOST_PROD_IDX_7 0x00005938 /* 64-bit */
1644 #define GRCMBOX_SNDHOST_PROD_IDX_8 0x00005940 /* 64-bit */
1645 #define GRCMBOX_SNDHOST_PROD_IDX_9 0x00005948 /* 64-bit */
1646 #define GRCMBOX_SNDHOST_PROD_IDX_10 0x00005950 /* 64-bit */
1647 #define GRCMBOX_SNDHOST_PROD_IDX_11 0x00005958 /* 64-bit */
1648 #define GRCMBOX_SNDHOST_PROD_IDX_12 0x00005960 /* 64-bit */
1649 #define GRCMBOX_SNDHOST_PROD_IDX_13 0x00005968 /* 64-bit */
1650 #define GRCMBOX_SNDHOST_PROD_IDX_14 0x00005970 /* 64-bit */
1651 #define GRCMBOX_SNDHOST_PROD_IDX_15 0x00005978 /* 64-bit */
1652 #define GRCMBOX_SNDNIC_PROD_IDX_0 0x00005980 /* 64-bit */
1653 #define GRCMBOX_SNDNIC_PROD_IDX_1 0x00005988 /* 64-bit */
1654 #define GRCMBOX_SNDNIC_PROD_IDX_2 0x00005990 /* 64-bit */
1655 #define GRCMBOX_SNDNIC_PROD_IDX_3 0x00005998 /* 64-bit */
1656 #define GRCMBOX_SNDNIC_PROD_IDX_4 0x000059a0 /* 64-bit */
1657 #define GRCMBOX_SNDNIC_PROD_IDX_5 0x000059a8 /* 64-bit */
1658 #define GRCMBOX_SNDNIC_PROD_IDX_6 0x000059b0 /* 64-bit */
1659 #define GRCMBOX_SNDNIC_PROD_IDX_7 0x000059b8 /* 64-bit */
1660 #define GRCMBOX_SNDNIC_PROD_IDX_8 0x000059c0 /* 64-bit */
1661 #define GRCMBOX_SNDNIC_PROD_IDX_9 0x000059c8 /* 64-bit */
1662 #define GRCMBOX_SNDNIC_PROD_IDX_10 0x000059d0 /* 64-bit */
1663 #define GRCMBOX_SNDNIC_PROD_IDX_11 0x000059d8 /* 64-bit */
1664 #define GRCMBOX_SNDNIC_PROD_IDX_12 0x000059e0 /* 64-bit */
1665 #define GRCMBOX_SNDNIC_PROD_IDX_13 0x000059e8 /* 64-bit */
1666 #define GRCMBOX_SNDNIC_PROD_IDX_14 0x000059f0 /* 64-bit */
1667 #define GRCMBOX_SNDNIC_PROD_IDX_15 0x000059f8 /* 64-bit */
1668 #define GRCMBOX_HIGH_PRIO_EV_VECTOR 0x00005a00
1669 #define GRCMBOX_HIGH_PRIO_EV_MASK 0x00005a04
1670 #define GRCMBOX_LOW_PRIO_EV_VEC 0x00005a08
1671 #define GRCMBOX_LOW_PRIO_EV_MASK 0x00005a0c
1672 /* 0x5a10 --> 0x5c00 */
1674 /* Flow Through queues */
1675 #define FTQ_RESET 0x00005c00
1676 /* 0x5c04 --> 0x5c10 unused */
1677 #define FTQ_DMA_NORM_READ_CTL 0x00005c10
1678 #define FTQ_DMA_NORM_READ_FULL_CNT 0x00005c14
1679 #define FTQ_DMA_NORM_READ_FIFO_ENQDEQ 0x00005c18
1680 #define FTQ_DMA_NORM_READ_WRITE_PEEK 0x00005c1c
1681 #define FTQ_DMA_HIGH_READ_CTL 0x00005c20
1682 #define FTQ_DMA_HIGH_READ_FULL_CNT 0x00005c24
1683 #define FTQ_DMA_HIGH_READ_FIFO_ENQDEQ 0x00005c28
1684 #define FTQ_DMA_HIGH_READ_WRITE_PEEK 0x00005c2c
1685 #define FTQ_DMA_COMP_DISC_CTL 0x00005c30
1686 #define FTQ_DMA_COMP_DISC_FULL_CNT 0x00005c34
1687 #define FTQ_DMA_COMP_DISC_FIFO_ENQDEQ 0x00005c38
1688 #define FTQ_DMA_COMP_DISC_WRITE_PEEK 0x00005c3c
1689 #define FTQ_SEND_BD_COMP_CTL 0x00005c40
1690 #define FTQ_SEND_BD_COMP_FULL_CNT 0x00005c44
1691 #define FTQ_SEND_BD_COMP_FIFO_ENQDEQ 0x00005c48
1692 #define FTQ_SEND_BD_COMP_WRITE_PEEK 0x00005c4c
1693 #define FTQ_SEND_DATA_INIT_CTL 0x00005c50
1694 #define FTQ_SEND_DATA_INIT_FULL_CNT 0x00005c54
1695 #define FTQ_SEND_DATA_INIT_FIFO_ENQDEQ 0x00005c58
1696 #define FTQ_SEND_DATA_INIT_WRITE_PEEK 0x00005c5c
1697 #define FTQ_DMA_NORM_WRITE_CTL 0x00005c60
1698 #define FTQ_DMA_NORM_WRITE_FULL_CNT 0x00005c64
1699 #define FTQ_DMA_NORM_WRITE_FIFO_ENQDEQ 0x00005c68
1700 #define FTQ_DMA_NORM_WRITE_WRITE_PEEK 0x00005c6c
1701 #define FTQ_DMA_HIGH_WRITE_CTL 0x00005c70
1702 #define FTQ_DMA_HIGH_WRITE_FULL_CNT 0x00005c74
1703 #define FTQ_DMA_HIGH_WRITE_FIFO_ENQDEQ 0x00005c78
1704 #define FTQ_DMA_HIGH_WRITE_WRITE_PEEK 0x00005c7c
1705 #define FTQ_SWTYPE1_CTL 0x00005c80
1706 #define FTQ_SWTYPE1_FULL_CNT 0x00005c84
1707 #define FTQ_SWTYPE1_FIFO_ENQDEQ 0x00005c88
1708 #define FTQ_SWTYPE1_WRITE_PEEK 0x00005c8c
1709 #define FTQ_SEND_DATA_COMP_CTL 0x00005c90
1710 #define FTQ_SEND_DATA_COMP_FULL_CNT 0x00005c94
1711 #define FTQ_SEND_DATA_COMP_FIFO_ENQDEQ 0x00005c98
1712 #define FTQ_SEND_DATA_COMP_WRITE_PEEK 0x00005c9c
1713 #define FTQ_HOST_COAL_CTL 0x00005ca0
1714 #define FTQ_HOST_COAL_FULL_CNT 0x00005ca4
1715 #define FTQ_HOST_COAL_FIFO_ENQDEQ 0x00005ca8
1716 #define FTQ_HOST_COAL_WRITE_PEEK 0x00005cac
1717 #define FTQ_MAC_TX_CTL 0x00005cb0
1718 #define FTQ_MAC_TX_FULL_CNT 0x00005cb4
1719 #define FTQ_MAC_TX_FIFO_ENQDEQ 0x00005cb8
1720 #define FTQ_MAC_TX_WRITE_PEEK 0x00005cbc
1721 #define FTQ_MB_FREE_CTL 0x00005cc0
1722 #define FTQ_MB_FREE_FULL_CNT 0x00005cc4
1723 #define FTQ_MB_FREE_FIFO_ENQDEQ 0x00005cc8
1724 #define FTQ_MB_FREE_WRITE_PEEK 0x00005ccc
1725 #define FTQ_RCVBD_COMP_CTL 0x00005cd0
1726 #define FTQ_RCVBD_COMP_FULL_CNT 0x00005cd4
1727 #define FTQ_RCVBD_COMP_FIFO_ENQDEQ 0x00005cd8
1728 #define FTQ_RCVBD_COMP_WRITE_PEEK 0x00005cdc
1729 #define FTQ_RCVLST_PLMT_CTL 0x00005ce0
1730 #define FTQ_RCVLST_PLMT_FULL_CNT 0x00005ce4
1731 #define FTQ_RCVLST_PLMT_FIFO_ENQDEQ 0x00005ce8
1732 #define FTQ_RCVLST_PLMT_WRITE_PEEK 0x00005cec
1733 #define FTQ_RCVDATA_INI_CTL 0x00005cf0
1734 #define FTQ_RCVDATA_INI_FULL_CNT 0x00005cf4
1735 #define FTQ_RCVDATA_INI_FIFO_ENQDEQ 0x00005cf8
1736 #define FTQ_RCVDATA_INI_WRITE_PEEK 0x00005cfc
1737 #define FTQ_RCVDATA_COMP_CTL 0x00005d00
1738 #define FTQ_RCVDATA_COMP_FULL_CNT 0x00005d04
1739 #define FTQ_RCVDATA_COMP_FIFO_ENQDEQ 0x00005d08
1740 #define FTQ_RCVDATA_COMP_WRITE_PEEK 0x00005d0c
1741 #define FTQ_SWTYPE2_CTL 0x00005d10
1742 #define FTQ_SWTYPE2_FULL_CNT 0x00005d14
1743 #define FTQ_SWTYPE2_FIFO_ENQDEQ 0x00005d18
1744 #define FTQ_SWTYPE2_WRITE_PEEK 0x00005d1c
1745 /* 0x5d20 --> 0x6000 unused */
1747 /* Message signaled interrupt registers */
1748 #define MSGINT_MODE 0x00006000
1749 #define MSGINT_MODE_RESET 0x00000001
1750 #define MSGINT_MODE_ENABLE 0x00000002
1751 #define MSGINT_MODE_ONE_SHOT_DISABLE 0x00000020
1752 #define MSGINT_MODE_MULTIVEC_EN 0x00000080
1753 #define MSGINT_STATUS 0x00006004
1754 #define MSGINT_STATUS_MSI_REQ 0x00000001
1755 #define MSGINT_FIFO 0x00006008
1756 /* 0x600c --> 0x6400 unused */
1758 /* DMA completion registers */
1759 #define DMAC_MODE 0x00006400
1760 #define DMAC_MODE_RESET 0x00000001
1761 #define DMAC_MODE_ENABLE 0x00000002
1762 /* 0x6404 --> 0x6800 unused */
1765 #define GRC_MODE 0x00006800
1766 #define GRC_MODE_UPD_ON_COAL 0x00000001
1767 #define GRC_MODE_BSWAP_NONFRM_DATA 0x00000002
1768 #define GRC_MODE_WSWAP_NONFRM_DATA 0x00000004
1769 #define GRC_MODE_BSWAP_DATA 0x00000010
1770 #define GRC_MODE_WSWAP_DATA 0x00000020
1771 #define GRC_MODE_BYTE_SWAP_B2HRX_DATA 0x00000040
1772 #define GRC_MODE_WORD_SWAP_B2HRX_DATA 0x00000080
1773 #define GRC_MODE_SPLITHDR 0x00000100
1774 #define GRC_MODE_NOFRM_CRACKING 0x00000200
1775 #define GRC_MODE_INCL_CRC 0x00000400
1776 #define GRC_MODE_ALLOW_BAD_FRMS 0x00000800
1777 #define GRC_MODE_NOIRQ_ON_SENDS 0x00002000
1778 #define GRC_MODE_NOIRQ_ON_RCV 0x00004000
1779 #define GRC_MODE_FORCE_PCI32BIT 0x00008000
1780 #define GRC_MODE_B2HRX_ENABLE 0x00008000
1781 #define GRC_MODE_HOST_STACKUP 0x00010000
1782 #define GRC_MODE_HOST_SENDBDS 0x00020000
1783 #define GRC_MODE_HTX2B_ENABLE 0x00040000
1784 #define GRC_MODE_NO_TX_PHDR_CSUM 0x00100000
1785 #define GRC_MODE_NVRAM_WR_ENABLE 0x00200000
1786 #define GRC_MODE_PCIE_TL_SEL 0x00000000
1787 #define GRC_MODE_PCIE_PL_SEL 0x00400000
1788 #define GRC_MODE_NO_RX_PHDR_CSUM 0x00800000
1789 #define GRC_MODE_IRQ_ON_TX_CPU_ATTN 0x01000000
1790 #define GRC_MODE_IRQ_ON_RX_CPU_ATTN 0x02000000
1791 #define GRC_MODE_IRQ_ON_MAC_ATTN 0x04000000
1792 #define GRC_MODE_IRQ_ON_DMA_ATTN 0x08000000
1793 #define GRC_MODE_IRQ_ON_FLOW_ATTN 0x10000000
1794 #define GRC_MODE_4X_NIC_SEND_RINGS 0x20000000
1795 #define GRC_MODE_PCIE_DL_SEL 0x20000000
1796 #define GRC_MODE_MCAST_FRM_ENABLE 0x40000000
1797 #define GRC_MODE_PCIE_HI_1K_EN 0x80000000
1798 #define GRC_MODE_PCIE_PORT_MASK (GRC_MODE_PCIE_TL_SEL | \
1799 GRC_MODE_PCIE_PL_SEL | \
1800 GRC_MODE_PCIE_DL_SEL | \
1801 GRC_MODE_PCIE_HI_1K_EN)
1802 #define GRC_MISC_CFG 0x00006804
1803 #define GRC_MISC_CFG_CORECLK_RESET 0x00000001
1804 #define GRC_MISC_CFG_PRESCALAR_MASK 0x000000fe
1805 #define GRC_MISC_CFG_PRESCALAR_SHIFT 1
1806 #define GRC_MISC_CFG_BOARD_ID_MASK 0x0001e000
1807 #define GRC_MISC_CFG_BOARD_ID_5700 0x0001e000
1808 #define GRC_MISC_CFG_BOARD_ID_5701 0x00000000
1809 #define GRC_MISC_CFG_BOARD_ID_5702FE 0x00004000
1810 #define GRC_MISC_CFG_BOARD_ID_5703 0x00000000
1811 #define GRC_MISC_CFG_BOARD_ID_5703S 0x00002000
1812 #define GRC_MISC_CFG_BOARD_ID_5704 0x00000000
1813 #define GRC_MISC_CFG_BOARD_ID_5704CIOBE 0x00004000
1814 #define GRC_MISC_CFG_BOARD_ID_5704_A2 0x00008000
1815 #define GRC_MISC_CFG_BOARD_ID_5788 0x00010000
1816 #define GRC_MISC_CFG_BOARD_ID_5788M 0x00018000
1817 #define GRC_MISC_CFG_BOARD_ID_AC91002A1 0x00018000
1818 #define GRC_MISC_CFG_EPHY_IDDQ 0x00200000
1819 #define GRC_MISC_CFG_KEEP_GPHY_POWER 0x04000000
1820 #define GRC_LOCAL_CTRL 0x00006808
1821 #define GRC_LCLCTRL_INT_ACTIVE 0x00000001
1822 #define GRC_LCLCTRL_CLEARINT 0x00000002
1823 #define GRC_LCLCTRL_SETINT 0x00000004
1824 #define GRC_LCLCTRL_INT_ON_ATTN 0x00000008
1825 #define GRC_LCLCTRL_GPIO_UART_SEL 0x00000010 /* 5755 only */
1826 #define GRC_LCLCTRL_USE_SIG_DETECT 0x00000010 /* 5714/5780 only */
1827 #define GRC_LCLCTRL_USE_EXT_SIG_DETECT 0x00000020 /* 5714/5780 only */
1828 #define GRC_LCLCTRL_GPIO_INPUT3 0x00000020
1829 #define GRC_LCLCTRL_GPIO_OE3 0x00000040
1830 #define GRC_LCLCTRL_GPIO_OUTPUT3 0x00000080
1831 #define GRC_LCLCTRL_GPIO_INPUT0 0x00000100
1832 #define GRC_LCLCTRL_GPIO_INPUT1 0x00000200
1833 #define GRC_LCLCTRL_GPIO_INPUT2 0x00000400
1834 #define GRC_LCLCTRL_GPIO_OE0 0x00000800
1835 #define GRC_LCLCTRL_GPIO_OE1 0x00001000
1836 #define GRC_LCLCTRL_GPIO_OE2 0x00002000
1837 #define GRC_LCLCTRL_GPIO_OUTPUT0 0x00004000
1838 #define GRC_LCLCTRL_GPIO_OUTPUT1 0x00008000
1839 #define GRC_LCLCTRL_GPIO_OUTPUT2 0x00010000
1840 #define GRC_LCLCTRL_EXTMEM_ENABLE 0x00020000
1841 #define GRC_LCLCTRL_MEMSZ_MASK 0x001c0000
1842 #define GRC_LCLCTRL_MEMSZ_256K 0x00000000
1843 #define GRC_LCLCTRL_MEMSZ_512K 0x00040000
1844 #define GRC_LCLCTRL_MEMSZ_1M 0x00080000
1845 #define GRC_LCLCTRL_MEMSZ_2M 0x000c0000
1846 #define GRC_LCLCTRL_MEMSZ_4M 0x00100000
1847 #define GRC_LCLCTRL_MEMSZ_8M 0x00140000
1848 #define GRC_LCLCTRL_MEMSZ_16M 0x00180000
1849 #define GRC_LCLCTRL_BANK_SELECT 0x00200000
1850 #define GRC_LCLCTRL_SSRAM_TYPE 0x00400000
1851 #define GRC_LCLCTRL_AUTO_SEEPROM 0x01000000
1852 #define GRC_TIMER 0x0000680c
1853 #define GRC_RX_CPU_EVENT 0x00006810
1854 #define GRC_RX_CPU_DRIVER_EVENT 0x00004000
1855 #define GRC_RX_TIMER_REF 0x00006814
1856 #define GRC_RX_CPU_SEM 0x00006818
1857 #define GRC_REMOTE_RX_CPU_ATTN 0x0000681c
1858 #define GRC_TX_CPU_EVENT 0x00006820
1859 #define GRC_TX_TIMER_REF 0x00006824
1860 #define GRC_TX_CPU_SEM 0x00006828
1861 #define GRC_REMOTE_TX_CPU_ATTN 0x0000682c
1862 #define GRC_MEM_POWER_UP 0x00006830 /* 64-bit */
1863 #define GRC_EEPROM_ADDR 0x00006838
1864 #define EEPROM_ADDR_WRITE 0x00000000
1865 #define EEPROM_ADDR_READ 0x80000000
1866 #define EEPROM_ADDR_COMPLETE 0x40000000
1867 #define EEPROM_ADDR_FSM_RESET 0x20000000
1868 #define EEPROM_ADDR_DEVID_MASK 0x1c000000
1869 #define EEPROM_ADDR_DEVID_SHIFT 26
1870 #define EEPROM_ADDR_START 0x02000000
1871 #define EEPROM_ADDR_CLKPERD_SHIFT 16
1872 #define EEPROM_ADDR_ADDR_MASK 0x0000ffff
1873 #define EEPROM_ADDR_ADDR_SHIFT 0
1874 #define EEPROM_DEFAULT_CLOCK_PERIOD 0x60
1875 #define EEPROM_CHIP_SIZE (64 * 1024)
1876 #define GRC_EEPROM_DATA 0x0000683c
1877 #define GRC_EEPROM_CTRL 0x00006840
1878 #define GRC_MDI_CTRL 0x00006844
1879 #define GRC_SEEPROM_DELAY 0x00006848
1880 /* 0x684c --> 0x6890 unused */
1881 #define GRC_VCPU_EXT_CTRL 0x00006890
1882 #define GRC_VCPU_EXT_CTRL_HALT_CPU 0x00400000
1883 #define GRC_VCPU_EXT_CTRL_DISABLE_WOL 0x20000000
1884 #define GRC_FASTBOOT_PC 0x00006894 /* 5752, 5755, 5787 */
1886 /* 0x6c00 --> 0x7000 unused */
1888 /* NVRAM Control registers */
1889 #define NVRAM_CMD 0x00007000
1890 #define NVRAM_CMD_RESET 0x00000001
1891 #define NVRAM_CMD_DONE 0x00000008
1892 #define NVRAM_CMD_GO 0x00000010
1893 #define NVRAM_CMD_WR 0x00000020
1894 #define NVRAM_CMD_RD 0x00000000
1895 #define NVRAM_CMD_ERASE 0x00000040
1896 #define NVRAM_CMD_FIRST 0x00000080
1897 #define NVRAM_CMD_LAST 0x00000100
1898 #define NVRAM_CMD_WREN 0x00010000
1899 #define NVRAM_CMD_WRDI 0x00020000
1900 #define NVRAM_STAT 0x00007004
1901 #define NVRAM_WRDATA 0x00007008
1902 #define NVRAM_ADDR 0x0000700c
1903 #define NVRAM_ADDR_MSK 0x00ffffff
1904 #define NVRAM_RDDATA 0x00007010
1905 #define NVRAM_CFG1 0x00007014
1906 #define NVRAM_CFG1_FLASHIF_ENAB 0x00000001
1907 #define NVRAM_CFG1_BUFFERED_MODE 0x00000002
1908 #define NVRAM_CFG1_PASS_THRU 0x00000004
1909 #define NVRAM_CFG1_STATUS_BITS 0x00000070
1910 #define NVRAM_CFG1_BIT_BANG 0x00000008
1911 #define NVRAM_CFG1_FLASH_SIZE 0x02000000
1912 #define NVRAM_CFG1_COMPAT_BYPASS 0x80000000
1913 #define NVRAM_CFG1_VENDOR_MASK 0x03000003
1914 #define FLASH_VENDOR_ATMEL_EEPROM 0x02000000
1915 #define FLASH_VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1916 #define FLASH_VENDOR_ATMEL_FLASH_UNBUFFERED 0x00000003
1917 #define FLASH_VENDOR_ST 0x03000001
1918 #define FLASH_VENDOR_SAIFUN 0x01000003
1919 #define FLASH_VENDOR_SST_SMALL 0x00000001
1920 #define FLASH_VENDOR_SST_LARGE 0x02000001
1921 #define NVRAM_CFG1_5752VENDOR_MASK 0x03c00003
1922 #define FLASH_5752VENDOR_ATMEL_EEPROM_64KHZ 0x00000000
1923 #define FLASH_5752VENDOR_ATMEL_EEPROM_376KHZ 0x02000000
1924 #define FLASH_5752VENDOR_ATMEL_FLASH_BUFFERED 0x02000003
1925 #define FLASH_5752VENDOR_ST_M45PE10 0x02400000
1926 #define FLASH_5752VENDOR_ST_M45PE20 0x02400002
1927 #define FLASH_5752VENDOR_ST_M45PE40 0x02400001
1928 #define FLASH_5755VENDOR_ATMEL_FLASH_1 0x03400001
1929 #define FLASH_5755VENDOR_ATMEL_FLASH_2 0x03400002
1930 #define FLASH_5755VENDOR_ATMEL_FLASH_3 0x03400000
1931 #define FLASH_5755VENDOR_ATMEL_FLASH_4 0x00000003
1932 #define FLASH_5755VENDOR_ATMEL_FLASH_5 0x02000003
1933 #define FLASH_5755VENDOR_ATMEL_EEPROM_64KHZ 0x03c00003
1934 #define FLASH_5755VENDOR_ATMEL_EEPROM_376KHZ 0x03c00002
1935 #define FLASH_5787VENDOR_ATMEL_EEPROM_64KHZ 0x03000003
1936 #define FLASH_5787VENDOR_ATMEL_EEPROM_376KHZ 0x03000002
1937 #define FLASH_5787VENDOR_MICRO_EEPROM_64KHZ 0x03000000
1938 #define FLASH_5787VENDOR_MICRO_EEPROM_376KHZ 0x02000000
1939 #define FLASH_5761VENDOR_ATMEL_MDB021D 0x00800003
1940 #define FLASH_5761VENDOR_ATMEL_MDB041D 0x00800000
1941 #define FLASH_5761VENDOR_ATMEL_MDB081D 0x00800002
1942 #define FLASH_5761VENDOR_ATMEL_MDB161D 0x00800001
1943 #define FLASH_5761VENDOR_ATMEL_ADB021D 0x00000003
1944 #define FLASH_5761VENDOR_ATMEL_ADB041D 0x00000000
1945 #define FLASH_5761VENDOR_ATMEL_ADB081D 0x00000002
1946 #define FLASH_5761VENDOR_ATMEL_ADB161D 0x00000001
1947 #define FLASH_5761VENDOR_ST_M_M45PE20 0x02800001
1948 #define FLASH_5761VENDOR_ST_M_M45PE40 0x02800000
1949 #define FLASH_5761VENDOR_ST_M_M45PE80 0x02800002
1950 #define FLASH_5761VENDOR_ST_M_M45PE16 0x02800003
1951 #define FLASH_5761VENDOR_ST_A_M45PE20 0x02000001
1952 #define FLASH_5761VENDOR_ST_A_M45PE40 0x02000000
1953 #define FLASH_5761VENDOR_ST_A_M45PE80 0x02000002
1954 #define FLASH_5761VENDOR_ST_A_M45PE16 0x02000003
1955 #define FLASH_57780VENDOR_ATMEL_AT45DB011D 0x00400000
1956 #define FLASH_57780VENDOR_ATMEL_AT45DB011B 0x03400000
1957 #define FLASH_57780VENDOR_ATMEL_AT45DB021D 0x00400002
1958 #define FLASH_57780VENDOR_ATMEL_AT45DB021B 0x03400002
1959 #define FLASH_57780VENDOR_ATMEL_AT45DB041D 0x00400001
1960 #define FLASH_57780VENDOR_ATMEL_AT45DB041B 0x03400001
1961 #define FLASH_5717VENDOR_ATMEL_EEPROM 0x02000001
1962 #define FLASH_5717VENDOR_MICRO_EEPROM 0x02000003
1963 #define FLASH_5717VENDOR_ATMEL_MDB011D 0x01000001
1964 #define FLASH_5717VENDOR_ATMEL_MDB021D 0x01000003
1965 #define FLASH_5717VENDOR_ST_M_M25PE10 0x02000000
1966 #define FLASH_5717VENDOR_ST_M_M25PE20 0x02000002
1967 #define FLASH_5717VENDOR_ST_M_M45PE10 0x00000001
1968 #define FLASH_5717VENDOR_ST_M_M45PE20 0x00000003
1969 #define FLASH_5717VENDOR_ATMEL_ADB011B 0x01400000
1970 #define FLASH_5717VENDOR_ATMEL_ADB021B 0x01400002
1971 #define FLASH_5717VENDOR_ATMEL_ADB011D 0x01400001
1972 #define FLASH_5717VENDOR_ATMEL_ADB021D 0x01400003
1973 #define FLASH_5717VENDOR_ST_A_M25PE10 0x02400000
1974 #define FLASH_5717VENDOR_ST_A_M25PE20 0x02400002
1975 #define FLASH_5717VENDOR_ST_A_M45PE10 0x02400001
1976 #define FLASH_5717VENDOR_ST_A_M45PE20 0x02400003
1977 #define FLASH_5717VENDOR_ATMEL_45USPT 0x03400000
1978 #define FLASH_5717VENDOR_ST_25USPT 0x03400002
1979 #define FLASH_5717VENDOR_ST_45USPT 0x03400001
1980 #define FLASH_5720_EEPROM_HD 0x00000001
1981 #define FLASH_5720_EEPROM_LD 0x00000003
1982 #define FLASH_5720VENDOR_M_ATMEL_DB011D 0x01000000
1983 #define FLASH_5720VENDOR_M_ATMEL_DB021D 0x01000002
1984 #define FLASH_5720VENDOR_M_ATMEL_DB041D 0x01000001
1985 #define FLASH_5720VENDOR_M_ATMEL_DB081D 0x01000003
1986 #define FLASH_5720VENDOR_M_ST_M25PE10 0x02000000
1987 #define FLASH_5720VENDOR_M_ST_M25PE20 0x02000002
1988 #define FLASH_5720VENDOR_M_ST_M25PE40 0x02000001
1989 #define FLASH_5720VENDOR_M_ST_M25PE80 0x02000003
1990 #define FLASH_5720VENDOR_M_ST_M45PE10 0x03000000
1991 #define FLASH_5720VENDOR_M_ST_M45PE20 0x03000002
1992 #define FLASH_5720VENDOR_M_ST_M45PE40 0x03000001
1993 #define FLASH_5720VENDOR_M_ST_M45PE80 0x03000003
1994 #define FLASH_5720VENDOR_A_ATMEL_DB011B 0x01800000
1995 #define FLASH_5720VENDOR_A_ATMEL_DB021B 0x01800002
1996 #define FLASH_5720VENDOR_A_ATMEL_DB041B 0x01800001
1997 #define FLASH_5720VENDOR_A_ATMEL_DB011D 0x01c00000
1998 #define FLASH_5720VENDOR_A_ATMEL_DB021D 0x01c00002
1999 #define FLASH_5720VENDOR_A_ATMEL_DB041D 0x01c00001
2000 #define FLASH_5720VENDOR_A_ATMEL_DB081D 0x01c00003
2001 #define FLASH_5720VENDOR_A_ST_M25PE10 0x02800000
2002 #define FLASH_5720VENDOR_A_ST_M25PE20 0x02800002
2003 #define FLASH_5720VENDOR_A_ST_M25PE40 0x02800001
2004 #define FLASH_5720VENDOR_A_ST_M25PE80 0x02800003
2005 #define FLASH_5720VENDOR_A_ST_M45PE10 0x02c00000
2006 #define FLASH_5720VENDOR_A_ST_M45PE20 0x02c00002
2007 #define FLASH_5720VENDOR_A_ST_M45PE40 0x02c00001
2008 #define FLASH_5720VENDOR_A_ST_M45PE80 0x02c00003
2009 #define FLASH_5720VENDOR_ATMEL_45USPT 0x03c00000
2010 #define FLASH_5720VENDOR_ST_25USPT 0x03c00002
2011 #define FLASH_5720VENDOR_ST_45USPT 0x03c00001
2012 #define NVRAM_CFG1_5752PAGE_SIZE_MASK 0x70000000
2013 #define FLASH_5752PAGE_SIZE_256 0x00000000
2014 #define FLASH_5752PAGE_SIZE_512 0x10000000
2015 #define FLASH_5752PAGE_SIZE_1K 0x20000000
2016 #define FLASH_5752PAGE_SIZE_2K 0x30000000
2017 #define FLASH_5752PAGE_SIZE_4K 0x40000000
2018 #define FLASH_5752PAGE_SIZE_264 0x50000000
2019 #define FLASH_5752PAGE_SIZE_528 0x60000000
2020 #define NVRAM_CFG2 0x00007018
2021 #define NVRAM_CFG3 0x0000701c
2022 #define NVRAM_SWARB 0x00007020
2023 #define SWARB_REQ_SET0 0x00000001
2024 #define SWARB_REQ_SET1 0x00000002
2025 #define SWARB_REQ_SET2 0x00000004
2026 #define SWARB_REQ_SET3 0x00000008
2027 #define SWARB_REQ_CLR0 0x00000010
2028 #define SWARB_REQ_CLR1 0x00000020
2029 #define SWARB_REQ_CLR2 0x00000040
2030 #define SWARB_REQ_CLR3 0x00000080
2031 #define SWARB_GNT0 0x00000100
2032 #define SWARB_GNT1 0x00000200
2033 #define SWARB_GNT2 0x00000400
2034 #define SWARB_GNT3 0x00000800
2035 #define SWARB_REQ0 0x00001000
2036 #define SWARB_REQ1 0x00002000
2037 #define SWARB_REQ2 0x00004000
2038 #define SWARB_REQ3 0x00008000
2039 #define NVRAM_ACCESS 0x00007024
2040 #define ACCESS_ENABLE 0x00000001
2041 #define ACCESS_WR_ENABLE 0x00000002
2042 #define NVRAM_WRITE1 0x00007028
2045 #define NVRAM_ADDR_LOCKOUT 0x00007030
2046 /* 0x7034 --> 0x7500 unused */
2048 #define OTP_MODE 0x00007500
2049 #define OTP_MODE_OTP_THRU_GRC 0x00000001
2050 #define OTP_CTRL 0x00007504
2051 #define OTP_CTRL_OTP_PROG_ENABLE 0x00200000
2052 #define OTP_CTRL_OTP_CMD_READ 0x00000000
2053 #define OTP_CTRL_OTP_CMD_INIT 0x00000008
2054 #define OTP_CTRL_OTP_CMD_START 0x00000001
2055 #define OTP_STATUS 0x00007508
2056 #define OTP_STATUS_CMD_DONE 0x00000001
2057 #define OTP_ADDRESS 0x0000750c
2058 #define OTP_ADDRESS_MAGIC1 0x000000a0
2059 #define OTP_ADDRESS_MAGIC2 0x00000080
2062 #define OTP_READ_DATA 0x00007514
2063 /* 0x7518 --> 0x7c04 unused */
2065 #define PCIE_TRANSACTION_CFG 0x00007c04
2066 #define PCIE_TRANS_CFG_1SHOT_MSI 0x20000000
2067 #define PCIE_TRANS_CFG_LOM 0x00000020
2068 /* 0x7c08 --> 0x7d28 unused */
2070 #define PCIE_PWR_MGMT_THRESH 0x00007d28
2071 #define PCIE_PWR_MGMT_L1_THRESH_MSK 0x0000ff00
2072 #define PCIE_PWR_MGMT_L1_THRESH_4MS 0x0000ff00
2073 #define PCIE_PWR_MGMT_EXT_ASPM_TMR_EN 0x01000000
2074 /* 0x7d2c --> 0x7d54 unused */
2076 #define TG3_PCIE_LNKCTL 0x00007d54
2077 #define TG3_PCIE_LNKCTL_L1_PLL_PD_EN 0x00000008
2078 #define TG3_PCIE_LNKCTL_L1_PLL_PD_DIS 0x00000080
2079 /* 0x7d58 --> 0x7e70 unused */
2081 #define TG3_PCIE_PHY_TSTCTL 0x00007e2c
2082 #define TG3_PCIE_PHY_TSTCTL_PCIE10 0x00000040
2083 #define TG3_PCIE_PHY_TSTCTL_PSCRAM 0x00000020
2085 #define TG3_PCIE_EIDLE_DELAY 0x00007e70
2086 #define TG3_PCIE_EIDLE_DELAY_MASK 0x0000001f
2087 #define TG3_PCIE_EIDLE_DELAY_13_CLKS 0x0000000c
2088 /* 0x7e74 --> 0x8000 unused */
2091 /* Alternate PCIE definitions */
2092 #define TG3_PCIE_TLDLPL_PORT 0x00007c00
2093 #define TG3_PCIE_DL_LO_FTSMAX 0x0000000c
2094 #define TG3_PCIE_DL_LO_FTSMAX_MSK 0x000000ff
2095 #define TG3_PCIE_DL_LO_FTSMAX_VAL 0x0000002c
2096 #define TG3_PCIE_PL_LO_PHYCTL1 0x00000004
2097 #define TG3_PCIE_PL_LO_PHYCTL1_L1PLLPD_EN 0x00001000
2098 #define TG3_PCIE_PL_LO_PHYCTL5 0x00000014
2099 #define TG3_PCIE_PL_LO_PHYCTL5_DIS_L2CLKREQ 0x80000000
2101 #define TG3_REG_BLK_SIZE 0x00008000
2103 /* OTP bit definitions */
2104 #define TG3_OTP_AGCTGT_MASK 0x000000e0
2105 #define TG3_OTP_AGCTGT_SHIFT 1
2106 #define TG3_OTP_HPFFLTR_MASK 0x00000300
2107 #define TG3_OTP_HPFFLTR_SHIFT 1
2108 #define TG3_OTP_HPFOVER_MASK 0x00000400
2109 #define TG3_OTP_HPFOVER_SHIFT 1
2110 #define TG3_OTP_LPFDIS_MASK 0x00000800
2111 #define TG3_OTP_LPFDIS_SHIFT 11
2112 #define TG3_OTP_VDAC_MASK 0xff000000
2113 #define TG3_OTP_VDAC_SHIFT 24
2114 #define TG3_OTP_10BTAMP_MASK 0x0000f000
2115 #define TG3_OTP_10BTAMP_SHIFT 8
2116 #define TG3_OTP_ROFF_MASK 0x00e00000
2117 #define TG3_OTP_ROFF_SHIFT 11
2118 #define TG3_OTP_RCOFF_MASK 0x001c0000
2119 #define TG3_OTP_RCOFF_SHIFT 16
2121 #define TG3_OTP_DEFAULT 0x286c1640
2124 /* Hardware Legacy NVRAM layout */
2125 #define TG3_NVM_VPD_OFF 0x100
2126 #define TG3_NVM_VPD_LEN 256
2128 /* Hardware Selfboot NVRAM layout */
2129 #define TG3_NVM_HWSB_CFG1 0x00000004
2130 #define TG3_NVM_HWSB_CFG1_MAJMSK 0xf8000000
2131 #define TG3_NVM_HWSB_CFG1_MAJSFT 27
2132 #define TG3_NVM_HWSB_CFG1_MINMSK 0x07c00000
2133 #define TG3_NVM_HWSB_CFG1_MINSFT 22
2135 #define TG3_EEPROM_MAGIC 0x669955aa
2136 #define TG3_EEPROM_MAGIC_FW 0xa5000000
2137 #define TG3_EEPROM_MAGIC_FW_MSK 0xff000000
2138 #define TG3_EEPROM_SB_FORMAT_MASK 0x00e00000
2139 #define TG3_EEPROM_SB_FORMAT_1 0x00200000
2140 #define TG3_EEPROM_SB_REVISION_MASK 0x001f0000
2141 #define TG3_EEPROM_SB_REVISION_0 0x00000000
2142 #define TG3_EEPROM_SB_REVISION_2 0x00020000
2143 #define TG3_EEPROM_SB_REVISION_3 0x00030000
2144 #define TG3_EEPROM_SB_REVISION_4 0x00040000
2145 #define TG3_EEPROM_SB_REVISION_5 0x00050000
2146 #define TG3_EEPROM_SB_REVISION_6 0x00060000
2147 #define TG3_EEPROM_MAGIC_HW 0xabcd
2148 #define TG3_EEPROM_MAGIC_HW_MSK 0xffff
2150 #define TG3_NVM_DIR_START 0x18
2151 #define TG3_NVM_DIR_END 0x78
2152 #define TG3_NVM_DIRENT_SIZE 0xc
2153 #define TG3_NVM_DIRTYPE_SHIFT 24
2154 #define TG3_NVM_DIRTYPE_LENMSK 0x003fffff
2155 #define TG3_NVM_DIRTYPE_ASFINI 1
2156 #define TG3_NVM_DIRTYPE_EXTVPD 20
2157 #define TG3_NVM_PTREV_BCVER 0x94
2158 #define TG3_NVM_BCVER_MAJMSK 0x0000ff00
2159 #define TG3_NVM_BCVER_MAJSFT 8
2160 #define TG3_NVM_BCVER_MINMSK 0x000000ff
2162 #define TG3_EEPROM_SB_F1R0_EDH_OFF 0x10
2163 #define TG3_EEPROM_SB_F1R2_EDH_OFF 0x14
2164 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2165 #define TG3_EEPROM_SB_F1R3_EDH_OFF 0x18
2166 #define TG3_EEPROM_SB_F1R4_EDH_OFF 0x1c
2167 #define TG3_EEPROM_SB_F1R5_EDH_OFF 0x20
2168 #define TG3_EEPROM_SB_F1R6_EDH_OFF 0x4c
2169 #define TG3_EEPROM_SB_EDH_MAJ_MASK 0x00000700
2170 #define TG3_EEPROM_SB_EDH_MAJ_SHFT 8
2171 #define TG3_EEPROM_SB_EDH_MIN_MASK 0x000000ff
2172 #define TG3_EEPROM_SB_EDH_BLD_MASK 0x0000f800
2173 #define TG3_EEPROM_SB_EDH_BLD_SHFT 11
2176 /* 32K Window into NIC internal memory */
2177 #define NIC_SRAM_WIN_BASE 0x00008000
2179 /* Offsets into first 32k of NIC internal memory. */
2180 #define NIC_SRAM_PAGE_ZERO 0x00000000
2181 #define NIC_SRAM_SEND_RCB 0x00000100 /* 16 * TG3_BDINFO_... */
2182 #define NIC_SRAM_RCV_RET_RCB 0x00000200 /* 16 * TG3_BDINFO_... */
2183 #define NIC_SRAM_STATS_BLK 0x00000300
2184 #define NIC_SRAM_STATUS_BLK 0x00000b00
2186 #define NIC_SRAM_FIRMWARE_MBOX 0x00000b50
2187 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC1 0x4B657654
2188 #define NIC_SRAM_FIRMWARE_MBOX_MAGIC2 0x4861764b /* !dma on linkchg */
2190 #define NIC_SRAM_DATA_SIG 0x00000b54
2191 #define NIC_SRAM_DATA_SIG_MAGIC 0x4b657654 /* ascii for 'KevT' */
2193 #define NIC_SRAM_DATA_CFG 0x00000b58
2194 #define NIC_SRAM_DATA_CFG_LED_MODE_MASK 0x0000000c
2195 #define NIC_SRAM_DATA_CFG_LED_MODE_MAC 0x00000000
2196 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_1 0x00000004
2197 #define NIC_SRAM_DATA_CFG_LED_MODE_PHY_2 0x00000008
2198 #define NIC_SRAM_DATA_CFG_PHY_TYPE_MASK 0x00000030
2199 #define NIC_SRAM_DATA_CFG_PHY_TYPE_UNKNOWN 0x00000000
2200 #define NIC_SRAM_DATA_CFG_PHY_TYPE_COPPER 0x00000010
2201 #define NIC_SRAM_DATA_CFG_PHY_TYPE_FIBER 0x00000020
2202 #define NIC_SRAM_DATA_CFG_WOL_ENABLE 0x00000040
2203 #define NIC_SRAM_DATA_CFG_ASF_ENABLE 0x00000080
2204 #define NIC_SRAM_DATA_CFG_EEPROM_WP 0x00000100
2205 #define NIC_SRAM_DATA_CFG_MINI_PCI 0x00001000
2206 #define NIC_SRAM_DATA_CFG_FIBER_WOL 0x00004000
2207 #define NIC_SRAM_DATA_CFG_NO_GPIO2 0x00100000
2208 #define NIC_SRAM_DATA_CFG_APE_ENABLE 0x00200000
2210 #define NIC_SRAM_DATA_VER 0x00000b5c
2211 #define NIC_SRAM_DATA_VER_SHIFT 16
2213 #define NIC_SRAM_DATA_PHY_ID 0x00000b74
2214 #define NIC_SRAM_DATA_PHY_ID1_MASK 0xffff0000
2215 #define NIC_SRAM_DATA_PHY_ID2_MASK 0x0000ffff
2217 #define NIC_SRAM_FW_CMD_MBOX 0x00000b78
2218 #define FWCMD_NICDRV_ALIVE 0x00000001
2219 #define FWCMD_NICDRV_PAUSE_FW 0x00000002
2220 #define FWCMD_NICDRV_IPV4ADDR_CHG 0x00000003
2221 #define FWCMD_NICDRV_IPV6ADDR_CHG 0x00000004
2222 #define FWCMD_NICDRV_FIX_DMAR 0x00000005
2223 #define FWCMD_NICDRV_FIX_DMAW 0x00000006
2224 #define FWCMD_NICDRV_LINK_UPDATE 0x0000000c
2225 #define FWCMD_NICDRV_ALIVE2 0x0000000d
2226 #define FWCMD_NICDRV_ALIVE3 0x0000000e
2227 #define NIC_SRAM_FW_CMD_LEN_MBOX 0x00000b7c
2228 #define NIC_SRAM_FW_CMD_DATA_MBOX 0x00000b80
2229 #define NIC_SRAM_FW_ASF_STATUS_MBOX 0x00000c00
2230 #define NIC_SRAM_FW_DRV_STATE_MBOX 0x00000c04
2231 #define DRV_STATE_START 0x00000001
2232 #define DRV_STATE_START_DONE 0x80000001
2233 #define DRV_STATE_UNLOAD 0x00000002
2234 #define DRV_STATE_UNLOAD_DONE 0x80000002
2235 #define DRV_STATE_WOL 0x00000003
2236 #define DRV_STATE_SUSPEND 0x00000004
2238 #define NIC_SRAM_FW_RESET_TYPE_MBOX 0x00000c08
2240 #define NIC_SRAM_MAC_ADDR_HIGH_MBOX 0x00000c14
2241 #define NIC_SRAM_MAC_ADDR_LOW_MBOX 0x00000c18
2243 #define NIC_SRAM_WOL_MBOX 0x00000d30
2244 #define WOL_SIGNATURE 0x474c0000
2245 #define WOL_DRV_STATE_SHUTDOWN 0x00000001
2246 #define WOL_DRV_WOL 0x00000002
2247 #define WOL_SET_MAGIC_PKT 0x00000004
2249 #define NIC_SRAM_DATA_CFG_2 0x00000d38
2251 #define NIC_SRAM_DATA_CFG_2_APD_EN 0x00000400
2252 #define SHASTA_EXT_LED_MODE_MASK 0x00018000
2253 #define SHASTA_EXT_LED_LEGACY 0x00000000
2254 #define SHASTA_EXT_LED_SHARED 0x00008000
2255 #define SHASTA_EXT_LED_MAC 0x00010000
2256 #define SHASTA_EXT_LED_COMBO 0x00018000
2258 #define NIC_SRAM_DATA_CFG_3 0x00000d3c
2259 #define NIC_SRAM_ASPM_DEBOUNCE 0x00000002
2261 #define NIC_SRAM_DATA_CFG_4 0x00000d60
2262 #define NIC_SRAM_GMII_MODE 0x00000002
2263 #define NIC_SRAM_RGMII_INBAND_DISABLE 0x00000004
2264 #define NIC_SRAM_RGMII_EXT_IBND_RX_EN 0x00000008
2265 #define NIC_SRAM_RGMII_EXT_IBND_TX_EN 0x00000010
2267 #define NIC_SRAM_RX_MINI_BUFFER_DESC 0x00001000
2269 #define NIC_SRAM_DMA_DESC_POOL_BASE 0x00002000
2270 #define NIC_SRAM_DMA_DESC_POOL_SIZE 0x00002000
2271 #define NIC_SRAM_TX_BUFFER_DESC 0x00004000 /* 512 entries */
2272 #define NIC_SRAM_RX_BUFFER_DESC 0x00006000 /* 256 entries */
2273 #define NIC_SRAM_RX_JUMBO_BUFFER_DESC 0x00007000 /* 256 entries */
2274 #define NIC_SRAM_MBUF_POOL_BASE 0x00008000
2275 #define NIC_SRAM_MBUF_POOL_SIZE96 0x00018000
2276 #define NIC_SRAM_MBUF_POOL_SIZE64 0x00010000
2277 #define NIC_SRAM_MBUF_POOL_BASE5705 0x00010000
2278 #define NIC_SRAM_MBUF_POOL_SIZE5705 0x0000e000
2280 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5700 128
2281 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5755 64
2282 #define TG3_SRAM_RX_STD_BDCACHE_SIZE_5906 32
2284 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5700 64
2285 #define TG3_SRAM_RX_JMB_BDCACHE_SIZE_5717 16
2288 /* Currently this is fixed. */
2289 #define TG3_PHY_MII_ADDR 0x01
2292 /*** Tigon3 specific PHY MII registers. ***/
2293 #define TG3_BMCR_SPEED1000 0x0040
2295 #define MII_TG3_CTRL 0x09 /* 1000-baseT control register */
2296 #define MII_TG3_CTRL_ADV_1000_HALF 0x0100
2297 #define MII_TG3_CTRL_ADV_1000_FULL 0x0200
2298 #define MII_TG3_CTRL_AS_MASTER 0x0800
2299 #define MII_TG3_CTRL_ENABLE_AS_MASTER 0x1000
2301 #define MII_TG3_MMD_CTRL 0x0d /* MMD Access Control register */
2302 #define MII_TG3_MMD_CTRL_DATA_NOINC 0x4000
2303 #define MII_TG3_MMD_ADDRESS 0x0e /* MMD Address Data register */
2305 #define MII_TG3_EXT_CTRL 0x10 /* Extended control register */
2306 #define MII_TG3_EXT_CTRL_FIFO_ELASTIC 0x0001
2307 #define MII_TG3_EXT_CTRL_LNK3_LED_MODE 0x0002
2308 #define MII_TG3_EXT_CTRL_FORCE_LED_OFF 0x0008
2309 #define MII_TG3_EXT_CTRL_TBI 0x8000
2311 #define MII_TG3_EXT_STAT 0x11 /* Extended status register */
2312 #define MII_TG3_EXT_STAT_LPASS 0x0100
2314 #define MII_TG3_RXR_COUNTERS 0x14 /* Local/Remote Receiver Counts */
2315 #define MII_TG3_DSP_RW_PORT 0x15 /* DSP coefficient read/write port */
2316 #define MII_TG3_DSP_CONTROL 0x16 /* DSP control register */
2317 #define MII_TG3_DSP_ADDRESS 0x17 /* DSP address register */
2319 #define MII_TG3_DSP_TAP1 0x0001
2320 #define MII_TG3_DSP_TAP1_AGCTGT_DFLT 0x0007
2321 #define MII_TG3_DSP_TAP26 0x001a
2322 #define MII_TG3_DSP_TAP26_ALNOKO 0x0001
2323 #define MII_TG3_DSP_TAP26_RMRXSTO 0x0002
2324 #define MII_TG3_DSP_TAP26_OPCSINPT 0x0004
2325 #define MII_TG3_DSP_AADJ1CH0 0x001f
2326 #define MII_TG3_DSP_CH34TP2 0x4022
2327 #define MII_TG3_DSP_CH34TP2_HIBW01 0x017b
2328 #define MII_TG3_DSP_AADJ1CH3 0x601f
2329 #define MII_TG3_DSP_AADJ1CH3_ADCCKADJ 0x0002
2330 #define MII_TG3_DSP_EXP1_INT_STAT 0x0f01
2331 #define MII_TG3_DSP_EXP8 0x0f08
2332 #define MII_TG3_DSP_EXP8_REJ2MHz 0x0001
2333 #define MII_TG3_DSP_EXP8_AEDW 0x0200
2334 #define MII_TG3_DSP_EXP75 0x0f75
2335 #define MII_TG3_DSP_EXP96 0x0f96
2336 #define MII_TG3_DSP_EXP97 0x0f97
2338 #define MII_TG3_AUX_CTRL 0x18 /* auxiliary control register */
2340 #define MII_TG3_AUXCTL_SHDWSEL_AUXCTL 0x0000
2341 #define MII_TG3_AUXCTL_ACTL_TX_6DB 0x0400
2342 #define MII_TG3_AUXCTL_ACTL_SMDSP_ENA 0x0800
2343 #define MII_TG3_AUXCTL_ACTL_EXTPKTLEN 0x4000
2345 #define MII_TG3_AUXCTL_SHDWSEL_PWRCTL 0x0002
2346 #define MII_TG3_AUXCTL_PCTL_WOL_EN 0x0008
2347 #define MII_TG3_AUXCTL_PCTL_100TX_LPWR 0x0010
2348 #define MII_TG3_AUXCTL_PCTL_SPR_ISOLATE 0x0020
2349 #define MII_TG3_AUXCTL_PCTL_CL_AB_TXDAC 0x0040
2350 #define MII_TG3_AUXCTL_PCTL_VREG_11V 0x0180
2352 #define MII_TG3_AUXCTL_SHDWSEL_MISCTEST 0x0004
2354 #define MII_TG3_AUXCTL_SHDWSEL_MISC 0x0007
2355 #define MII_TG3_AUXCTL_MISC_WIRESPD_EN 0x0010
2356 #define MII_TG3_AUXCTL_MISC_FORCE_AMDIX 0x0200
2357 #define MII_TG3_AUXCTL_MISC_RDSEL_SHIFT 12
2358 #define MII_TG3_AUXCTL_MISC_WREN 0x8000
2361 #define MII_TG3_AUX_STAT 0x19 /* auxiliary status register */
2362 #define MII_TG3_AUX_STAT_LPASS 0x0004
2363 #define MII_TG3_AUX_STAT_SPDMASK 0x0700
2364 #define MII_TG3_AUX_STAT_10HALF 0x0100
2365 #define MII_TG3_AUX_STAT_10FULL 0x0200
2366 #define MII_TG3_AUX_STAT_100HALF 0x0300
2367 #define MII_TG3_AUX_STAT_100_4 0x0400
2368 #define MII_TG3_AUX_STAT_100FULL 0x0500
2369 #define MII_TG3_AUX_STAT_1000HALF 0x0600
2370 #define MII_TG3_AUX_STAT_1000FULL 0x0700
2371 #define MII_TG3_AUX_STAT_100 0x0008
2372 #define MII_TG3_AUX_STAT_FULL 0x0001
2374 #define MII_TG3_ISTAT 0x1a /* IRQ status register */
2375 #define MII_TG3_IMASK 0x1b /* IRQ mask register */
2377 /* ISTAT/IMASK event bits */
2378 #define MII_TG3_INT_LINKCHG 0x0002
2379 #define MII_TG3_INT_SPEEDCHG 0x0004
2380 #define MII_TG3_INT_DUPLEXCHG 0x0008
2381 #define MII_TG3_INT_ANEG_PAGE_RX 0x0400
2383 #define MII_TG3_MISC_SHDW 0x1c
2384 #define MII_TG3_MISC_SHDW_WREN 0x8000
2386 #define MII_TG3_MISC_SHDW_APD_WKTM_84MS 0x0001
2387 #define MII_TG3_MISC_SHDW_APD_ENABLE 0x0020
2388 #define MII_TG3_MISC_SHDW_APD_SEL 0x2800
2390 #define MII_TG3_MISC_SHDW_SCR5_C125OE 0x0001
2391 #define MII_TG3_MISC_SHDW_SCR5_DLLAPD 0x0002
2392 #define MII_TG3_MISC_SHDW_SCR5_SDTL 0x0004
2393 #define MII_TG3_MISC_SHDW_SCR5_DLPTLM 0x0008
2394 #define MII_TG3_MISC_SHDW_SCR5_LPED 0x0010
2395 #define MII_TG3_MISC_SHDW_SCR5_SEL 0x1400
2397 #define MII_TG3_TEST1 0x1e
2398 #define MII_TG3_TEST1_TRIM_EN 0x0010
2399 #define MII_TG3_TEST1_CRC_EN 0x8000
2401 /* Clause 45 expansion registers */
2402 #define TG3_CL45_D7_EEERES_STAT 0x803e
2403 #define TG3_CL45_D7_EEERES_STAT_LP_100TX 0x0002
2404 #define TG3_CL45_D7_EEERES_STAT_LP_1000T 0x0004
2407 /* Fast Ethernet Tranceiver definitions */
2408 #define MII_TG3_FET_PTEST 0x17
2409 #define MII_TG3_FET_PTEST_FRC_TX_LINK 0x1000
2410 #define MII_TG3_FET_PTEST_FRC_TX_LOCK 0x0800
2412 #define MII_TG3_FET_TEST 0x1f
2413 #define MII_TG3_FET_SHADOW_EN 0x0080
2415 #define MII_TG3_FET_SHDW_MISCCTRL 0x10
2416 #define MII_TG3_FET_SHDW_MISCCTRL_MDIX 0x4000
2418 #define MII_TG3_FET_SHDW_AUXMODE4 0x1a
2419 #define MII_TG3_FET_SHDW_AUXMODE4_SBPD 0x0008
2421 #define MII_TG3_FET_SHDW_AUXSTAT2 0x1b
2422 #define MII_TG3_FET_SHDW_AUXSTAT2_APD 0x0020
2425 /* APE registers. Accessible through BAR1 */
2426 #define TG3_APE_EVENT 0x000c
2427 #define APE_EVENT_1 0x00000001
2428 #define TG3_APE_LOCK_REQ 0x002c
2429 #define APE_LOCK_REQ_DRIVER 0x00001000
2430 #define TG3_APE_LOCK_GRANT 0x004c
2431 #define APE_LOCK_GRANT_DRIVER 0x00001000
2432 #define TG3_APE_SEG_SIG 0x4000
2433 #define APE_SEG_SIG_MAGIC 0x41504521
2435 /* APE shared memory. Accessible through BAR1 */
2436 #define TG3_APE_FW_STATUS 0x400c
2437 #define APE_FW_STATUS_READY 0x00000100
2438 #define TG3_APE_FW_FEATURES 0x4010
2439 #define TG3_APE_FW_FEATURE_NCSI 0x00000002
2440 #define TG3_APE_FW_VERSION 0x4018
2441 #define APE_FW_VERSION_MAJMSK 0xff000000
2442 #define APE_FW_VERSION_MAJSFT 24
2443 #define APE_FW_VERSION_MINMSK 0x00ff0000
2444 #define APE_FW_VERSION_MINSFT 16
2445 #define APE_FW_VERSION_REVMSK 0x0000ff00
2446 #define APE_FW_VERSION_REVSFT 8
2447 #define APE_FW_VERSION_BLDMSK 0x000000ff
2448 #define TG3_APE_HOST_SEG_SIG 0x4200
2449 #define APE_HOST_SEG_SIG_MAGIC 0x484f5354
2450 #define TG3_APE_HOST_SEG_LEN 0x4204
2451 #define APE_HOST_SEG_LEN_MAGIC 0x00000020
2452 #define TG3_APE_HOST_INIT_COUNT 0x4208
2453 #define TG3_APE_HOST_DRIVER_ID 0x420c
2454 #define APE_HOST_DRIVER_ID_LINUX 0xf0000000
2455 #define APE_HOST_DRIVER_ID_MAGIC(maj, min) \
2456 (APE_HOST_DRIVER_ID_LINUX | (maj & 0xff) << 16 | (min & 0xff) << 8)
2457 #define TG3_APE_HOST_BEHAVIOR 0x4210
2458 #define APE_HOST_BEHAV_NO_PHYLOCK 0x00000001
2459 #define TG3_APE_HOST_HEARTBEAT_INT_MS 0x4214
2460 #define APE_HOST_HEARTBEAT_INT_DISABLE 0
2461 #define APE_HOST_HEARTBEAT_INT_5SEC 5000
2462 #define TG3_APE_HOST_HEARTBEAT_COUNT 0x4218
2463 #define TG3_APE_HOST_DRVR_STATE 0x421c
2464 #define TG3_APE_HOST_DRVR_STATE_START 0x00000001
2465 #define TG3_APE_HOST_DRVR_STATE_UNLOAD 0x00000002
2466 #define TG3_APE_HOST_DRVR_STATE_WOL 0x00000003
2467 #define TG3_APE_HOST_WOL_SPEED 0x4224
2468 #define TG3_APE_HOST_WOL_SPEED_AUTO 0x00008000
2470 #define TG3_APE_EVENT_STATUS 0x4300
2472 #define APE_EVENT_STATUS_DRIVER_EVNT 0x00000010
2473 #define APE_EVENT_STATUS_STATE_CHNGE 0x00000500
2474 #define APE_EVENT_STATUS_STATE_START 0x00010000
2475 #define APE_EVENT_STATUS_STATE_UNLOAD 0x00020000
2476 #define APE_EVENT_STATUS_STATE_WOL 0x00030000
2477 #define APE_EVENT_STATUS_STATE_SUSPEND 0x00040000
2478 #define APE_EVENT_STATUS_EVENT_PENDING 0x80000000
2480 #define TG3_APE_PER_LOCK_REQ 0x8400
2481 #define APE_LOCK_PER_REQ_DRIVER 0x00001000
2482 #define TG3_APE_PER_LOCK_GRANT 0x8420
2483 #define APE_PER_LOCK_GRANT_DRIVER 0x00001000
2485 /* APE convenience enumerations. */
2486 #define TG3_APE_LOCK_GRC 1
2487 #define TG3_APE_LOCK_MEM 4
2489 #define TG3_EEPROM_SB_F1R2_MBA_OFF 0x10
2492 /* There are two ways to manage the TX descriptors on the tigon3.
2493 * Either the descriptors are in host DMA'able memory, or they
2494 * exist only in the cards on-chip SRAM. All 16 send bds are under
2495 * the same mode, they may not be configured individually.
2497 * This driver always uses host memory TX descriptors.
2499 * To use host memory TX descriptors:
2500 * 1) Set GRC_MODE_HOST_SENDBDS in GRC_MODE register.
2501 * Make sure GRC_MODE_4X_NIC_SEND_RINGS is clear.
2502 * 2) Allocate DMA'able memory.
2503 * 3) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2504 * a) Set TG3_BDINFO_HOST_ADDR to DMA address of memory
2505 * obtained in step 2
2506 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC.
2507 * c) Set len field of TG3_BDINFO_MAXLEN_FLAGS to number
2508 * of TX descriptors. Leave flags field clear.
2509 * 4) Access TX descriptors via host memory. The chip
2510 * will refetch into local SRAM as needed when producer
2511 * index mailboxes are updated.
2513 * To use on-chip TX descriptors:
2514 * 1) Set GRC_MODE_4X_NIC_SEND_RINGS in GRC_MODE register.
2515 * Make sure GRC_MODE_HOST_SENDBDS is clear.
2516 * 2) In NIC_SRAM_SEND_RCB (of desired index) of on-chip SRAM:
2517 * a) Set TG3_BDINFO_HOST_ADDR to zero.
2518 * b) Set TG3_BDINFO_NIC_ADDR to NIC_SRAM_TX_BUFFER_DESC
2519 * c) TG3_BDINFO_MAXLEN_FLAGS is don't care.
2520 * 3) Access TX descriptors directly in on-chip SRAM
2521 * using normal {read,write}l(). (and not using
2522 * pointer dereferencing of ioremap()'d memory like
2523 * the broken Broadcom driver does)
2525 * Note that BDINFO_FLAGS_DISABLED should be set in the flags field of
2526 * TG3_BDINFO_MAXLEN_FLAGS of all unused SEND_RCB indices.
2528 struct tg3_tx_buffer_desc {
2533 #define TXD_FLAG_TCPUDP_CSUM 0x0001
2534 #define TXD_FLAG_IP_CSUM 0x0002
2535 #define TXD_FLAG_END 0x0004
2536 #define TXD_FLAG_IP_FRAG 0x0008
2537 #define TXD_FLAG_JMB_PKT 0x0008
2538 #define TXD_FLAG_IP_FRAG_END 0x0010
2539 #define TXD_FLAG_VLAN 0x0040
2540 #define TXD_FLAG_COAL_NOW 0x0080
2541 #define TXD_FLAG_CPU_PRE_DMA 0x0100
2542 #define TXD_FLAG_CPU_POST_DMA 0x0200
2543 #define TXD_FLAG_ADD_SRC_ADDR 0x1000
2544 #define TXD_FLAG_CHOOSE_SRC_ADDR 0x6000
2545 #define TXD_FLAG_NO_CRC 0x8000
2546 #define TXD_LEN_SHIFT 16
2549 #define TXD_VLAN_TAG_SHIFT 0
2550 #define TXD_MSS_SHIFT 16
2553 #define TXD_ADDR 0x00UL /* 64-bit */
2554 #define TXD_LEN_FLAGS 0x08UL /* 32-bit (upper 16-bits are len) */
2555 #define TXD_VLAN_TAG 0x0cUL /* 32-bit (upper 16-bits are tag) */
2556 #define TXD_SIZE 0x10UL
2558 struct tg3_rx_buffer_desc {
2563 #define RXD_IDX_MASK 0xffff0000
2564 #define RXD_IDX_SHIFT 16
2565 #define RXD_LEN_MASK 0x0000ffff
2566 #define RXD_LEN_SHIFT 0
2569 #define RXD_TYPE_SHIFT 16
2570 #define RXD_FLAGS_SHIFT 0
2572 #define RXD_FLAG_END 0x0004
2573 #define RXD_FLAG_MINI 0x0800
2574 #define RXD_FLAG_JUMBO 0x0020
2575 #define RXD_FLAG_VLAN 0x0040
2576 #define RXD_FLAG_ERROR 0x0400
2577 #define RXD_FLAG_IP_CSUM 0x1000
2578 #define RXD_FLAG_TCPUDP_CSUM 0x2000
2579 #define RXD_FLAG_IS_TCP 0x4000
2582 #define RXD_IPCSUM_MASK 0xffff0000
2583 #define RXD_IPCSUM_SHIFT 16
2584 #define RXD_TCPCSUM_MASK 0x0000ffff
2585 #define RXD_TCPCSUM_SHIFT 0
2589 #define RXD_VLAN_MASK 0x0000ffff
2591 #define RXD_ERR_BAD_CRC 0x00010000
2592 #define RXD_ERR_COLLISION 0x00020000
2593 #define RXD_ERR_LINK_LOST 0x00040000
2594 #define RXD_ERR_PHY_DECODE 0x00080000
2595 #define RXD_ERR_ODD_NIBBLE_RCVD_MII 0x00100000
2596 #define RXD_ERR_MAC_ABRT 0x00200000
2597 #define RXD_ERR_TOO_SMALL 0x00400000
2598 #define RXD_ERR_NO_RESOURCES 0x00800000
2599 #define RXD_ERR_HUGE_FRAME 0x01000000
2600 #define RXD_ERR_MASK 0xffff0000
2604 #define RXD_OPAQUE_INDEX_MASK 0x0000ffff
2605 #define RXD_OPAQUE_INDEX_SHIFT 0
2606 #define RXD_OPAQUE_RING_STD 0x00010000
2607 #define RXD_OPAQUE_RING_JUMBO 0x00020000
2608 #define RXD_OPAQUE_RING_MINI 0x00040000
2609 #define RXD_OPAQUE_RING_MASK 0x00070000
2612 struct tg3_ext_rx_buffer_desc {
2619 struct tg3_rx_buffer_desc std;
2622 /* We only use this when testing out the DMA engine
2623 * at probe time. This is the internal format of buffer
2624 * descriptors used by the chip at NIC_SRAM_DMA_DESCS.
2626 struct tg3_internal_buffer_desc {
2631 #if __BYTE_ORDER == __BIG_ENDIAN
2644 #define TG3_HW_STATUS_SIZE 0x50
2645 struct tg3_hw_status {
2647 #define SD_STATUS_UPDATED 0x00000001
2648 #define SD_STATUS_LINK_CHG 0x00000002
2649 #define SD_STATUS_ERROR 0x00000004
2653 #if __BYTE_ORDER == __BIG_ENDIAN
2655 u16 rx_jumbo_consumer;
2657 u16 rx_jumbo_consumer;
2661 #if __BYTE_ORDER == __BIG_ENDIAN
2663 u16 rx_mini_consumer;
2665 u16 rx_mini_consumer;
2669 #if __BYTE_ORDER == __BIG_ENDIAN
2683 struct tg3_hw_stats {
2684 u8 __reserved0[0x400-0x300];
2686 /* Statistics maintained by Receive MAC. */
2687 tg3_stat64_t rx_octets;
2689 tg3_stat64_t rx_fragments;
2690 tg3_stat64_t rx_ucast_packets;
2691 tg3_stat64_t rx_mcast_packets;
2692 tg3_stat64_t rx_bcast_packets;
2693 tg3_stat64_t rx_fcs_errors;
2694 tg3_stat64_t rx_align_errors;
2695 tg3_stat64_t rx_xon_pause_rcvd;
2696 tg3_stat64_t rx_xoff_pause_rcvd;
2697 tg3_stat64_t rx_mac_ctrl_rcvd;
2698 tg3_stat64_t rx_xoff_entered;
2699 tg3_stat64_t rx_frame_too_long_errors;
2700 tg3_stat64_t rx_jabbers;
2701 tg3_stat64_t rx_undersize_packets;
2702 tg3_stat64_t rx_in_length_errors;
2703 tg3_stat64_t rx_out_length_errors;
2704 tg3_stat64_t rx_64_or_less_octet_packets;
2705 tg3_stat64_t rx_65_to_127_octet_packets;
2706 tg3_stat64_t rx_128_to_255_octet_packets;
2707 tg3_stat64_t rx_256_to_511_octet_packets;
2708 tg3_stat64_t rx_512_to_1023_octet_packets;
2709 tg3_stat64_t rx_1024_to_1522_octet_packets;
2710 tg3_stat64_t rx_1523_to_2047_octet_packets;
2711 tg3_stat64_t rx_2048_to_4095_octet_packets;
2712 tg3_stat64_t rx_4096_to_8191_octet_packets;
2713 tg3_stat64_t rx_8192_to_9022_octet_packets;
2717 /* Statistics maintained by Transmit MAC. */
2718 tg3_stat64_t tx_octets;
2720 tg3_stat64_t tx_collisions;
2721 tg3_stat64_t tx_xon_sent;
2722 tg3_stat64_t tx_xoff_sent;
2723 tg3_stat64_t tx_flow_control;
2724 tg3_stat64_t tx_mac_errors;
2725 tg3_stat64_t tx_single_collisions;
2726 tg3_stat64_t tx_mult_collisions;
2727 tg3_stat64_t tx_deferred;
2729 tg3_stat64_t tx_excessive_collisions;
2730 tg3_stat64_t tx_late_collisions;
2731 tg3_stat64_t tx_collide_2times;
2732 tg3_stat64_t tx_collide_3times;
2733 tg3_stat64_t tx_collide_4times;
2734 tg3_stat64_t tx_collide_5times;
2735 tg3_stat64_t tx_collide_6times;
2736 tg3_stat64_t tx_collide_7times;
2737 tg3_stat64_t tx_collide_8times;
2738 tg3_stat64_t tx_collide_9times;
2739 tg3_stat64_t tx_collide_10times;
2740 tg3_stat64_t tx_collide_11times;
2741 tg3_stat64_t tx_collide_12times;
2742 tg3_stat64_t tx_collide_13times;
2743 tg3_stat64_t tx_collide_14times;
2744 tg3_stat64_t tx_collide_15times;
2745 tg3_stat64_t tx_ucast_packets;
2746 tg3_stat64_t tx_mcast_packets;
2747 tg3_stat64_t tx_bcast_packets;
2748 tg3_stat64_t tx_carrier_sense_errors;
2749 tg3_stat64_t tx_discards;
2750 tg3_stat64_t tx_errors;
2754 /* Statistics maintained by Receive List Placement. */
2755 tg3_stat64_t COS_rx_packets[16];
2756 tg3_stat64_t COS_rx_filter_dropped;
2757 tg3_stat64_t dma_writeq_full;
2758 tg3_stat64_t dma_write_prioq_full;
2759 tg3_stat64_t rxbds_empty;
2760 tg3_stat64_t rx_discards;
2761 tg3_stat64_t rx_errors;
2762 tg3_stat64_t rx_threshold_hit;
2766 /* Statistics maintained by Send Data Initiator. */
2767 tg3_stat64_t COS_out_packets[16];
2768 tg3_stat64_t dma_readq_full;
2769 tg3_stat64_t dma_read_prioq_full;
2770 tg3_stat64_t tx_comp_queue_full;
2772 /* Statistics maintained by Host Coalescing. */
2773 tg3_stat64_t ring_set_send_prod_index;
2774 tg3_stat64_t ring_status_update;
2775 tg3_stat64_t nic_irqs;
2776 tg3_stat64_t nic_avoided_irqs;
2777 tg3_stat64_t nic_tx_threshold_hit;
2779 /* NOT a part of the hardware statistics block format.
2780 * These stats are here as storage for tg3_periodic_fetch_stats().
2782 tg3_stat64_t mbuf_lwm_thresh_hit;
2784 u8 __reserved4[0xb00-0x9c8];
2787 typedef u32 dma_addr_t;
2789 /* 'mapping' is superfluous as the chip does not write into
2790 * the tx/rx post rings so we could just fetch it from there.
2791 * But the cache behavior is better how we are doing it now.
2794 struct io_buffer *iob;
2795 /// dma_addr_t mapping;
2798 struct tg3_link_config {
2799 /* Describes what we're trying to get. */
2806 /* Describes what we actually have. */
2810 #define SPEED_INVALID 0xffff
2811 #define DUPLEX_INVALID 0xff
2812 #define AUTONEG_INVALID 0xff
2815 /* When we go in and out of low power mode we need
2816 * to swap with this state.
2821 u32 orig_advertising;
2824 struct tg3_bufmgr_config {
2825 u32 mbuf_read_dma_low_water;
2826 u32 mbuf_mac_rx_low_water;
2827 u32 mbuf_high_water;
2829 u32 mbuf_read_dma_low_water_jumbo;
2830 u32 mbuf_mac_rx_low_water_jumbo;
2831 u32 mbuf_high_water_jumbo;
2837 struct tg3_ethtool_stats {
2838 /* Statistics maintained by Receive MAC. */
2841 u64 rx_ucast_packets;
2842 u64 rx_mcast_packets;
2843 u64 rx_bcast_packets;
2845 u64 rx_align_errors;
2846 u64 rx_xon_pause_rcvd;
2847 u64 rx_xoff_pause_rcvd;
2848 u64 rx_mac_ctrl_rcvd;
2849 u64 rx_xoff_entered;
2850 u64 rx_frame_too_long_errors;
2852 u64 rx_undersize_packets;
2853 u64 rx_in_length_errors;
2854 u64 rx_out_length_errors;
2855 u64 rx_64_or_less_octet_packets;
2856 u64 rx_65_to_127_octet_packets;
2857 u64 rx_128_to_255_octet_packets;
2858 u64 rx_256_to_511_octet_packets;
2859 u64 rx_512_to_1023_octet_packets;
2860 u64 rx_1024_to_1522_octet_packets;
2861 u64 rx_1523_to_2047_octet_packets;
2862 u64 rx_2048_to_4095_octet_packets;
2863 u64 rx_4096_to_8191_octet_packets;
2864 u64 rx_8192_to_9022_octet_packets;
2866 /* Statistics maintained by Transmit MAC. */
2871 u64 tx_flow_control;
2873 u64 tx_single_collisions;
2874 u64 tx_mult_collisions;
2876 u64 tx_excessive_collisions;
2877 u64 tx_late_collisions;
2878 u64 tx_collide_2times;
2879 u64 tx_collide_3times;
2880 u64 tx_collide_4times;
2881 u64 tx_collide_5times;
2882 u64 tx_collide_6times;
2883 u64 tx_collide_7times;
2884 u64 tx_collide_8times;
2885 u64 tx_collide_9times;
2886 u64 tx_collide_10times;
2887 u64 tx_collide_11times;
2888 u64 tx_collide_12times;
2889 u64 tx_collide_13times;
2890 u64 tx_collide_14times;
2891 u64 tx_collide_15times;
2892 u64 tx_ucast_packets;
2893 u64 tx_mcast_packets;
2894 u64 tx_bcast_packets;
2895 u64 tx_carrier_sense_errors;
2899 /* Statistics maintained by Receive List Placement. */
2900 u64 dma_writeq_full;
2901 u64 dma_write_prioq_full;
2905 u64 rx_threshold_hit;
2907 /* Statistics maintained by Send Data Initiator. */
2909 u64 dma_read_prioq_full;
2910 u64 tx_comp_queue_full;
2912 /* Statistics maintained by Host Coalescing. */
2913 u64 ring_set_send_prod_index;
2914 u64 ring_status_update;
2916 u64 nic_avoided_irqs;
2917 u64 nic_tx_threshold_hit;
2919 u64 mbuf_lwm_thresh_hit;
2922 /* number of io_buffers to allocate */
2923 #define TG3_DEF_RX_RING_PENDING 8
2925 struct tg3_rx_prodring_set {
2926 u32 rx_std_prod_idx;
2927 u32 rx_std_cons_idx;
2929 struct tg3_rx_buffer_desc *rx_std;
2930 struct io_buffer *rx_iobufs[TG3_DEF_RX_RING_PENDING];
2931 dma_addr_t rx_std_mapping;
2934 #define TG3_IRQ_MAX_VECS_RSS 5
2935 #define TG3_IRQ_MAX_VECS TG3_IRQ_MAX_VECS_RSS
2938 TG3_FLAG_TAGGED_STATUS = 0,
2939 TG3_FLAG_TXD_MBOX_HWBUG,
2940 TG3_FLAG_USE_LINKCHG_REG,
2941 TG3_FLAG_ERROR_PROCESSED,
2942 TG3_FLAG_ENABLE_ASF,
2943 TG3_FLAG_ASPM_WORKAROUND,
2944 TG3_FLAG_POLL_SERDES,
2945 TG3_FLAG_MBOX_WRITE_REORDER,
2946 TG3_FLAG_PCIX_TARGET_HWBUG,
2947 TG3_FLAG_WOL_SPEED_100MB,
2948 TG3_FLAG_WOL_ENABLE,
2949 TG3_FLAG_EEPROM_WRITE_PROT,
2951 TG3_FLAG_NVRAM_BUFFERED,
2952 TG3_FLAG_SUPPORT_MSI,
2953 TG3_FLAG_SUPPORT_MSIX,
2955 TG3_FLAG_PCI_HIGH_SPEED,
2957 TG3_FLAG_SRAM_USE_CONFIG,
2958 TG3_FLAG_TX_RECOVERY_PENDING,
2960 TG3_FLAG_JUMBO_RING_ENABLE,
2961 TG3_FLAG_PAUSE_AUTONEG,
2962 TG3_FLAG_CPMU_PRESENT,
2963 TG3_FLAG_BROKEN_CHECKSUMS,
2964 TG3_FLAG_JUMBO_CAPABLE,
2965 TG3_FLAG_CHIP_RESETTING,
2966 TG3_FLAG_INIT_COMPLETE,
2967 TG3_FLAG_RESTART_TIMER,
2970 TG3_FLAG_MAX_RXPEND_64,
2971 TG3_FLAG_TSO_CAPABLE,
2972 TG3_FLAG_PCI_EXPRESS,
2973 TG3_FLAG_ASF_NEW_HANDSHAKE,
2974 TG3_FLAG_HW_AUTONEG,
2982 TG3_FLAG_USING_MSIX,
2983 TG3_FLAG_ICH_WORKAROUND,
2984 TG3_FLAG_5780_CLASS,
2987 TG3_FLAG_NO_FWARE_REPORTED,
2988 TG3_FLAG_NO_NVRAM_ADDR_TRANS,
2989 TG3_FLAG_ENABLE_APE,
2990 TG3_FLAG_PROTECTED_NVRAM,
2991 TG3_FLAG_MDIOBUS_INITED,
2992 TG3_FLAG_LRG_PROD_RING_CAP,
2993 TG3_FLAG_RGMII_INBAND_DISABLE,
2994 TG3_FLAG_RGMII_EXT_IBND_RX_EN,
2995 TG3_FLAG_RGMII_EXT_IBND_TX_EN,
2996 TG3_FLAG_CLKREQ_BUG,
2999 TG3_FLAG_ENABLE_RSS,
3000 TG3_FLAG_ENABLE_TSS,
3001 TG3_FLAG_4G_DMA_BNDRY_BUG,
3002 TG3_FLAG_USE_JUMBO_BDFLAG,
3003 TG3_FLAG_L1PLLPD_EN,
3004 TG3_FLAG_57765_PLUS,
3005 TG3_FLAG_APE_HAS_NCSI,
3008 /* Add new flags before this comment and TG3_FLAG_NUMBER_OF_FLAGS */
3009 TG3_FLAG_NUMBER_OF_FLAGS, /* Last entry in enum TG3_FLAGS */
3012 /* Following definition is copied from linux-3.0rc1/include/linux/kernel.h */
3013 #define DIV_ROUND_UP(n,d) (((n) + (d) - 1) / (d))
3015 #define BITS_PER_BYTE 8
3016 #define BITS_TO_LONGS(nr) DIV_ROUND_UP(nr, BITS_PER_BYTE * sizeof(long))
3018 #define DECLARE_BITMAP(name,bits) \
3019 unsigned long name[BITS_TO_LONGS(bits)]
3022 /* begin "general, frequently-used members" cacheline section */
3024 /* If the IRQ handler (which runs lockless) needs to be
3025 * quiesced, the following bitmask state is used. The
3026 * SYNC flag is set by non-IRQ context code to initiate
3029 * When the IRQ handler notices that SYNC is set, it
3030 * disables interrupts and returns.
3032 * When all outstanding IRQ handlers have returned after
3033 * the SYNC flag has been set, the setter can be assured
3034 * that interrupts will no longer get run.
3036 * In this way all SMP driver locks are never acquired
3037 * in hw IRQ context, only sw IRQ context or lower.
3039 unsigned int irq_sync;
3041 /* SMP locking strategy:
3043 * lock: Held during reset, PHY access, timer, and when
3044 * updating tg3_flags.
3046 * netif_tx_lock: Held during tg3_start_xmit. tg3_tx holds
3047 * netif_tx_lock when it needs to call
3050 * Both of these locks are to be held with BH safety.
3052 * Because the IRQ handler, tg3_poll, and tg3_start_xmit
3053 * are running lockless, it is necessary to completely
3054 * quiesce the chip with tg3_netif_stop and tg3_full_lock
3055 * before reconfiguring the device.
3057 * indirect_lock: Held when accessing registers indirectly
3058 * with IRQ disabling.
3061 u32 (*read32_mbox) (struct tg3 *, u32);
3062 void (*write32_mbox) (struct tg3 *, u32,
3065 struct net_device *dev;
3066 struct pci_device *pdev;
3070 /* begin "tx thread" cacheline section */
3071 void (*write32_tx_mbox) (struct tg3 *, u32,
3074 /* begin "rx thread" cacheline section */
3075 void (*write32_rx_mbox) (struct tg3 *, u32,
3077 u32 rx_std_max_post;
3080 /* was struct tg3_napi: */
3081 struct tg3_hw_status *hw_status;
3086 /* NOTE: there was a coal_now in struct tg3_napi and struct tg3. We
3087 * didn't use coal_now in struct tg3, so it was removed */
3092 u16 *rx_rcb_prod_idx;
3093 struct tg3_rx_prodring_set prodring;
3094 struct tg3_rx_buffer_desc *rx_rcb;
3099 struct tg3_tx_buffer_desc *tx_ring;
3100 struct ring_info *tx_buffers;
3102 dma_addr_t status_mapping;
3103 dma_addr_t rx_rcb_mapping;
3104 dma_addr_t tx_desc_mapping;
3107 /* begin "everything else" cacheline(s) section */
3108 unsigned long rx_dropped;
3110 DECLARE_BITMAP(tg3_flags, TG3_FLAG_NUMBER_OF_FLAGS);
3113 unsigned long phy_crc_errors;
3117 u16 timer_multiplier;
3122 /* 1 second counter for transient serdes link events */
3124 #define SERDES_AN_TIMEOUT_5704S 2
3125 #define SERDES_PARALLEL_DET_TIMEOUT 1
3126 #define SERDES_AN_TIMEOUT_5714S 1
3128 struct tg3_link_config link_config;
3129 struct tg3_bufmgr_config bufmgr_config;
3131 /* cache h/w values, often passed straight to h/w */
3143 u32 pci_chip_rev_id;
3145 u8 pci_cacheline_sz;
3159 #define TG3_PHY_ID_MASK 0xfffffff0
3160 #define TG3_PHY_ID_BCM5400 0x60008040
3161 #define TG3_PHY_ID_BCM5401 0x60008050
3162 #define TG3_PHY_ID_BCM5411 0x60008070
3163 #define TG3_PHY_ID_BCM5701 0x60008110
3164 #define TG3_PHY_ID_BCM5703 0x60008160
3165 #define TG3_PHY_ID_BCM5704 0x60008190
3166 #define TG3_PHY_ID_BCM5705 0x600081a0
3167 #define TG3_PHY_ID_BCM5750 0x60008180
3168 #define TG3_PHY_ID_BCM5752 0x60008100
3169 #define TG3_PHY_ID_BCM5714 0x60008340
3170 #define TG3_PHY_ID_BCM5780 0x60008350
3171 #define TG3_PHY_ID_BCM5755 0xbc050cc0
3172 #define TG3_PHY_ID_BCM5787 0xbc050ce0
3173 #define TG3_PHY_ID_BCM5756 0xbc050ed0
3174 #define TG3_PHY_ID_BCM5784 0xbc050fa0
3175 #define TG3_PHY_ID_BCM5761 0xbc050fd0
3176 #define TG3_PHY_ID_BCM5718C 0x5c0d8a00
3177 #define TG3_PHY_ID_BCM5718S 0xbc050ff0
3178 #define TG3_PHY_ID_BCM57765 0x5c0d8a40
3179 #define TG3_PHY_ID_BCM5719C 0x5c0d8a20
3180 #define TG3_PHY_ID_BCM5720C 0x5c0d8b60
3181 #define TG3_PHY_ID_BCM5906 0xdc00ac40
3182 #define TG3_PHY_ID_BCM8002 0x60010140
3183 #define TG3_PHY_ID_INVALID 0xffffffff
3185 #define PHY_ID_RTL8211C 0x001cc910
3186 #define PHY_ID_RTL8201E 0x00008200
3188 #define TG3_PHY_ID_REV_MASK 0x0000000f
3189 #define TG3_PHY_REV_BCM5401_B0 0x1
3191 /* This macro assumes the passed PHY ID is
3192 * already masked with TG3_PHY_ID_MASK.
3194 #define TG3_KNOWN_PHY_ID(X) \
3195 ((X) == TG3_PHY_ID_BCM5400 || (X) == TG3_PHY_ID_BCM5401 || \
3196 (X) == TG3_PHY_ID_BCM5411 || (X) == TG3_PHY_ID_BCM5701 || \
3197 (X) == TG3_PHY_ID_BCM5703 || (X) == TG3_PHY_ID_BCM5704 || \
3198 (X) == TG3_PHY_ID_BCM5705 || (X) == TG3_PHY_ID_BCM5750 || \
3199 (X) == TG3_PHY_ID_BCM5752 || (X) == TG3_PHY_ID_BCM5714 || \
3200 (X) == TG3_PHY_ID_BCM5780 || (X) == TG3_PHY_ID_BCM5787 || \
3201 (X) == TG3_PHY_ID_BCM5755 || (X) == TG3_PHY_ID_BCM5756 || \
3202 (X) == TG3_PHY_ID_BCM5906 || (X) == TG3_PHY_ID_BCM5761 || \
3203 (X) == TG3_PHY_ID_BCM5718C || (X) == TG3_PHY_ID_BCM5718S || \
3204 (X) == TG3_PHY_ID_BCM57765 || (X) == TG3_PHY_ID_BCM5719C || \
3205 (X) == TG3_PHY_ID_BCM8002)
3208 #define TG3_PHYFLG_IS_LOW_POWER 0x00000001
3209 #define TG3_PHYFLG_IS_CONNECTED 0x00000002
3210 #define TG3_PHYFLG_USE_MI_INTERRUPT 0x00000004
3211 #define TG3_PHYFLG_PHY_SERDES 0x00000010
3212 #define TG3_PHYFLG_MII_SERDES 0x00000020
3213 #define TG3_PHYFLG_ANY_SERDES (TG3_PHYFLG_PHY_SERDES | \
3214 TG3_PHYFLG_MII_SERDES)
3215 #define TG3_PHYFLG_IS_FET 0x00000040
3216 #define TG3_PHYFLG_10_100_ONLY 0x00000080
3217 #define TG3_PHYFLG_ENABLE_APD 0x00000100
3218 #define TG3_PHYFLG_CAPACITIVE_COUPLING 0x00000200
3219 #define TG3_PHYFLG_NO_ETH_WIRE_SPEED 0x00000400
3220 #define TG3_PHYFLG_JITTER_BUG 0x00000800
3221 #define TG3_PHYFLG_ADJUST_TRIM 0x00001000
3222 #define TG3_PHYFLG_ADC_BUG 0x00002000
3223 #define TG3_PHYFLG_5704_A0_BUG 0x00004000
3224 #define TG3_PHYFLG_BER_BUG 0x00008000
3225 #define TG3_PHYFLG_SERDES_PREEMPHASIS 0x00010000
3226 #define TG3_PHYFLG_PARALLEL_DETECT 0x00020000
3227 #define TG3_PHYFLG_EEE_CAP 0x00040000
3233 #define TG3_BPN_SIZE 24
3234 char board_part_number[TG3_BPN_SIZE];
3235 #define TG3_VER_SIZE 32
3236 char fw_ver[TG3_VER_SIZE];
3237 u32 nic_sram_data_cfg;
3239 struct pci_device *pdev_peer;
3243 #define TG3_NVRAM_SIZE_2KB 0x00000800
3244 #define TG3_NVRAM_SIZE_64KB 0x00010000
3245 #define TG3_NVRAM_SIZE_128KB 0x00020000
3246 #define TG3_NVRAM_SIZE_256KB 0x00040000
3247 #define TG3_NVRAM_SIZE_512KB 0x00080000
3248 #define TG3_NVRAM_SIZE_1MB 0x00100000
3249 #define TG3_NVRAM_SIZE_2MB 0x00200000
3254 #define JEDEC_ATMEL 0x1f
3255 #define JEDEC_ST 0x20
3256 #define JEDEC_SAIFUN 0x4f
3257 #define JEDEC_SST 0xbf
3259 #define ATMEL_AT24C02_CHIP_SIZE TG3_NVRAM_SIZE_2KB
3260 #define ATMEL_AT24C02_PAGE_SIZE (8)
3262 #define ATMEL_AT24C64_CHIP_SIZE TG3_NVRAM_SIZE_64KB
3263 #define ATMEL_AT24C64_PAGE_SIZE (32)
3265 #define ATMEL_AT24C512_CHIP_SIZE TG3_NVRAM_SIZE_512KB
3266 #define ATMEL_AT24C512_PAGE_SIZE (128)
3268 #define ATMEL_AT45DB0X1B_PAGE_POS 9
3269 #define ATMEL_AT45DB0X1B_PAGE_SIZE 264
3271 #define ATMEL_AT25F512_PAGE_SIZE 256
3273 #define ST_M45PEX0_PAGE_SIZE 256
3275 #define SAIFUN_SA25F0XX_PAGE_SIZE 256
3277 #define SST_25VF0X0_PAGE_SIZE 4098
3279 u16 subsystem_vendor;
3280 u16 subsystem_device;
3283 #define ARRAY_SIZE(x) ( sizeof(x) / sizeof((x)[0]) )
3285 #define TG3_TX_RING_SIZE 512
3286 #define TG3_DEF_TX_RING_PENDING (TG3_TX_RING_SIZE - 1)
3288 #define TG3_DMA_ALIGNMENT 16
3290 #define TG3_RX_STD_DMA_SZ (1536 + 64 + 2)
3292 static inline void tw32_mailbox_flush(struct tg3 *tp, u32 off, u32 val)
3294 tp->write32_mbox(tp, off, val);
3295 /// if (!tg3_flag(tp, MBOX_WRITE_REORDER) && !tg3_flag(tp, ICH_WORKAROUND))
3296 /// tp->read32_mbox(tp, off);
3299 u32 tg3_read_indirect_reg32(struct tg3 *tp, u32 off);
3300 void tg3_write_indirect_reg32(struct tg3 *tp, u32 off, u32 val);
3301 u32 tg3_read_indirect_mbox(struct tg3 *tp, u32 off);
3302 void tg3_write_indirect_mbox(struct tg3 *tp, u32 off, u32 val);
3304 #define tw32(reg, val) tg3_write_indirect_reg32(tp, reg, val)
3305 ///#define tw32_mailbox(reg, val) tg3_write_indirect_mbox(((val) & 0xffffffff), tp->regs + (reg))
3306 #define tw32_mailbox(reg, val) tg3_write_indirect_mbox(tp, (reg), (val))
3307 #define tw32_mailbox_f(reg, val) tw32_mailbox_flush(tp, (reg), (val))
3308 #define tw32_f(reg, val) _tw32_flush(tp, (reg), (val), 0)
3309 #define tw32_wait_f(reg, val, us) _tw32_flush(tp, (reg), (val), (us))
3311 #define tw32_tx_mbox(reg, val) tp->write32_tx_mbox(tp, reg, val)
3312 #define tw32_rx_mbox(reg, val) tp->write32_rx_mbox(tp, reg, val)
3314 #define tr32(reg) tg3_read_indirect_reg32(tp, reg)
3315 #define tr32_mailbox(reg) tp->read32_mbox(tp, reg)
3317 /* Functions & macros to verify TG3_FLAGS types */
3319 static inline int variable_test_bit(int nr, volatile const unsigned long *addr)
3323 asm volatile("bt %2,%1\n\t"
3326 : "m" (*(unsigned long *)addr), "Ir" (nr));
3331 static inline int _tg3_flag(enum TG3_FLAGS flag, unsigned long *bits)
3333 return variable_test_bit(flag, bits);
3336 #define BITOP_ADDR(x) "+m" (*(volatile long *) (x))
3338 static inline void __set_bit(int nr, volatile unsigned long *addr)
3340 asm volatile("bts %1,%0" : BITOP_ADDR(addr) : "Ir" (nr) : "memory");
3343 static inline void _tg3_flag_set(enum TG3_FLAGS flag, unsigned long *bits)
3345 __set_bit(flag, bits);
3348 static inline void __clear_bit(int nr, volatile unsigned long *addr)
3350 asm volatile("btr %1,%0" : BITOP_ADDR(addr) : "Ir" (nr));
3353 static inline void _tg3_flag_clear(enum TG3_FLAGS flag, unsigned long *bits)
3355 __clear_bit(flag, bits);
3358 #define tg3_flag(tp, flag) \
3359 _tg3_flag(TG3_FLAG_##flag, (tp)->tg3_flags)
3360 #define tg3_flag_set(tp, flag) \
3361 _tg3_flag_set(TG3_FLAG_##flag, (tp)->tg3_flags)
3362 #define tg3_flag_clear(tp, flag) \
3363 _tg3_flag_clear(TG3_FLAG_##flag, (tp)->tg3_flags)
3365 /* tg3_main.c forward declarations */
3366 int tg3_init_rings(struct tg3 *tp);
3367 void tg3_rx_prodring_fini(struct tg3_rx_prodring_set *tpr);
3368 ///int tg3_rx_prodring_init(struct tg3 *tp, struct tg3_rx_prodring_set *tpr);
3370 /* tg3_phy.c forward declarations */
3371 u32 tg3_read_otp_phycfg(struct tg3 *tp);
3372 void tg3_mdio_init(struct tg3 *tp);
3373 int tg3_phy_probe(struct tg3 *tp);
3374 int tg3_phy_reset(struct tg3 *tp);
3375 int tg3_setup_phy(struct tg3 *tp, int force_reset);
3376 int tg3_readphy(struct tg3 *tp, int reg, u32 *val);
3377 int tg3_writephy(struct tg3 *tp, int reg, u32 val);
3379 /* tg3_hw.c forward declarations */
3380 void _tw32_flush(struct tg3 *tp, u32 off, u32 val, u32 usec_wait);
3381 void tg3_write_mem(struct tg3 *tp, u32 off, u32 val);
3382 int tg3_get_invariants(struct tg3 *tp);
3383 void tg3_init_bufmgr_config(struct tg3 *tp);
3384 int tg3_get_device_address(struct tg3 *tp);
3385 int tg3_halt(struct tg3 *tp);
3386 void tg3_set_txd(struct tg3 *tp, int entry, dma_addr_t mapping, int len, u32 flags);
3387 void tg3_set_power_state_0(struct tg3 *tp);
3388 int tg3_alloc_consistent(struct tg3 *tp);
3389 int tg3_init_hw(struct tg3 *tp, int reset_phy);
3390 void tg3_poll_link(struct tg3 *tp);
3391 void tg3_wait_for_event_ack(struct tg3 *tp);
3392 void __tg3_set_mac_addr(struct tg3 *tp, int skip_mac_1);
3393 void tg3_disable_ints(struct tg3 *tp);
3394 void tg3_enable_ints(struct tg3 *tp);
3396 static inline void tg3_generate_fw_event(struct tg3 *tp)
3400 val = tr32(GRC_RX_CPU_EVENT);
3401 val |= GRC_RX_CPU_DRIVER_EVENT;
3402 tw32_f(GRC_RX_CPU_EVENT, val);
3405 /* linux-2.6.39, include/linux/mii.h: */
3407 * mii_resolve_flowctrl_fdx
3408 * @lcladv: value of MII ADVERTISE register
3409 * @rmtadv: value of MII LPA register
3411 * Resolve full duplex flow control as per IEEE 802.3-2005 table 28B-3
3413 static inline u8 mii_resolve_flowctrl_fdx(u16 lcladv, u16 rmtadv)
3417 if (lcladv & rmtadv & ADVERTISE_PAUSE_CAP) {
3418 cap = FLOW_CTRL_TX | FLOW_CTRL_RX;
3419 } else if (lcladv & rmtadv & ADVERTISE_PAUSE_ASYM) {
3420 if (lcladv & ADVERTISE_PAUSE_CAP)
3422 else if (rmtadv & ADVERTISE_PAUSE_CAP)
3429 #define ETH_FCS_LEN 4
3431 #endif /* !(_T3_H) */