1 /**************************************************************************
3 * sundance.c -- Etherboot device driver for the Sundance ST201 "Alta".
4 * Written 2002-2002 by Timothy Legge <tlegge@rogers.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; either version 2 of the License, or
9 * (at your option) any later version.
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 * Portions of this code based on:
22 * sundance.c: A Linux device driver for the Sundance ST201 "Alta"
23 * Written 1999-2002 by Donald Becker
25 * tulip.c: Tulip and Clone Etherboot Driver
27 * Copyright (C) 2001 Entity Cyber, Inc.
29 * Linux Driver Version LK1.09a, 10-Jul-2003 (2.4.25)
33 * v1.1 01-01-2003 timlegge Initial implementation
34 * v1.7 04-10-2003 timlegge Transfers Linux Kernel (30 sec)
35 * v1.8 04-13-2003 timlegge Fix multiple transmission bug
36 * v1.9 08-19-2003 timlegge Support Multicast
37 * v1.10 01-17-2004 timlegge Initial driver output cleanup
38 * v1.11 03-21-2004 timlegge Remove unused variables
39 * v1.12 03-21-2004 timlegge Remove excess MII defines
40 * v1.13 03-24-2004 timlegge Update to Linux 2.4.25 driver
42 ****************************************************************************/
44 FILE_LICENCE ( GPL2_OR_LATER );
46 /* to get some global routines like printf */
47 #include "etherboot.h"
48 /* to get the interface to the body of the program */
50 /* to get the PCI support functions, if this is a PCI NIC */
54 #define drv_version "v1.12"
55 #define drv_date "2004-03-21"
59 /* Condensed operations for readability. */
60 #define virt_to_le32desc(addr) cpu_to_le32(virt_to_bus(addr))
61 #define le32desc_to_virt(addr) bus_to_virt(le32_to_cpu(addr))
64 static int mtu = 1514;
66 /* Maximum number of multicast addresses to filter (vs. rx-all-multicast).
67 The sundance uses a 64 element hash table based on the Ethernet CRC. */
68 // static int multicast_filter_limit = 32;
70 /* Set the copy breakpoint for the copy-only-tiny-frames scheme.
71 Setting to > 1518 effectively disables this feature.
72 This chip can receive into any byte alignment buffers, so word-oriented
73 archs do not need a copy-align of the IP header. */
74 static int rx_copybreak = 0;
75 static int flowctrl = 1;
77 /* Allow forcing the media type */
78 /* media[] specifies the media type the NIC operates at.
79 autosense Autosensing active media.
80 10mbps_hd 10Mbps half duplex.
81 10mbps_fd 10Mbps full duplex.
82 100mbps_hd 100Mbps half duplex.
83 100mbps_fd 100Mbps full duplex.
85 static char media[] = "autosense";
87 /* Operational parameters that are set at compile time. */
89 /* As Etherboot uses a Polling driver we can keep the number of rings
90 to the minimum number required. In general that is 1 transmit and 4 receive receive rings. However some cards require that
91 there be a minimum of 2 rings */
92 #define TX_RING_SIZE 2
93 #define TX_QUEUE_LEN 10 /* Limit ring entries actually used. */
94 #define RX_RING_SIZE 4
97 /* Operational parameters that usually are not changed. */
98 /* Time in jiffies before concluding the transmitter is hung. */
99 #define TX_TIME_OUT (4*HZ)
100 #define PKT_BUF_SZ 1536
102 /* Offsets to the device registers.
103 Unlike software-only systems, device drivers interact with complex hardware.
104 It's not useful to define symbolic names for every register bit in the
105 device. The name can only partially document the semantics and make
106 the driver longer and more difficult to read.
107 In general, only the important configuration values or bits changed
108 multiple times should be defined symbolically.
113 TxDMABurstThresh = 0x08,
114 TxDMAUrgentThresh = 0x09,
115 TxDMAPollPeriod = 0x0a,
120 RxDMABurstThresh = 0x14,
121 RxDMAUrgentThresh = 0x15,
122 RxDMAPollPeriod = 0x16,
127 TxStartThresh = 0x3c,
128 RxEarlyThresh = 0x3e,
143 MulticastFilter0 = 0x60,
144 MulticastFilter1 = 0x64,
151 StatsCarrierError = 0x74,
152 StatsLateColl = 0x75,
153 StatsMultiColl = 0x76,
157 StatsTxXSDefer = 0x7a,
163 /* Aliased and bogus values! */
166 enum ASICCtrl_HiWord_bit {
167 GlobalReset = 0x0001,
172 NetworkReset = 0x0020,
177 /* Bits in the interrupt status/mask registers. */
178 enum intr_status_bits {
179 IntrSummary = 0x0001, IntrPCIErr = 0x0002, IntrMACCtrl = 0x0008,
180 IntrTxDone = 0x0004, IntrRxDone = 0x0010, IntrRxStart = 0x0020,
181 IntrDrvRqst = 0x0040,
182 StatsMax = 0x0080, LinkChange = 0x0100,
183 IntrTxDMADone = 0x0200, IntrRxDMADone = 0x0400,
186 /* Bits in the RxMode register. */
188 AcceptAllIPMulti = 0x20, AcceptMultiHash = 0x10, AcceptAll = 0x08,
189 AcceptBroadcast = 0x04, AcceptMulticast = 0x02, AcceptMyPhys =
192 /* Bits in MACCtrl. */
193 enum mac_ctrl0_bits {
194 EnbFullDuplex = 0x20, EnbRcvLargeFrame = 0x40,
195 EnbFlowCtrl = 0x100, EnbPassRxCRC = 0x200,
197 enum mac_ctrl1_bits {
198 StatsEnable = 0x0020, StatsDisable = 0x0040, StatsEnabled = 0x0080,
199 TxEnable = 0x0100, TxDisable = 0x0200, TxEnabled = 0x0400,
200 RxEnable = 0x0800, RxDisable = 0x1000, RxEnabled = 0x2000,
203 /* The Rx and Tx buffer descriptors.
204 Using only 32 bit fields simplifies software endian correction.
205 This structure must be aligned, and should avoid spanning cache lines.
214 /* Bits in netdev_desc.status */
215 enum desc_status_bits {
217 DescEndPacket = 0x4000,
218 DescEndRing = 0x2000,
219 LastFrag = 0x80000000,
220 DescIntrOnTx = 0x8000,
221 DescIntrOnDMADone = 0x80000000,
222 DisableAlign = 0x00000001,
225 /**********************************************
226 * Descriptor Ring and Buffer defination
227 ***********************************************/
228 /* Define the TX Descriptor */
229 static struct netdev_desc tx_ring[TX_RING_SIZE];
231 /* Define the RX Descriptor */
232 static struct netdev_desc rx_ring[RX_RING_SIZE];
234 /* Create a static buffer of size PKT_BUF_SZ for each RX and TX descriptor.
235 All descriptors point to a part of this buffer */
237 unsigned char txb[PKT_BUF_SZ * TX_RING_SIZE];
238 unsigned char rxb[RX_RING_SIZE * PKT_BUF_SZ];
239 } rx_tx_buf __shared;
240 #define rxb rx_tx_buf.rxb
241 #define txb rx_tx_buf.txb
243 /* FIXME: Move BASE to the private structure */
245 #define EEPROM_SIZE 128
247 enum pci_id_flags_bits {
248 PCI_USES_IO = 1, PCI_USES_MEM = 2, PCI_USES_MASTER = 4,
249 PCI_ADDR0 = 0 << 4, PCI_ADDR1 = 1 << 4, PCI_ADDR2 =
250 2 << 4, PCI_ADDR3 = 3 << 4,
253 enum chip_capability_flags { CanHaveMII = 1, KendinPktDropBug = 2, };
254 #define PCI_IOTYPE (PCI_USES_MASTER | PCI_USES_IO | PCI_ADDR0)
257 static struct sundance_private {
258 const char *nic_name;
259 /* Frequently used values */
261 unsigned int cur_rx; /* Producer/consumer ring indices */
264 /* These values keep track of the tranceiver/media in use */
265 unsigned int flowctrl:1;
266 unsigned int an_enable:1;
270 /* MII tranceiver section */
271 struct mii_if_info mii_if;
272 int mii_preamble_required;
273 unsigned char phys[MII_CNT];
274 unsigned char pci_rev_id;
277 static struct sundance_private *sdc;
279 /* Station Address location within the EEPROM */
280 #define EEPROM_SA_OFFSET 0x10
281 #define DEFAULT_INTR (IntrRxDMADone | IntrPCIErr | \
282 IntrDrvRqst | IntrTxDone | StatsMax | \
285 static int eeprom_read(long ioaddr, int location);
286 static int mdio_read(struct nic *nic, int phy_id, unsigned int location);
287 static void mdio_write(struct nic *nic, int phy_id, unsigned int location,
289 static void set_rx_mode(struct nic *nic);
291 static void check_duplex(struct nic *nic)
293 int mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA);
294 int negotiated = mii_lpa & sdc->mii_if.advertising;
298 if (!sdc->an_enable || mii_lpa == 0xffff) {
299 if (sdc->mii_if.full_duplex)
300 outw(inw(BASE + MACCtrl0) | EnbFullDuplex,
305 /* Autonegotiation */
306 duplex = (negotiated & 0x0100) || (negotiated & 0x01C0) == 0x0040;
307 if (sdc->mii_if.full_duplex != duplex) {
308 sdc->mii_if.full_duplex = duplex;
309 DBG ("%s: Setting %s-duplex based on MII #%d "
310 "negotiated capability %4.4x.\n", sdc->nic_name,
311 duplex ? "full" : "half", sdc->phys[0],
313 outw(inw(BASE + MACCtrl0) | duplex ? 0x20 : 0,
319 /**************************************************************************
320 * init_ring - setup the tx and rx descriptors
321 *************************************************************************/
322 static void init_ring(struct nic *nic __unused)
328 /* Initialize all the Rx descriptors */
329 for (i = 0; i < RX_RING_SIZE; i++) {
330 rx_ring[i].next_desc = virt_to_le32desc(&rx_ring[i + 1]);
331 rx_ring[i].status = 0;
332 rx_ring[i].length = 0;
336 /* Mark the last entry as wrapping the ring */
337 rx_ring[i - 1].next_desc = virt_to_le32desc(&rx_ring[0]);
339 for (i = 0; i < RX_RING_SIZE; i++) {
340 rx_ring[i].addr = virt_to_le32desc(&rxb[i * PKT_BUF_SZ]);
341 rx_ring[i].length = cpu_to_le32(PKT_BUF_SZ | LastFrag);
344 /* We only use one transmit buffer, but two
345 * descriptors so transmit engines have somewhere
346 * to point should they feel the need */
347 tx_ring[0].status = 0x00000000;
348 tx_ring[0].addr = virt_to_bus(&txb[0]);
349 tx_ring[0].next_desc = 0; /* virt_to_bus(&tx_ring[1]); */
351 /* This descriptor is never used */
352 tx_ring[1].status = 0x00000000;
353 tx_ring[1].addr = 0; /*virt_to_bus(&txb[0]); */
354 tx_ring[1].next_desc = 0;
356 /* Mark the last entry as wrapping the ring,
357 * though this should never happen */
358 tx_ring[1].length = cpu_to_le32(LastFrag | PKT_BUF_SZ);
361 /**************************************************************************
362 * RESET - Reset Adapter
363 * ***********************************************************************/
364 static void sundance_reset(struct nic *nic)
370 outl(virt_to_le32desc(&rx_ring[0]), BASE + RxListPtr);
371 /* The Tx List Pointer is written as packets are queued */
373 /* Initialize other registers. */
374 /* __set_mac_addr(dev); */
378 addr16 = (nic->node_addr[0] | (nic->node_addr[1] << 8));
379 outw(addr16, BASE + StationAddr);
380 addr16 = (nic->node_addr[2] | (nic->node_addr[3] << 8));
381 outw(addr16, BASE + StationAddr + 2);
382 addr16 = (nic->node_addr[4] | (nic->node_addr[5] << 8));
383 outw(addr16, BASE + StationAddr + 4);
386 outw(sdc->mtu + 14, BASE + MaxFrameSize);
387 if (sdc->mtu > 2047) /* this will never happen with default options */
388 outl(inl(BASE + ASICCtrl) | 0x0c, BASE + ASICCtrl);
392 outw(0, BASE + DownCounter);
393 /* Set the chip to poll every N*30nsec */
394 outb(100, BASE + RxDMAPollPeriod);
396 /* Fix DFE-580TX packet drop issue */
397 if (sdc->pci_rev_id >= 0x14)
398 writeb(0x01, BASE + DebugCtrl1);
400 outw(RxEnable | TxEnable, BASE + MACCtrl1);
402 /* Construct a perfect filter frame with the mac address as first match
403 * and broadcast for all others */
404 for (i = 0; i < 192; i++)
407 txb[0] = nic->node_addr[0];
408 txb[1] = nic->node_addr[1];
409 txb[2] = nic->node_addr[2];
410 txb[3] = nic->node_addr[3];
411 txb[4] = nic->node_addr[4];
412 txb[5] = nic->node_addr[5];
414 DBG ( "%s: Done sundance_reset, status: Rx %hX Tx %hX "
415 "MAC Control %hX, %hX %hX\n",
416 sdc->nic_name, (int) inl(BASE + RxStatus),
417 (int) inw(BASE + TxStatus), (int) inl(BASE + MACCtrl0),
418 (int) inw(BASE + MACCtrl1), (int) inw(BASE + MACCtrl0) );
421 /**************************************************************************
422 IRQ - Wait for a frame
423 ***************************************************************************/
424 static void sundance_irq ( struct nic *nic, irq_action_t action ) {
425 unsigned int intr_status;
430 intr_status = inw(nic->ioaddr + IntrStatus);
431 intr_status = intr_status & ~DEFAULT_INTR;
432 if ( action == ENABLE )
433 intr_status = intr_status | DEFAULT_INTR;
434 outw(intr_status, nic->ioaddr + IntrEnable);
437 outw(0x0200, BASE + ASICCtrl);
441 /**************************************************************************
442 POLL - Wait for a frame
443 ***************************************************************************/
444 static int sundance_poll(struct nic *nic, int retrieve)
446 /* return true if there's an ethernet packet ready to read */
447 /* nic->packet should contain data on return */
448 /* nic->packetlen should contain length of data */
449 int entry = sdc->cur_rx % RX_RING_SIZE;
450 u32 frame_status = le32_to_cpu(rx_ring[entry].status);
454 if (!(frame_status & DescOwn))
457 /* There is a packet ready */
461 intr_status = inw(nic->ioaddr + IntrStatus);
462 outw(intr_status, nic->ioaddr + IntrStatus);
464 pkt_len = frame_status & 0x1fff;
466 if (frame_status & 0x001f4000) {
467 DBG ( "Polling frame_status error\n" ); /* Do we really care about this */
469 if (pkt_len < rx_copybreak) {
470 /* FIXME: What should happen Will this ever occur */
471 printf("Poll Error: pkt_len < rx_copybreak");
473 nic->packetlen = pkt_len;
474 memcpy(nic->packet, rxb +
475 (sdc->cur_rx * PKT_BUF_SZ), nic->packetlen);
479 rx_ring[entry].length = cpu_to_le32(PKT_BUF_SZ | LastFrag);
480 rx_ring[entry].status = 0;
482 sdc->cur_rx = entry % RX_RING_SIZE;
483 outw(DEFAULT_INTR & ~(IntrRxDone|IntrRxDMADone),
484 nic->ioaddr + IntrStatus);
488 /**************************************************************************
489 TRANSMIT - Transmit a frame
490 ***************************************************************************/
491 static void sundance_transmit(struct nic *nic, const char *d, /* Destination */
492 unsigned int t, /* Type */
493 unsigned int s, /* size */
500 outw(TxDisable, BASE + MACCtrl1);
502 memcpy(txb, d, ETH_ALEN);
503 memcpy(txb + ETH_ALEN, nic->node_addr, ETH_ALEN);
504 nstype = htons((u16) t);
505 memcpy(txb + 2 * ETH_ALEN, (u8 *) & nstype, 2);
506 memcpy(txb + ETH_HLEN, p, s);
513 /* Setup the transmit descriptor */
514 tx_ring[0].length = cpu_to_le32(s | LastFrag);
515 tx_ring[0].status = cpu_to_le32(0x00000001);
517 /* Point to transmit descriptor */
518 outl(virt_to_le32desc(&tx_ring[0]), BASE + TxListPtr);
521 outw(TxEnable, BASE + MACCtrl1);
522 /* Trigger an immediate send */
523 outw(0, BASE + TxStatus);
525 to = currticks() + TX_TIME_OUT;
526 while (!(tx_ring[0].status & 0x00010000) && (currticks() < to)); /* wait */
528 if (currticks() >= to) {
529 printf("TX Time Out");
532 outw(TxDisable, BASE + MACCtrl1);
536 /**************************************************************************
537 DISABLE - Turn off ethernet interface
538 ***************************************************************************/
539 static void sundance_disable ( struct nic *nic __unused ) {
540 /* put the card in its initial state */
541 /* This function serves 3 purposes.
542 * This disables DMA and interrupts so we don't receive
543 * unexpected packets or interrupts from the card after
544 * etherboot has finished.
545 * This frees resources so etherboot may use
546 * this driver on another interface
547 * This allows etherboot to reinitialize the interface
548 * if something is something goes wrong.
550 outw(0x0000, BASE + IntrEnable);
551 /* Stop the Chipchips Tx and Rx Status */
552 outw(TxDisable | RxDisable | StatsDisable, BASE + MACCtrl1);
555 static struct nic_operations sundance_operations = {
556 .connect = dummy_connect,
557 .poll = sundance_poll,
558 .transmit = sundance_transmit,
563 /**************************************************************************
564 PROBE - Look for an adapter, this routine's visible to the outside
565 ***************************************************************************/
566 static int sundance_probe ( struct nic *nic, struct pci_device *pci ) {
568 u8 ee_data[EEPROM_SIZE];
573 if (pci->ioaddr == 0)
576 /* BASE is used throughout to address the card */
578 printf(" sundance.c: Found %s Vendor=0x%hX Device=0x%hX\n",
579 pci->id->name, pci->vendor, pci->device);
581 /* Get the MAC Address by reading the EEPROM */
582 for (i = 0; i < 3; i++) {
583 ((u16 *) ee_data)[i] =
584 le16_to_cpu(eeprom_read(BASE, i + EEPROM_SA_OFFSET));
586 /* Update the nic structure with the MAC Address */
587 for (i = 0; i < ETH_ALEN; i++) {
588 nic->node_addr[i] = ee_data[i];
591 /* Set the card as PCI Bus Master */
592 adjust_pci_device(pci);
594 // sdc->mii_if.dev = pci;
595 // sdc->mii_if.phy_id_mask = 0x1f;
596 // sdc->mii_if.reg_num_mask = 0x1f;
598 /* point to private storage */
601 sdc->nic_name = pci->id->name;
604 pci_read_config_byte(pci, PCI_REVISION_ID, &sdc->pci_rev_id);
606 DBG ( "Device revision id: %hx\n", sdc->pci_rev_id );
608 /* Print out some hardware info */
609 DBG ( "%s: %s at ioaddr %hX, ",
610 pci->id->name, nic->node_addr, (unsigned int) BASE);
612 sdc->mii_preamble_required = 0;
614 int phy, phy_idx = 0;
615 sdc->phys[0] = 1; /* Default Setting */
616 sdc->mii_preamble_required++;
617 for (phy = 1; phy < 32 && phy_idx < MII_CNT; phy++) {
618 int mii_status = mdio_read(nic, phy, MII_BMSR);
619 if (mii_status != 0xffff && mii_status != 0x0000) {
620 sdc->phys[phy_idx++] = phy;
621 sdc->mii_if.advertising =
622 mdio_read(nic, phy, MII_ADVERTISE);
623 if ((mii_status & 0x0040) == 0)
624 sdc->mii_preamble_required++;
626 ( "%s: MII PHY found at address %d, status " "%hX advertising %hX\n", sdc->nic_name, phy, mii_status, sdc->mii_if.advertising );
629 sdc->mii_preamble_required--;
631 printf("%s: No MII transceiver found!\n",
633 sdc->mii_if.phy_id = sdc->phys[0];
636 /* Parse override configuration */
638 if (strcasecmp(media, "autosense") != 0) {
640 if (strcasecmp(media, "100mbps_fd") == 0 ||
641 strcasecmp(media, "4") == 0) {
643 sdc->mii_if.full_duplex = 1;
644 } else if (strcasecmp(media, "100mbps_hd") == 0
645 || strcasecmp(media, "3") == 0) {
647 sdc->mii_if.full_duplex = 0;
648 } else if (strcasecmp(media, "10mbps_fd") == 0 ||
649 strcasecmp(media, "2") == 0) {
651 sdc->mii_if.full_duplex = 1;
652 } else if (strcasecmp(media, "10mbps_hd") == 0 ||
653 strcasecmp(media, "1") == 0) {
655 sdc->mii_if.full_duplex = 0;
664 if (inl(BASE + ASICCtrl) & 0x80) {
665 /* Default 100Mbps Full */
666 if (sdc->an_enable) {
668 sdc->mii_if.full_duplex = 1;
673 /* The Linux driver uses flow control and resets the link here. This means the
674 mii section from above would need to be re done I believe. Since it serves
675 no real purpose leave it out. */
677 /* Force media type */
678 if (!sdc->an_enable) {
680 mii_ctl |= (sdc->speed == 100) ? BMCR_SPEED100 : 0;
681 mii_ctl |= (sdc->mii_if.full_duplex) ? BMCR_FULLDPLX : 0;
682 mdio_write(nic, sdc->phys[0], MII_BMCR, mii_ctl);
683 printf("Override speed=%d, %s duplex\n",
685 sdc->mii_if.full_duplex ? "Full" : "Half");
688 /* Reset the chip to erase previous misconfiguration */
689 DBG ( "ASIC Control is %#x\n", inl(BASE + ASICCtrl) );
690 outw(0x007f, BASE + ASICCtrl + 2);
693 * wait for reset to complete
694 * this is heavily inspired by the linux sundance driver
695 * according to the linux driver it can take up to 1ms for the reset
699 while(inl(BASE + ASICCtrl) & (ResetBusy << 16)) {
701 DBG("sundance: NIC reset did not complete.\n");
707 DBG ( "ASIC Control is now %#x.\n", inl(BASE + ASICCtrl) );
710 if (sdc->an_enable) {
711 u16 mii_advertise, mii_lpa;
713 mdio_read(nic, sdc->phys[0], MII_ADVERTISE);
714 mii_lpa = mdio_read(nic, sdc->phys[0], MII_LPA);
715 mii_advertise &= mii_lpa;
716 if (mii_advertise & ADVERTISE_100FULL)
718 else if (mii_advertise & ADVERTISE_100HALF)
720 else if (mii_advertise & ADVERTISE_10FULL)
722 else if (mii_advertise & ADVERTISE_10HALF)
725 mii_ctl = mdio_read(nic, sdc->phys[0], MII_BMCR);
726 speed = (mii_ctl & BMCR_SPEED100) ? 100 : 10;
728 printf("%s: Link changed: %dMbps ,", sdc->nic_name, speed);
729 printf("%s duplex.\n", (mii_ctl & BMCR_FULLDPLX) ?
733 if (sdc->flowctrl && sdc->mii_if.full_duplex) {
734 outw(inw(BASE + MulticastFilter1 + 2) | 0x0200,
735 BASE + MulticastFilter1 + 2);
736 outw(inw(BASE + MACCtrl0) | EnbFlowCtrl, BASE + MACCtrl0);
738 printf("%dMbps, %s-Duplex\n", sdc->speed,
739 sdc->mii_if.full_duplex ? "Full" : "Half");
741 /* point to NIC specific routines */
742 nic->nic_op = &sundance_operations;
744 nic->irqno = pci->irq;
751 /* Read the EEPROM and MII Management Data I/O (MDIO) interfaces. */
752 static int eeprom_read(long ioaddr, int location)
754 int boguscnt = 10000; /* Typical 1900 ticks */
755 outw(0x0200 | (location & 0xff), ioaddr + EECtrl);
757 if (!(inw(ioaddr + EECtrl) & 0x8000)) {
758 return inw(ioaddr + EEData);
761 while (--boguscnt > 0);
765 /* MII transceiver control section.
766 Read and write the MII registers using software-generated serial
767 MDIO protocol. See the MII specifications or DP83840A data sheet
770 The maximum data clock rate is 2.5 Mhz.
771 The timing is decoupled from the processor clock by flushing the write
772 from the CPU write buffer with a following read, and using PCI
775 #define mdio_in(mdio_addr) inb(mdio_addr)
776 #define mdio_out(value, mdio_addr) outb(value, mdio_addr)
777 #define mdio_delay(mdio_addr) inb(mdio_addr)
780 MDIO_ShiftClk = 0x0001, MDIO_Data = 0x0002, MDIO_EnbOutput =
783 #define MDIO_EnbIn (0)
784 #define MDIO_WRITE0 (MDIO_EnbOutput)
785 #define MDIO_WRITE1 (MDIO_Data | MDIO_EnbOutput)
787 /* Generate the preamble required for initial synchronization and
788 a few older transceivers. */
789 static void mdio_sync(long mdio_addr)
793 /* Establish sync by sending at least 32 logic ones. */
794 while (--bits >= 0) {
795 mdio_out(MDIO_WRITE1, mdio_addr);
796 mdio_delay(mdio_addr);
797 mdio_out(MDIO_WRITE1 | MDIO_ShiftClk, mdio_addr);
798 mdio_delay(mdio_addr);
803 mdio_read(struct nic *nic __unused, int phy_id, unsigned int location)
805 long mdio_addr = BASE + MIICtrl;
806 int mii_cmd = (0xf6 << 10) | (phy_id << 5) | location;
809 if (sdc->mii_preamble_required)
810 mdio_sync(mdio_addr);
812 /* Shift the read command bits out. */
813 for (i = 15; i >= 0; i--) {
815 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
817 mdio_out(dataval, mdio_addr);
818 mdio_delay(mdio_addr);
819 mdio_out(dataval | MDIO_ShiftClk, mdio_addr);
820 mdio_delay(mdio_addr);
822 /* Read the two transition, 16 data, and wire-idle bits. */
823 for (i = 19; i > 0; i--) {
824 mdio_out(MDIO_EnbIn, mdio_addr);
825 mdio_delay(mdio_addr);
826 retval = (retval << 1) | ((mdio_in(mdio_addr) & MDIO_Data)
828 mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
829 mdio_delay(mdio_addr);
831 return (retval >> 1) & 0xffff;
835 mdio_write(struct nic *nic __unused, int phy_id,
836 unsigned int location, int value)
838 long mdio_addr = BASE + MIICtrl;
840 (0x5002 << 16) | (phy_id << 23) | (location << 18) | value;
843 if (sdc->mii_preamble_required)
844 mdio_sync(mdio_addr);
846 /* Shift the command bits out. */
847 for (i = 31; i >= 0; i--) {
849 (mii_cmd & (1 << i)) ? MDIO_WRITE1 : MDIO_WRITE0;
850 mdio_out(dataval, mdio_addr);
851 mdio_delay(mdio_addr);
852 mdio_out(dataval | MDIO_ShiftClk, mdio_addr);
853 mdio_delay(mdio_addr);
855 /* Clear out extra bits. */
856 for (i = 2; i > 0; i--) {
857 mdio_out(MDIO_EnbIn, mdio_addr);
858 mdio_delay(mdio_addr);
859 mdio_out(MDIO_EnbIn | MDIO_ShiftClk, mdio_addr);
860 mdio_delay(mdio_addr);
865 static void set_rx_mode(struct nic *nic __unused)
868 u16 mc_filter[4]; /* Multicast hash filter */
871 memset(mc_filter, 0xff, sizeof(mc_filter));
872 rx_mode = AcceptBroadcast | AcceptMulticast | AcceptMyPhys;
874 if (sdc->mii_if.full_duplex && sdc->flowctrl)
875 mc_filter[3] |= 0x0200;
876 for (i = 0; i < 4; i++)
877 outw(mc_filter[i], BASE + MulticastFilter0 + i * 2);
878 outb(rx_mode, BASE + RxMode);
882 static struct pci_device_id sundance_nics[] = {
883 PCI_ROM(0x13f0, 0x0201, "sundance", "ST201 Sundance 'Alta' based Adaptor", 0),
884 PCI_ROM(0x1186, 0x1002, "dfe530txs", "D-Link DFE530TXS (Sundance ST201 Alta)", 0),
885 PCI_ROM(0x13f0, 0x0200, "ip100a", "IC+ IP100A", 0),
888 PCI_DRIVER ( sundance_driver, sundance_nics, PCI_NO_CLASS );
890 DRIVER ( "SUNDANCE/PCI", nic_driver, pci_driver, sundance_driver,
891 sundance_probe, sundance_disable );