2 #error multicast support is not yet implemented
4 /*------------------------------------------------------------------------
6 * This is a Etherboot driver for SMC's 9000 series of Ethernet cards.
8 * Copyright (C) 1998 Daniel Engström <daniel.engstrom@riksnett.no>
9 * Based on the Linux SMC9000 driver, smc9194.c by Eric Stahlman
10 * Copyright (C) 1996 by Erik Stahlman <eric@vt.edu>
12 * This software may be used and distributed according to the terms
13 * of the GNU Public License, incorporated herein by reference.
15 * "Features" of the SMC chip:
16 * 4608 byte packet memory. ( for the 91C92/4. Others have more )
17 * EEPROM for configuration
21 * Erik Stahlman <erik@vt.edu>
22 * Daniel Engström <daniel.engstrom@riksnett.no>
25 * 98-09-25 Daniel Engström Etherboot driver crated from Eric's
28 *---------------------------------------------------------------------------*/
30 FILE_LICENCE ( GPL_ANY );
32 #define LINUX_OUT_MACROS 1
33 #define SMC9000_DEBUG 0
36 #define PRINTK2 printf
38 #define PRINTK2(args...)
41 #include <ipxe/ethernet.h>
43 #include "etherboot.h"
51 static const char smc9000_version[] = "Version 0.99 98-09-30";
52 static const char *interfaces[ 2 ] = { "TP", "AUI" };
53 static const char *chip_ids[ 15 ] = {
55 /* 3 */ "SMC91C90/91C92",
60 /* 8 */ "SMC91C100FD",
61 /* 9 */ "SMC91C11xFD",
65 static const char smc91c96_id[] = "SMC91C96";
67 /*------------------------------------------------------------
68 . Reads a register from the MII Management serial interface
69 .-------------------------------------------------------------*/
70 static word smc_read_phy_register(int ioaddr, byte phyaddr, byte phyreg)
81 // 32 consecutive ones on MDO to establish sync
82 for (i = 0; i < 32; ++i)
83 bits[clk_idx++] = MII_MDOE | MII_MDO;
86 bits[clk_idx++] = MII_MDOE;
87 bits[clk_idx++] = MII_MDOE | MII_MDO;
90 bits[clk_idx++] = MII_MDOE | MII_MDO;
91 bits[clk_idx++] = MII_MDOE;
93 // Output the PHY address, msb first
95 for (i = 0; i < 5; ++i)
98 bits[clk_idx++] = MII_MDOE | MII_MDO;
100 bits[clk_idx++] = MII_MDOE;
102 // Shift to next lowest bit
106 // Output the phy register number, msb first
108 for (i = 0; i < 5; ++i)
111 bits[clk_idx++] = MII_MDOE | MII_MDO;
113 bits[clk_idx++] = MII_MDOE;
115 // Shift to next lowest bit
119 // Tristate and turnaround (2 bit times)
121 //bits[clk_idx++] = 0;
123 // Input starts at this bit time
126 // Will input 16 bits
127 for (i = 0; i < 16; ++i)
133 // Save the current bank
134 oldBank = inw( ioaddr+BANK_SELECT );
137 SMC_SELECT_BANK(ioaddr, 3);
139 // Get the current MII register value
140 mii_reg = inw( ioaddr+MII_REG );
142 // Turn off all MII Interface bits
143 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
145 // Clock all 64 cycles
146 for (i = 0; i < sizeof(bits); ++i)
148 // Clock Low - output data
149 outw( mii_reg | bits[i], ioaddr+MII_REG );
153 // Clock Hi - input data
154 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
156 bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
159 // Return to idle state
160 // Set clock to low, data to low, and output tristated
161 outw( mii_reg, ioaddr+MII_REG );
164 // Restore original bank select
165 SMC_SELECT_BANK(ioaddr, oldBank);
167 // Recover input data
169 for (i = 0; i < 16; ++i)
173 if (bits[input_idx++] & MII_MDI)
178 printf("smc_read_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
179 phyaddr, phyreg, phydata);
186 /*------------------------------------------------------------
187 . Writes a register to the MII Management serial interface
188 .-------------------------------------------------------------*/
189 static void smc_write_phy_register(int ioaddr,
190 byte phyaddr, byte phyreg, word phydata)
199 // 32 consecutive ones on MDO to establish sync
200 for (i = 0; i < 32; ++i)
201 bits[clk_idx++] = MII_MDOE | MII_MDO;
204 bits[clk_idx++] = MII_MDOE;
205 bits[clk_idx++] = MII_MDOE | MII_MDO;
207 // Write command <01>
208 bits[clk_idx++] = MII_MDOE;
209 bits[clk_idx++] = MII_MDOE | MII_MDO;
211 // Output the PHY address, msb first
213 for (i = 0; i < 5; ++i)
216 bits[clk_idx++] = MII_MDOE | MII_MDO;
218 bits[clk_idx++] = MII_MDOE;
220 // Shift to next lowest bit
224 // Output the phy register number, msb first
226 for (i = 0; i < 5; ++i)
229 bits[clk_idx++] = MII_MDOE | MII_MDO;
231 bits[clk_idx++] = MII_MDOE;
233 // Shift to next lowest bit
237 // Tristate and turnaround (2 bit times)
241 // Write out 16 bits of data, msb first
243 for (i = 0; i < 16; ++i)
246 bits[clk_idx++] = MII_MDOE | MII_MDO;
248 bits[clk_idx++] = MII_MDOE;
250 // Shift to next lowest bit
254 // Final clock bit (tristate)
257 // Save the current bank
258 oldBank = inw( ioaddr+BANK_SELECT );
261 SMC_SELECT_BANK(ioaddr, 3);
263 // Get the current MII register value
264 mii_reg = inw( ioaddr+MII_REG );
266 // Turn off all MII Interface bits
267 mii_reg &= ~(MII_MDOE|MII_MCLK|MII_MDI|MII_MDO);
270 for (i = 0; i < sizeof(bits); ++i)
272 // Clock Low - output data
273 outw( mii_reg | bits[i], ioaddr+MII_REG );
277 // Clock Hi - input data
278 outw( mii_reg | bits[i] | MII_MCLK, ioaddr+MII_REG );
280 bits[i] |= inw( ioaddr+MII_REG ) & MII_MDI;
283 // Return to idle state
284 // Set clock to low, data to low, and output tristated
285 outw( mii_reg, ioaddr+MII_REG );
288 // Restore original bank select
289 SMC_SELECT_BANK(ioaddr, oldBank);
292 printf("smc_write_phy_register(): phyaddr=%x,phyreg=%x,phydata=%x\n",
293 phyaddr, phyreg, phydata);
298 /*------------------------------------------------------------
299 . Finds and reports the PHY address
300 .-------------------------------------------------------------*/
301 static int smc_detect_phy(int ioaddr, byte *pphyaddr)
308 // Scan all 32 PHY addresses if necessary
309 for (phyaddr = 0; phyaddr < 32; ++phyaddr)
311 // Read the PHY identifiers
312 phy_id1 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID1_REG);
313 phy_id2 = smc_read_phy_register(ioaddr, phyaddr, PHY_ID2_REG);
315 // Make sure it is a valid identifier
316 if ((phy_id2 > 0x0000) && (phy_id2 < 0xffff) &&
317 (phy_id1 > 0x0000) && (phy_id1 < 0xffff))
319 if ((phy_id1 != 0x8000) && (phy_id2 != 0x8000))
321 // Save the PHY's address
331 printf("No PHY found\n");
336 if ( (phy_id1 == 0x0016) && ((phy_id2 & 0xFFF0) == 0xF840 ) )
338 printf("PHY=LAN83C183 (LAN91C111 Internal)\n");
341 if ( (phy_id1 == 0x0282) && ((phy_id2 & 0xFFF0) == 0x1C50) )
343 printf("PHY=LAN83C180\n");
349 /*------------------------------------------------------------
350 . Configures the specified PHY using Autonegotiation. Calls
351 . smc_phy_fixed() if the user has requested a certain config.
352 .-------------------------------------------------------------*/
353 static void smc_phy_configure(int ioaddr)
357 word my_phy_caps; // My PHY capabilities
358 word my_ad_caps; // My Advertised capabilities
360 int rpc_cur_mode = RPC_DEFAULT;
363 // Find the address and type of our phy
364 if (!smc_detect_phy(ioaddr, &phyaddr))
369 // Reset the PHY, setting all other bits to zero
370 smc_write_phy_register(ioaddr, phyaddr, PHY_CNTL_REG, PHY_CNTL_RST);
372 // Wait for the reset to complete, or time out
373 timeout = 6; // Wait up to 3 seconds
376 if (!(smc_read_phy_register(ioaddr, phyaddr, PHY_CNTL_REG)
383 mdelay(500); // wait 500 millisecs
388 PRINTK2("PHY reset timed out\n");
392 // Read PHY Register 18, Status Output
393 lastPhy18 = smc_read_phy_register(ioaddr, phyaddr, PHY_INT_REG);
395 // Enable PHY Interrupts (for register 18)
396 // Interrupts listed here are disabled
397 smc_write_phy_register(ioaddr, phyaddr, PHY_MASK_REG,
398 PHY_INT_LOSSSYNC | PHY_INT_CWRD | PHY_INT_SSD |
399 PHY_INT_ESD | PHY_INT_RPOL | PHY_INT_JAB |
400 PHY_INT_SPDDET | PHY_INT_DPLXDET);
402 /* Configure the Receive/Phy Control register */
403 SMC_SELECT_BANK(ioaddr, 0);
404 outw( rpc_cur_mode, ioaddr + RPC_REG );
406 // Copy our capabilities from PHY_STAT_REG to PHY_AD_REG
407 my_phy_caps = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
408 my_ad_caps = PHY_AD_CSMA; // I am CSMA capable
410 if (my_phy_caps & PHY_STAT_CAP_T4)
411 my_ad_caps |= PHY_AD_T4;
413 if (my_phy_caps & PHY_STAT_CAP_TXF)
414 my_ad_caps |= PHY_AD_TX_FDX;
416 if (my_phy_caps & PHY_STAT_CAP_TXH)
417 my_ad_caps |= PHY_AD_TX_HDX;
419 if (my_phy_caps & PHY_STAT_CAP_TF)
420 my_ad_caps |= PHY_AD_10_FDX;
422 if (my_phy_caps & PHY_STAT_CAP_TH)
423 my_ad_caps |= PHY_AD_10_HDX;
425 // Update our Auto-Neg Advertisement Register
426 smc_write_phy_register(ioaddr, phyaddr, PHY_AD_REG, my_ad_caps);
428 PRINTK2("phy caps=%x\n", my_phy_caps);
429 PRINTK2("phy advertised caps=%x\n", my_ad_caps);
431 // Restart auto-negotiation process in order to advertise my caps
432 smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
433 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST );
435 // Wait for the auto-negotiation to complete. This may take from
437 // Wait for the reset to complete, or time out
438 timeout = 20; // Wait up to 10 seconds
441 status = smc_read_phy_register(ioaddr, phyaddr, PHY_STAT_REG);
442 if (status & PHY_STAT_ANEG_ACK)
444 // auto-negotiate complete
448 mdelay(500); // wait 500 millisecs
450 // Restart auto-negotiation if remote fault
451 if (status & PHY_STAT_REM_FLT)
453 PRINTK2("PHY remote fault detected\n");
455 // Restart auto-negotiation
456 PRINTK2("PHY restarting auto-negotiation\n");
457 smc_write_phy_register( ioaddr, phyaddr, PHY_CNTL_REG,
458 PHY_CNTL_ANEG_EN | PHY_CNTL_ANEG_RST |
459 PHY_CNTL_SPEED | PHY_CNTL_DPLX);
465 PRINTK2("PHY auto-negotiate timed out\n");
468 // Fail if we detected an auto-negotiate remote fault
469 if (status & PHY_STAT_REM_FLT)
471 PRINTK2("PHY remote fault detected\n");
474 // Set our sysctl parameters to match auto-negotiation results
475 if ( lastPhy18 & PHY_INT_SPDDET )
477 PRINTK2("PHY 100BaseT\n");
478 rpc_cur_mode |= RPC_SPEED;
482 PRINTK2("PHY 10BaseT\n");
483 rpc_cur_mode &= ~RPC_SPEED;
486 if ( lastPhy18 & PHY_INT_DPLXDET )
488 PRINTK2("PHY Full Duplex\n");
489 rpc_cur_mode |= RPC_DPLX;
493 PRINTK2("PHY Half Duplex\n");
494 rpc_cur_mode &= ~RPC_DPLX;
497 // Re-Configure the Receive/Phy Control register
498 outw( rpc_cur_mode, ioaddr + RPC_REG );
502 * Function: smc_reset( int ioaddr )
504 * This sets the SMC91xx chip to its normal state, hopefully from whatever
505 * mess that any other DOS driver has put it in.
507 * Maybe I should reset more registers to defaults in here? SOFTRESET should
511 * 1. send a SOFT RESET
512 * 2. wait for it to finish
513 * 3. reset the memory management unit
514 * 4. clear all interrupts
517 static void smc_reset(int ioaddr)
519 /* This resets the registers mostly to defaults, but doesn't
520 * affect EEPROM. That seems unnecessary */
521 SMC_SELECT_BANK(ioaddr, 0);
522 _outw( RCR_SOFTRESET, ioaddr + RCR );
524 /* this should pause enough for the chip to be happy */
527 /* Set the transmit and receive configuration registers to
529 _outw(RCR_CLEAR, ioaddr + RCR);
530 _outw(TCR_CLEAR, ioaddr + TCR);
533 SMC_SELECT_BANK(ioaddr, 2);
534 _outw( MC_RESET, ioaddr + MMU_CMD );
536 /* Note: It doesn't seem that waiting for the MMU busy is needed here,
537 * but this is a place where future chipsets _COULD_ break. Be wary
538 * of issuing another MMU command right after this */
539 _outb(0, ioaddr + INT_MASK);
543 /*----------------------------------------------------------------------
544 * Function: smc9000_probe_addr( int ioaddr )
547 * Tests to see if a given ioaddr points to an SMC9xxx chip.
548 * Returns a 1 on success
551 * (1) see if the high byte of BANK_SELECT is 0x33
552 * (2) compare the ioaddr with the base register's address
553 * (3) see if I recognize the chip ID in the appropriate register
555 * ---------------------------------------------------------------------
557 static int smc9000_probe_addr( isa_probe_addr_t ioaddr )
560 word revision_register;
561 word base_address_register;
563 /* First, see if the high byte is 0x33 */
564 bank = inw(ioaddr + BANK_SELECT);
565 if ((bank & 0xFF00) != 0x3300) {
568 /* The above MIGHT indicate a device, but I need to write to further
570 _outw(0x0, ioaddr + BANK_SELECT);
571 bank = inw(ioaddr + BANK_SELECT);
572 if ((bank & 0xFF00) != 0x3300) {
576 /* well, we've already written once, so hopefully another time won't
577 * hurt. This time, I need to switch the bank register to bank 1,
578 * so I can access the base address register */
579 SMC_SELECT_BANK(ioaddr, 1);
580 base_address_register = inw(ioaddr + BASE);
582 if (ioaddr != (base_address_register >> 3 & 0x3E0)) {
583 DBG("SMC9000: IOADDR %hX doesn't match configuration (%hX)."
584 "Probably not a SMC chip\n",
585 ioaddr, base_address_register >> 3 & 0x3E0);
586 /* well, the base address register didn't match. Must not have
587 * been a SMC chip after all. */
592 /* check if the revision register is something that I recognize.
593 * These might need to be added to later, as future revisions
595 SMC_SELECT_BANK(ioaddr, 3);
596 revision_register = inw(ioaddr + REVISION);
597 if (!chip_ids[(revision_register >> 4) & 0xF]) {
598 /* I don't recognize this chip, so... */
599 DBG( "SMC9000: IO %hX: Unrecognized revision register:"
600 " %hX, Contact author.\n", ioaddr, revision_register );
604 /* at this point I'll assume that the chip is an SMC9xxx.
605 * It might be prudent to check a listing of MAC addresses
606 * against the hardware address, or do some other tests. */
611 /**************************************************************************
612 * ETH_TRANSMIT - Transmit a frame
613 ***************************************************************************/
614 static void smc9000_transmit(
616 const char *d, /* Destination */
617 unsigned int t, /* Type */
618 unsigned int s, /* size */
619 const char *p) /* Packet */
621 word length; /* real, length incl. header */
623 unsigned long time_out;
628 /* We dont pad here since we can have the hardware doing it for us */
629 length = (s + ETH_HLEN + 1)&~1;
631 /* convert to MMU pages */
632 numPages = length / 256;
635 DBG("SMC9000: Far too big packet error. \n");
639 /* dont try more than, say 30 times */
641 /* now, try to allocate the memory */
642 SMC_SELECT_BANK(nic->ioaddr, 2);
643 _outw(MC_ALLOC | numPages, nic->ioaddr + MMU_CMD);
646 /* wait for the memory allocation to finnish */
647 for (time_out = currticks() + 5*TICKS_PER_SEC; currticks() < time_out; ) {
648 status = inb(nic->ioaddr + INTERRUPT);
649 if ( status & IM_ALLOC_INT ) {
650 /* acknowledge the interrupt */
651 _outb(IM_ALLOC_INT, nic->ioaddr + INTERRUPT);
656 if ((status & IM_ALLOC_INT) != 0 ) {
657 /* We've got the memory */
660 printf("SMC9000: Memory allocation timed out, resetting MMU.\n");
661 _outw(MC_RESET, nic->ioaddr + MMU_CMD);
665 /* If I get here, I _know_ there is a packet slot waiting for me */
666 packet_no = inb(nic->ioaddr + PNR_ARR + 1);
667 if (packet_no & 0x80) {
668 /* or isn't there? BAD CHIP! */
669 printf("SMC9000: Memory allocation failed. \n");
673 /* we have a packet address, so tell the card to use it */
674 _outb(packet_no, nic->ioaddr + PNR_ARR);
676 /* point to the beginning of the packet */
677 _outw(PTR_AUTOINC, nic->ioaddr + POINTER);
679 #if SMC9000_DEBUG > 2
680 printf("Trying to xmit packet of length %hX\n", length );
683 /* send the packet length ( +6 for status, length and ctl byte )
684 * and the status word ( set to zeros ) */
685 _outw(0, nic->ioaddr + DATA_1 );
687 /* send the packet length ( +6 for status words, length, and ctl) */
688 _outb((length+6) & 0xFF, nic->ioaddr + DATA_1);
689 _outb((length+6) >> 8 , nic->ioaddr + DATA_1);
691 /* Write the contents of the packet */
693 /* The ethernet header first... */
694 outsw(nic->ioaddr + DATA_1, d, ETH_ALEN >> 1);
695 outsw(nic->ioaddr + DATA_1, nic->node_addr, ETH_ALEN >> 1);
696 _outw(htons(t), nic->ioaddr + DATA_1);
698 /* ... the data ... */
699 outsw(nic->ioaddr + DATA_1 , p, s >> 1);
701 /* ... and the last byte, if there is one. */
703 _outw(0, nic->ioaddr + DATA_1);
705 _outb(p[s-1], nic->ioaddr + DATA_1);
706 _outb(0x20, nic->ioaddr + DATA_1);
709 /* and let the chipset deal with it */
710 _outw(MC_ENQUEUE , nic->ioaddr + MMU_CMD);
712 status = 0; time_out = currticks() + 5*TICKS_PER_SEC;
714 status = inb(nic->ioaddr + INTERRUPT);
716 if ((status & IM_TX_INT ) != 0) {
720 _outb(IM_TX_INT, nic->ioaddr + INTERRUPT);
722 packet_no = inw(nic->ioaddr + FIFO_PORTS);
725 /* select this as the packet to read from */
726 _outb( packet_no, nic->ioaddr + PNR_ARR );
728 /* read the first word from this packet */
729 _outw( PTR_AUTOINC | PTR_READ, nic->ioaddr + POINTER );
731 tx_status = inw( nic->ioaddr + DATA_1 );
733 if (0 == (tx_status & TS_SUCCESS)) {
734 DBG("SMC9000: TX FAIL STATUS: %hX \n", tx_status);
735 /* re-enable transmit */
736 SMC_SELECT_BANK(nic->ioaddr, 0);
737 _outw(inw(nic->ioaddr + TCR ) | TCR_ENABLE, nic->ioaddr + TCR );
740 /* kill the packet */
741 SMC_SELECT_BANK(nic->ioaddr, 2);
742 _outw(MC_FREEPKT, nic->ioaddr + MMU_CMD);
746 }while(currticks() < time_out);
748 printf("SMC9000: TX timed out, resetting board\n");
749 smc_reset(nic->ioaddr);
753 /**************************************************************************
754 * ETH_POLL - Wait for a frame
755 ***************************************************************************/
756 static int smc9000_poll(struct nic *nic, int retrieve)
758 SMC_SELECT_BANK(nic->ioaddr, 2);
759 if (inw(nic->ioaddr + FIFO_PORTS) & FP_RXEMPTY)
762 if ( ! retrieve ) return 1;
764 /* start reading from the start of the packet */
765 _outw(PTR_READ | PTR_RCV | PTR_AUTOINC, nic->ioaddr + POINTER);
767 /* First read the status and check that we're ok */
768 if (!(inw(nic->ioaddr + DATA_1) & RS_ERRORS)) {
769 /* Next: read the packet length and mask off the top bits */
770 nic->packetlen = (inw(nic->ioaddr + DATA_1) & 0x07ff);
772 /* the packet length includes the 3 extra words */
774 #if SMC9000_DEBUG > 2
775 printf(" Reading %d words (and %d byte(s))\n",
776 (nic->packetlen >> 1), nic->packetlen & 1);
778 /* read the packet (and the last "extra" word) */
779 insw(nic->ioaddr + DATA_1, nic->packet, (nic->packetlen+2) >> 1);
780 /* is there an odd last byte ? */
781 if (nic->packet[nic->packetlen+1] & 0x20)
784 /* error or good, tell the card to get rid of this packet */
785 _outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
789 printf("SMC9000: RX error\n");
790 /* error or good, tell the card to get rid of this packet */
791 _outw(MC_RELEASE, nic->ioaddr + MMU_CMD);
795 static void smc9000_disable ( struct nic *nic, struct isa_device *isa __unused ) {
797 smc_reset(nic->ioaddr);
799 /* no more interrupts for me */
800 SMC_SELECT_BANK(nic->ioaddr, 2);
801 _outb( 0, nic->ioaddr + INT_MASK);
803 /* and tell the card to stay away from that nasty outside world */
804 SMC_SELECT_BANK(nic->ioaddr, 0);
805 _outb( RCR_CLEAR, nic->ioaddr + RCR );
806 _outb( TCR_CLEAR, nic->ioaddr + TCR );
809 static void smc9000_irq(struct nic *nic __unused, irq_action_t action __unused)
821 static struct nic_operations smc9000_operations = {
822 .connect = dummy_connect,
823 .poll = smc9000_poll,
824 .transmit = smc9000_transmit,
829 /**************************************************************************
830 * ETH_PROBE - Look for an adapter
831 ***************************************************************************/
833 static int smc9000_probe ( struct nic *nic, struct isa_device *isa ) {
835 unsigned short revision;
838 const char * version_string;
839 const char * if_string;
843 nic->ioaddr = isa->ioaddr;
846 * Get the MAC address ( bank 1, regs 4 - 9 )
848 SMC_SELECT_BANK(nic->ioaddr, 1);
849 for ( i = 0; i < 6; i += 2 ) {
852 address = inw(nic->ioaddr + ADDR0 + i);
853 nic->node_addr[i+1] = address >> 8;
854 nic->node_addr[i] = address & 0xFF;
857 /* get the memory information */
858 SMC_SELECT_BANK(nic->ioaddr, 0);
859 memory = ( inw(nic->ioaddr + MCR) >> 9 ) & 0x7; /* multiplier */
860 memory *= 256 * (inw(nic->ioaddr + MIR) & 0xFF);
863 * Now, I want to find out more about the chip. This is sort of
864 * redundant, but it's cleaner to have it in both, rather than having
865 * one VERY long probe procedure.
867 SMC_SELECT_BANK(nic->ioaddr, 3);
868 revision = inw(nic->ioaddr + REVISION);
869 version_string = chip_ids[(revision >> 4) & 0xF];
871 if (((revision & 0xF0) >> 4 == CHIP_9196) &&
872 ((revision & 0x0F) >= REV_9196)) {
873 /* This is a 91c96. 'c96 has the same chip id as 'c94 (4) but
874 * a revision starting at 6 */
875 version_string = smc91c96_id;
878 if ( !version_string ) {
879 /* I shouldn't get here because this call was done before.... */
883 /* is it using AUI or 10BaseT ? */
884 SMC_SELECT_BANK(nic->ioaddr, 1);
885 if (inw(nic->ioaddr + CFG) & CFG_AUI_SELECT)
890 if_string = interfaces[media - 1];
892 /* now, reset the chip, and put it into a known state */
893 smc_reset(nic->ioaddr);
895 printf("SMC9000 %s\n", smc9000_version);
896 DBG("Copyright (C) 1998 Daniel Engstr\x94m\n");
897 DBG("Copyright (C) 1996 Eric Stahlman\n");
899 printf("%s rev:%d I/O port:%hX Interface:%s RAM:%d bytes \n",
900 version_string, revision & 0xF,
901 nic->ioaddr, if_string, memory );
903 DBG ( "Ethernet MAC address: %s\n", eth_ntoa ( nic->node_addr ) );
905 SMC_SELECT_BANK(nic->ioaddr, 0);
907 /* see the header file for options in TCR/RCR NORMAL*/
908 _outw(TCR_NORMAL, nic->ioaddr + TCR);
909 _outw(RCR_NORMAL, nic->ioaddr + RCR);
911 /* Select which interface to use */
912 SMC_SELECT_BANK(nic->ioaddr, 1);
914 _outw( inw( nic->ioaddr + CFG ) & ~CFG_AUI_SELECT,
917 else if ( media == 2 ) {
918 _outw( inw( nic->ioaddr + CFG ) | CFG_AUI_SELECT,
922 smc_phy_configure(nic->ioaddr);
924 nic->nic_op = &smc9000_operations;
929 * The SMC9000 can be at any of the following port addresses. To
930 * change for a slightly different card, you can add it to the array.
933 static isa_probe_addr_t smc9000_probe_addrs[] = {
934 0x200, 0x220, 0x240, 0x260, 0x280, 0x2A0, 0x2C0, 0x2E0,
935 0x300, 0x320, 0x340, 0x360, 0x380, 0x3A0, 0x3C0, 0x3E0,
938 ISA_DRIVER ( smc9000_driver, smc9000_probe_addrs, smc9000_probe_addr,
939 GENERIC_ISAPNP_VENDOR, 0x8228 );
941 DRIVER ( "SMC9000", nic_driver, isa_driver, smc9000_driver,
942 smc9000_probe, smc9000_disable );
944 ISA_ROM ( "smc9000", "SMC9000" );