6 * Realtek 10/100/1000 network card driver
10 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
13 #include <ipxe/spi_bit.h>
15 #include <ipxe/if_ether.h>
17 /** PCI memory BAR size */
18 #define RTL_BAR_SIZE 0x100
20 /** A packet descriptor */
21 struct realtek_descriptor {
30 } __attribute__ (( packed ));
32 /** Descriptor buffer size mask */
33 #define RTL_DESC_SIZE_MASK 0x3fff
35 /** Packet descriptor flags */
36 enum realtek_descriptor_flags {
37 /** Descriptor is owned by NIC */
38 RTL_DESC_OWN = 0x8000,
39 /** End of descriptor ring */
40 RTL_DESC_EOR = 0x4000,
41 /** First segment descriptor */
43 /** Last segment descriptor */
45 /** Receive error summary */
46 RTL_DESC_RES = 0x0020,
49 /** Descriptor ring alignment */
50 #define RTL_RING_ALIGN 256
52 /** A legacy mode receive packet header */
53 struct realtek_legacy_header {
60 } __attribute__ (( packed ));
62 /** Legacy mode status bits */
63 enum realtek_legacy_status {
65 RTL_STAT_ROK = 0x0001,
68 /** ID Register 0 (6 bytes) */
71 /** Multicast Register 0 (dword) */
74 /** Multicast Register 4 (dword) */
77 /** Transmit Status of Descriptor N (dword, 8139 only) */
78 #define RTL_TSD(n) ( 0x10 + 4 * (n) )
79 #define RTL_TSD_ERTXTH(x) ( (x) << 16 ) /**< Early TX threshold */
80 #define RTL_TSD_ERTXTH_DEFAULT RTL_TSD_ERTXTH ( 256 / 32 )
81 #define RTL_TSD_OWN 0x00002000UL /**< Ownership */
83 /** Transmit Start Address of Descriptor N (dword, 8139 only) */
84 #define RTL_TSAD(n) ( 0x20 + 4 * (n) )
86 /** Transmit Normal Priority Descriptors (qword) */
87 #define RTL_TNPDS 0x20
89 /** Number of transmit descriptors
91 * This is a hardware limit when using legacy mode.
93 #define RTL_NUM_TX_DESC 4
95 /** Receive Buffer Start Address (dword, 8139 only) */
96 #define RTL_RBSTART 0x30
98 /** Receive buffer length */
99 #define RTL_RXBUF_LEN 8192
101 /** Receive buffer padding */
102 #define RTL_RXBUF_PAD 2038 /* Allow space for WRAP */
104 /** Receive buffer alignment */
105 #define RTL_RXBUF_ALIGN 16
107 /** Command Register (byte) */
109 #define RTL_CR_RST 0x10 /**< Reset */
110 #define RTL_CR_RE 0x08 /**< Receiver Enable */
111 #define RTL_CR_TE 0x04 /**< Transmit Enable */
112 #define RTL_CR_BUFE 0x01 /**< Receive buffer empty */
114 /** Maximum time to wait for a reset, in milliseconds */
115 #define RTL_RESET_MAX_WAIT_MS 100
117 /** Current Address of Packet Read (word, 8139 only) */
118 #define RTL_CAPR 0x38
120 /** Transmit Priority Polling Register (byte, 8169 only) */
121 #define RTL_TPPOLL_8169 0x38
122 #define RTL_TPPOLL_NPQ 0x40 /**< Normal Priority Queue Polling */
124 /** Interrupt Mask Register (word) */
126 #define RTL_IRQ_PUN_LINKCHG 0x0020 /**< Packet underrun / link change */
127 #define RTL_IRQ_TER 0x0008 /**< Transmit error */
128 #define RTL_IRQ_TOK 0x0004 /**< Transmit OK */
129 #define RTL_IRQ_RER 0x0002 /**< Receive error */
130 #define RTL_IRQ_ROK 0x0001 /**< Receive OK */
132 /** Interrupt Status Register (word) */
135 /** Transmit (Tx) Configuration Register (dword) */
137 #define RTL_TCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
138 #define RTL_TCR_MXDMA_MASK RTL_TCR_MXDMA ( 0x7 )
139 #define RTL_TCR_MXDMA_DEFAULT RTL_TCR_MXDMA ( 0x7 /* Unlimited */ )
141 /** Receive (Rx) Configuration Register (dword) */
143 #define RTL_RCR_STOP_WORKING 0x01000000UL /**< Here be dragons */
144 #define RTL_RCR_RXFTH(x) ( (x) << 13 ) /**< Receive FIFO threshold */
145 #define RTL_RCR_RXFTH_MASK RTL_RCR_RXFTH ( 0x7 )
146 #define RTL_RCR_RXFTH_DEFAULT RTL_RCR_RXFTH ( 0x7 /* Whole packet */ )
147 #define RTL_RCR_RBLEN(x) ( (x) << 11 ) /**< Receive buffer length */
148 #define RTL_RCR_RBLEN_MASK RTL_RCR_RBLEN ( 0x3 )
149 #define RTL_RCR_RBLEN_DEFAULT RTL_RCR_RBLEN ( 0 /* 8kB */ )
150 #define RTL_RCR_MXDMA(x) ( (x) << 8 ) /**< Max DMA burst size */
151 #define RTL_RCR_MXDMA_MASK RTL_RCR_MXDMA ( 0x7 )
152 #define RTL_RCR_MXDMA_DEFAULT RTL_RCR_MXDMA ( 0x7 /* Unlimited */ )
153 #define RTL_RCR_WRAP 0x00000080UL /**< Overrun receive buffer */
154 #define RTL_RCR_9356SEL 0x00000040UL /**< EEPROM is a 93C56 */
155 #define RTL_RCR_AB 0x00000008UL /**< Accept broadcast packets */
156 #define RTL_RCR_AM 0x00000004UL /**< Accept multicast packets */
157 #define RTL_RCR_APM 0x00000002UL /**< Accept physical match */
158 #define RTL_RCR_AAP 0x00000001UL /**< Accept all packets */
160 /** 93C46 (93C56) Command Register (byte) */
161 #define RTL_9346CR 0x50
162 #define RTL_9346CR_EEM(x) ( (x) << 6 ) /**< Mode select */
163 #define RTL_9346CR_EEM_EEPROM RTL_9346CR_EEM ( 0x2 ) /**< EEPROM mode */
164 #define RTL_9346CR_EEM_NORMAL RTL_9346CR_EEM ( 0x0 ) /**< Normal mode */
165 #define RTL_9346CR_EECS 0x08 /**< Chip select */
166 #define RTL_9346CR_EESK 0x04 /**< Clock */
167 #define RTL_9346CR_EEDI 0x02 /**< Data in */
168 #define RTL_9346CR_EEDO 0x01 /**< Data out */
170 /** Word offset of ID code word within EEPROM */
171 #define RTL_EEPROM_ID ( 0x00 / 2 )
173 /** EEPROM code word magic value */
174 #define RTL_EEPROM_ID_MAGIC 0x8129
176 /** Word offset of MAC address within EEPROM */
177 #define RTL_EEPROM_MAC ( 0x0e / 2 )
179 /** Word offset of VPD / non-volatile options within EEPROM */
180 #define RTL_EEPROM_VPD ( 0x40 / 2 )
182 /** Length of VPD / non-volatile options within EEPROM */
183 #define RTL_EEPROM_VPD_LEN 0x40
185 /** Configuration Register 1 (byte) */
186 #define RTL_CONFIG1 0x52
187 #define RTL_CONFIG1_VPD 0x02 /**< Vital Product Data enabled */
189 /** Media Status Register (byte, 8139 only) */
191 #define RTL_MSR_TXFCE 0x80 /**< TX flow control enabled */
192 #define RTL_MSR_RXFCE 0x40 /**< RX flow control enabled */
193 #define RTL_MSR_AUX_STATUS 0x10 /**< Aux power present */
194 #define RTL_MSR_SPEED_10 0x08 /**< 10Mbps */
195 #define RTL_MSR_LINKB 0x04 /**< Inverse of link status */
196 #define RTL_MSR_TXPF 0x02 /**< TX pause flag */
197 #define RTL_MSR_RXPF 0x01 /**< RX pause flag */
199 /** PHY Access Register (dword, 8169 only) */
200 #define RTL_PHYAR 0x60
201 #define RTL_PHYAR_FLAG 0x80000000UL /**< Read/write flag */
203 /** Construct PHY Access Register value */
204 #define RTL_PHYAR_VALUE( flag, reg, data ) ( (flag) | ( (reg) << 16 ) | (data) )
206 /** Extract PHY Access Register data */
207 #define RTL_PHYAR_DATA( value ) ( (value) & 0xffff )
209 /** Maximum time to wait for PHY access, in microseconds */
210 #define RTL_MII_MAX_WAIT_US 500
212 /** PHY (GMII, MII, or TBI) Status Register (byte, 8169 only) */
213 #define RTL_PHYSTATUS 0x6c
214 #define RTL_PHYSTATUS_ENTBI 0x80 /**< TBI / GMII mode */
215 #define RTL_PHYSTATUS_TXFLOW 0x40 /**< TX flow control enabled */
216 #define RTL_PHYSTATUS_RXFLOW 0x20 /**< RX flow control enabled */
217 #define RTL_PHYSTATUS_1000MF 0x10 /**< 1000Mbps full-duplex */
218 #define RTL_PHYSTATUS_100M 0x08 /**< 100Mbps */
219 #define RTL_PHYSTATUS_10M 0x04 /**< 10Mbps */
220 #define RTL_PHYSTATUS_LINKSTS 0x02 /**< Link ok */
221 #define RTL_PHYSTATUS_FULLDUP 0x01 /**< Full duplex */
223 /** Transmit Priority Polling Register (byte, 8139C+ only) */
224 #define RTL_TPPOLL_8139CP 0xd9
226 /** RX Packet Maximum Size Register (word) */
229 /** C+ Command Register (word) */
230 #define RTL_CPCR 0xe0
231 #define RTL_CPCR_DAC 0x0010 /**< PCI Dual Address Cycle Enable */
232 #define RTL_CPCR_MULRW 0x0008 /**< PCI Multiple Read/Write Enable */
233 #define RTL_CPCR_CPRX 0x0002 /**< C+ receive enable */
234 #define RTL_CPCR_CPTX 0x0001 /**< C+ transmit enable */
236 /** Receive Descriptor Start Address Register (qword) */
237 #define RTL_RDSAR 0xe4
239 /** Number of receive descriptors */
240 #define RTL_NUM_RX_DESC 4
242 /** Receive buffer length */
243 #define RTL_RX_MAX_LEN \
244 ( ETH_FRAME_LEN + 4 /* VLAN */ + 4 /* CRC */ + 4 /* extra space */ )
246 /** A Realtek descriptor ring */
247 struct realtek_ring {
249 struct realtek_descriptor *desc;
250 /** Producer index */
252 /** Consumer index */
255 /** Descriptor start address register */
257 /** Length (in bytes) */
262 * Initialise descriptor ring
264 * @v ring Descriptor ring
265 * @v count Number of descriptors
266 * @v reg Descriptor start address register
268 static inline __attribute__ (( always_inline)) void
269 realtek_init_ring ( struct realtek_ring *ring, unsigned int count,
271 ring->len = ( count * sizeof ( ring->desc[0] ) );
275 /** A Realtek network card */
279 /** SPI bit-bashing interface */
280 struct spi_bit_basher spibit;
282 struct spi_device eeprom;
283 /** Non-volatile options */
284 struct nvo_block nvo;
286 struct mii_interface mii;
288 /** Legacy datapath mode */
290 /** PHYAR and PHYSTATUS registers are present */
292 /** TPPoll register offset */
295 /** Transmit descriptor ring */
296 struct realtek_ring tx;
297 /** Receive descriptor ring */
298 struct realtek_ring rx;
299 /** Receive I/O buffers */
300 struct io_buffer *rx_iobuf[RTL_NUM_RX_DESC];
301 /** Receive buffer (legacy mode) */
303 /** Offset within receive buffer (legacy mode) */
304 unsigned int rx_offset;
307 #endif /* _REALTEK_H */