2 * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
4 * (EEPROM code originally implemented for rtl8139.c)
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of the
9 * License, or (at your option) any later version.
11 * This program is distributed in the hope that it will be useful, but
12 * WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
14 * General Public License for more details.
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
22 FILE_LICENCE ( GPL2_OR_LATER );
29 #include <ipxe/netdevice.h>
30 #include <ipxe/ethernet.h>
31 #include <ipxe/if_ether.h>
32 #include <ipxe/iobuf.h>
33 #include <ipxe/malloc.h>
36 #include <ipxe/threewire.h>
37 #include <ipxe/bitbash.h>
43 * Realtek 10/100/1000 network card driver
45 * Based on the following datasheets:
47 * http://www.datasheetarchive.com/dl/Datasheets-8/DSA-153536.pdf
48 * http://www.datasheetarchive.com/indexdl/Datasheet-028/DSA00494723.pdf
51 /******************************************************************************
55 ******************************************************************************
59 * Dump all registers (for debugging)
61 * @v rtl Realtek device
63 static __attribute__ (( unused )) void realtek_dump ( struct realtek_nic *rtl ){
67 /* Do nothing unless debug output is enabled */
71 /* Dump registers (via byte accesses; may not work for all registers) */
72 for ( i = 0 ; i < sizeof ( regs ) ; i++ )
73 regs[i] = readb ( rtl->regs + i );
74 DBGC ( rtl, "REALTEK %p register dump:\n", rtl );
75 DBGC_HDA ( rtl, 0, regs, sizeof ( regs ) );
78 /******************************************************************************
82 ******************************************************************************
85 /** Pin mapping for SPI bit-bashing interface */
86 static const uint8_t realtek_eeprom_bits[] = {
87 [SPI_BIT_SCLK] = RTL_9346CR_EESK,
88 [SPI_BIT_MOSI] = RTL_9346CR_EEDI,
89 [SPI_BIT_MISO] = RTL_9346CR_EEDO,
90 [SPI_BIT_SS(0)] = RTL_9346CR_EECS,
94 * Open bit-bashing interface
96 * @v basher Bit-bashing interface
98 static void realtek_spi_open_bit ( struct bit_basher *basher ) {
99 struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
102 /* Enable EEPROM access */
103 writeb ( RTL_9346CR_EEM_EEPROM, rtl->regs + RTL_9346CR );
104 readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
108 * Close bit-bashing interface
110 * @v basher Bit-bashing interface
112 static void realtek_spi_close_bit ( struct bit_basher *basher ) {
113 struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
116 /* Disable EEPROM access */
117 writeb ( RTL_9346CR_EEM_NORMAL, rtl->regs + RTL_9346CR );
118 readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
124 * @v basher Bit-bashing interface
125 * @v bit_id Bit number
126 * @ret zero Input is a logic 0
127 * @ret non-zero Input is a logic 1
129 static int realtek_spi_read_bit ( struct bit_basher *basher,
130 unsigned int bit_id ) {
131 struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
133 uint8_t mask = realtek_eeprom_bits[bit_id];
136 DBG_DISABLE ( DBGLVL_IO );
137 reg = readb ( rtl->regs + RTL_9346CR );
138 DBG_ENABLE ( DBGLVL_IO );
139 return ( reg & mask );
143 * Set/clear output bit
145 * @v basher Bit-bashing interface
146 * @v bit_id Bit number
147 * @v data Value to write
149 static void realtek_spi_write_bit ( struct bit_basher *basher,
150 unsigned int bit_id, unsigned long data ) {
151 struct realtek_nic *rtl = container_of ( basher, struct realtek_nic,
153 uint8_t mask = realtek_eeprom_bits[bit_id];
156 DBG_DISABLE ( DBGLVL_IO );
157 reg = readb ( rtl->regs + RTL_9346CR );
159 reg |= ( data & mask );
160 writeb ( reg, rtl->regs + RTL_9346CR );
161 readb ( rtl->regs + RTL_9346CR ); /* Ensure write reaches chip */
162 DBG_ENABLE ( DBGLVL_IO );
165 /** SPI bit-bashing interface */
166 static struct bit_basher_operations realtek_basher_ops = {
167 .open = realtek_spi_open_bit,
168 .close = realtek_spi_close_bit,
169 .read = realtek_spi_read_bit,
170 .write = realtek_spi_write_bit,
176 * @v netdev Network device
177 * @ret rc Return status code
179 static int realtek_init_eeprom ( struct net_device *netdev ) {
180 struct realtek_nic *rtl = netdev->priv;
184 /* Initialise SPI bit-bashing interface */
185 rtl->spibit.basher.op = &realtek_basher_ops;
186 rtl->spibit.bus.mode = SPI_MODE_THREEWIRE;
187 init_spi_bit_basher ( &rtl->spibit );
189 /* Detect EEPROM type and initialise three-wire device */
190 if ( readl ( rtl->regs + RTL_RCR ) & RTL_RCR_9356SEL ) {
191 DBGC ( rtl, "REALTEK %p EEPROM is a 93C56\n", rtl );
192 init_at93c56 ( &rtl->eeprom, 16 );
194 DBGC ( rtl, "REALTEK %p EEPROM is a 93C46\n", rtl );
195 init_at93c46 ( &rtl->eeprom, 16 );
197 rtl->eeprom.bus = &rtl->spibit.bus;
199 /* Check for EEPROM presence. Some onboard NICs will have no
200 * EEPROM connected, with the BIOS being responsible for
201 * programming the initial register values.
203 if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_ID,
204 &id, sizeof ( id ) ) ) != 0 ) {
205 DBGC ( rtl, "REALTEK %p could not read EEPROM ID: %s\n",
206 rtl, strerror ( rc ) );
209 if ( id != cpu_to_le16 ( RTL_EEPROM_ID_MAGIC ) ) {
210 DBGC ( rtl, "REALTEK %p EEPROM ID incorrect (%#04x); assuming "
211 "no EEPROM\n", rtl, le16_to_cpu ( id ) );
215 /* Initialise space for non-volatile options, if available
217 * We use offset 0x40 (i.e. address 0x20), length 0x40. This
218 * block is marked as VPD in the Realtek datasheets, so we use
219 * it only if we detect that the card is not supporting VPD.
221 if ( readb ( rtl->regs + RTL_CONFIG1 ) & RTL_CONFIG1_VPD ) {
222 DBGC ( rtl, "REALTEK %p EEPROM in use for VPD; cannot use "
223 "for options\n", rtl );
225 nvo_init ( &rtl->nvo, &rtl->eeprom.nvs, RTL_EEPROM_VPD,
226 RTL_EEPROM_VPD_LEN, NULL, &netdev->refcnt );
232 /******************************************************************************
236 ******************************************************************************
240 * Read from MII register
242 * @v mii MII interface
243 * @v reg Register address
244 * @ret value Data read, or negative error
246 static int realtek_mii_read ( struct mii_interface *mii, unsigned int reg ) {
247 struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
251 /* Fail if PHYAR register is not present */
252 if ( ! rtl->have_phy_regs )
256 writel ( RTL_PHYAR_VALUE ( 0, reg, 0 ), rtl->regs + RTL_PHYAR );
258 /* Wait for read to complete */
259 for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
261 /* If read is not complete, delay 1us and retry */
262 value = readl ( rtl->regs + RTL_PHYAR );
263 if ( ! ( value & RTL_PHYAR_FLAG ) ) {
268 /* Return register value */
269 return ( RTL_PHYAR_DATA ( value ) );
272 DBGC ( rtl, "REALTEK %p timed out waiting for MII read\n", rtl );
277 * Write to MII register
279 * @v mii MII interface
280 * @v reg Register address
281 * @v data Data to write
282 * @ret rc Return status code
284 static int realtek_mii_write ( struct mii_interface *mii, unsigned int reg,
286 struct realtek_nic *rtl = container_of ( mii, struct realtek_nic, mii );
289 /* Fail if PHYAR register is not present */
290 if ( ! rtl->have_phy_regs )
294 writel ( RTL_PHYAR_VALUE ( RTL_PHYAR_FLAG, reg, data ),
295 rtl->regs + RTL_PHYAR );
297 /* Wait for write to complete */
298 for ( i = 0 ; i < RTL_MII_MAX_WAIT_US ; i++ ) {
300 /* If write is not complete, delay 1us and retry */
301 if ( readl ( rtl->regs + RTL_PHYAR ) & RTL_PHYAR_FLAG ) {
309 DBGC ( rtl, "REALTEK %p timed out waiting for MII write\n", rtl );
313 /** Realtek MII operations */
314 static struct mii_operations realtek_mii_operations = {
315 .read = realtek_mii_read,
316 .write = realtek_mii_write,
319 /******************************************************************************
323 ******************************************************************************
329 * @v rtl Realtek device
330 * @ret rc Return status code
332 static int realtek_reset ( struct realtek_nic *rtl ) {
336 writeb ( RTL_CR_RST, rtl->regs + RTL_CR );
338 /* Wait for reset to complete */
339 for ( i = 0 ; i < RTL_RESET_MAX_WAIT_MS ; i++ ) {
341 /* If reset is not complete, delay 1ms and retry */
342 if ( readb ( rtl->regs + RTL_CR ) & RTL_CR_RST ) {
350 DBGC ( rtl, "REALTEK %p timed out waiting for reset\n", rtl );
355 * Configure PHY for Gigabit operation
357 * @v rtl Realtek device
358 * @ret rc Return status code
360 static int realtek_phy_speed ( struct realtek_nic *rtl ) {
364 /* Read CTRL1000 register */
365 ctrl1000 = mii_read ( &rtl->mii, MII_CTRL1000 );
366 if ( ctrl1000 < 0 ) {
368 DBGC ( rtl, "REALTEK %p could not read CTRL1000: %s\n",
369 rtl, strerror ( rc ) );
373 /* Advertise 1000Mbps speeds */
374 ctrl1000 |= ( ADVERTISE_1000FULL | ADVERTISE_1000HALF );
375 if ( ( rc = mii_write ( &rtl->mii, MII_CTRL1000, ctrl1000 ) ) != 0 ) {
376 DBGC ( rtl, "REALTEK %p could not write CTRL1000: %s\n",
377 rtl, strerror ( rc ) );
387 * @v rtl Realtek device
388 * @ret rc Return status code
390 static int realtek_phy_reset ( struct realtek_nic *rtl ) {
393 /* Do nothing if we have no separate PHY register access */
394 if ( ! rtl->have_phy_regs )
397 /* Perform MII reset */
398 if ( ( rc = mii_reset ( &rtl->mii ) ) != 0 ) {
399 DBGC ( rtl, "REALTEK %p could not reset MII: %s\n",
400 rtl, strerror ( rc ) );
404 /* Some cards (e.g. RTL8169SC) do not advertise Gigabit by
405 * default. Try to enable advertisement of Gigabit speeds.
407 if ( ( rc = realtek_phy_speed ( rtl ) ) != 0 ) {
408 /* Ignore failures, since the register may not be
409 * present on non-Gigabit PHYs (e.g. RTL8101).
413 /* Restart autonegotiation */
414 if ( ( rc = mii_restart ( &rtl->mii ) ) != 0 ) {
415 DBGC ( rtl, "REALTEK %p could not restart MII: %s\n",
416 rtl, strerror ( rc ) );
423 /******************************************************************************
427 ******************************************************************************
433 * @v netdev Network device
435 static void realtek_check_link ( struct net_device *netdev ) {
436 struct realtek_nic *rtl = netdev->priv;
441 /* Determine link state */
442 if ( rtl->have_phy_regs ) {
443 mii_dump ( &rtl->mii );
444 phystatus = readb ( rtl->regs + RTL_PHYSTATUS );
445 link_up = ( phystatus & RTL_PHYSTATUS_LINKSTS );
446 DBGC ( rtl, "REALTEK %p PHY status is %02x (%s%s%s%s%s%s, "
447 "Link%s, %sDuplex)\n", rtl, phystatus,
448 ( ( phystatus & RTL_PHYSTATUS_ENTBI ) ? "TBI" : "GMII" ),
449 ( ( phystatus & RTL_PHYSTATUS_TXFLOW ) ?
451 ( ( phystatus & RTL_PHYSTATUS_RXFLOW ) ?
453 ( ( phystatus & RTL_PHYSTATUS_1000MF ) ?
455 ( ( phystatus & RTL_PHYSTATUS_100M ) ?
457 ( ( phystatus & RTL_PHYSTATUS_10M ) ?
459 ( ( phystatus & RTL_PHYSTATUS_LINKSTS ) ?
461 ( ( phystatus & RTL_PHYSTATUS_FULLDUP ) ?
464 msr = readb ( rtl->regs + RTL_MSR );
465 link_up = ( ! ( msr & RTL_MSR_LINKB ) );
466 DBGC ( rtl, "REALTEK %p media status is %02x (Link%s, "
467 "%dMbps%s%s%s%s%s)\n", rtl, msr,
468 ( ( msr & RTL_MSR_LINKB ) ? "Down" : "Up" ),
469 ( ( msr & RTL_MSR_SPEED_10 ) ? 10 : 100 ),
470 ( ( msr & RTL_MSR_TXFCE ) ? ", TxFlow" : "" ),
471 ( ( msr & RTL_MSR_RXFCE ) ? ", RxFlow" : "" ),
472 ( ( msr & RTL_MSR_AUX_STATUS ) ? ", AuxPwr" : "" ),
473 ( ( msr & RTL_MSR_TXPF ) ? ", TxPause" : "" ),
474 ( ( msr & RTL_MSR_RXPF ) ? ", RxPause" : "" ) );
477 /* Report link state */
479 netdev_link_up ( netdev );
481 netdev_link_down ( netdev );
485 /******************************************************************************
487 * Network device interface
489 ******************************************************************************
493 * Create receive buffer (legacy mode)
495 * @v rtl Realtek device
496 * @ret rc Return status code
498 static int realtek_create_buffer ( struct realtek_nic *rtl ) {
499 size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
503 /* Do nothing unless in legacy mode */
507 /* Allocate buffer */
508 rtl->rx_buffer = malloc_dma ( len, RTL_RXBUF_ALIGN );
509 if ( ! rtl->rx_buffer ) {
513 address = virt_to_bus ( rtl->rx_buffer );
515 /* Check that card can support address */
516 if ( address & ~0xffffffffULL ) {
517 DBGC ( rtl, "REALTEK %p cannot support 64-bit RX buffer "
523 /* Program buffer address */
524 writel ( address, rtl->regs + RTL_RBSTART );
525 DBGC ( rtl, "REALTEK %p receive buffer is at [%08llx,%08llx,%08llx)\n",
526 rtl, ( ( unsigned long long ) address ),
527 ( ( unsigned long long ) address + RTL_RXBUF_LEN ),
528 ( ( unsigned long long ) address + len ) );
533 free_dma ( rtl->rx_buffer, len );
534 rtl->rx_buffer = NULL;
540 * Destroy receive buffer (legacy mode)
542 * @v rtl Realtek device
544 static void realtek_destroy_buffer ( struct realtek_nic *rtl ) {
545 size_t len = ( RTL_RXBUF_LEN + RTL_RXBUF_PAD );
547 /* Do nothing unless in legacy mode */
551 /* Clear buffer address */
552 writel ( 0, rtl->regs + RTL_RBSTART );
555 free_dma ( rtl->rx_buffer, len );
556 rtl->rx_buffer = NULL;
561 * Create descriptor ring
563 * @v rtl Realtek device
564 * @v ring Descriptor ring
565 * @ret rc Return status code
567 static int realtek_create_ring ( struct realtek_nic *rtl,
568 struct realtek_ring *ring ) {
571 /* Do nothing in legacy mode */
575 /* Allocate descriptor ring */
576 ring->desc = malloc_dma ( ring->len, RTL_RING_ALIGN );
580 /* Initialise descriptor ring */
581 memset ( ring->desc, 0, ring->len );
583 /* Program ring address */
584 address = virt_to_bus ( ring->desc );
585 writel ( ( ( ( uint64_t ) address ) >> 32 ),
586 rtl->regs + ring->reg + 4 );
587 writel ( ( address & 0xffffffffUL ), rtl->regs + ring->reg );
588 DBGC ( rtl, "REALTEK %p ring %02x is at [%08llx,%08llx)\n",
589 rtl, ring->reg, ( ( unsigned long long ) address ),
590 ( ( unsigned long long ) address + ring->len ) );
596 * Destroy descriptor ring
598 * @v rtl Realtek device
599 * @v ring Descriptor ring
601 static void realtek_destroy_ring ( struct realtek_nic *rtl,
602 struct realtek_ring *ring ) {
604 /* Reset producer and consumer counters */
608 /* Do nothing more if in legacy mode */
612 /* Clear ring address */
613 writel ( 0, rtl->regs + ring->reg );
614 writel ( 0, rtl->regs + ring->reg + 4 );
616 /* Free descriptor ring */
617 free_dma ( ring->desc, ring->len );
622 * Refill receive descriptor ring
624 * @v rtl Realtek device
626 static void realtek_refill_rx ( struct realtek_nic *rtl ) {
627 struct realtek_descriptor *rx;
628 struct io_buffer *iobuf;
633 /* Do nothing in legacy mode */
637 while ( ( rtl->rx.prod - rtl->rx.cons ) < RTL_NUM_RX_DESC ) {
639 /* Allocate I/O buffer */
640 iobuf = alloc_iob ( RTL_RX_MAX_LEN );
642 /* Wait for next refill */
646 /* Get next receive descriptor */
647 rx_idx = ( rtl->rx.prod++ % RTL_NUM_RX_DESC );
648 is_last = ( rx_idx == ( RTL_NUM_RX_DESC - 1 ) );
649 rx = &rtl->rx.desc[rx_idx];
651 /* Populate receive descriptor */
652 address = virt_to_bus ( iobuf->data );
653 rx->address = cpu_to_le64 ( address );
654 rx->length = cpu_to_le16 ( RTL_RX_MAX_LEN );
656 rx->flags = ( cpu_to_le16 ( RTL_DESC_OWN ) |
657 ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
660 /* Record I/O buffer */
661 assert ( rtl->rx_iobuf[rx_idx] == NULL );
662 rtl->rx_iobuf[rx_idx] = iobuf;
664 DBGC2 ( rtl, "REALTEK %p RX %d is [%llx,%llx)\n", rtl, rx_idx,
665 ( ( unsigned long long ) address ),
666 ( ( unsigned long long ) address + RTL_RX_MAX_LEN ) );
671 * Open network device
673 * @v netdev Network device
674 * @ret rc Return status code
676 static int realtek_open ( struct net_device *netdev ) {
677 struct realtek_nic *rtl = netdev->priv;
682 /* Create transmit descriptor ring */
683 if ( ( rc = realtek_create_ring ( rtl, &rtl->tx ) ) != 0 )
686 /* Create receive descriptor ring */
687 if ( ( rc = realtek_create_ring ( rtl, &rtl->rx ) ) != 0 )
690 /* Create receive buffer */
691 if ( ( rc = realtek_create_buffer ( rtl ) ) != 0 )
692 goto err_create_buffer;
694 /* Accept all packets */
695 writel ( 0xffffffffUL, rtl->regs + RTL_MAR0 );
696 writel ( 0xffffffffUL, rtl->regs + RTL_MAR4 );
698 /* Enable transmitter and receiver. RTL8139 requires that
699 * this happens before writing to RCR.
701 writeb ( ( RTL_CR_TE | RTL_CR_RE ), rtl->regs + RTL_CR );
703 /* Configure transmitter */
704 tcr = readl ( rtl->regs + RTL_TCR );
705 tcr &= ~RTL_TCR_MXDMA_MASK;
706 tcr |= RTL_TCR_MXDMA_DEFAULT;
707 writel ( tcr, rtl->regs + RTL_TCR );
709 /* Configure receiver */
710 rcr = readl ( rtl->regs + RTL_RCR );
711 rcr &= ~( RTL_RCR_STOP_WORKING | RTL_RCR_RXFTH_MASK |
712 RTL_RCR_RBLEN_MASK | RTL_RCR_MXDMA_MASK );
713 rcr |= ( RTL_RCR_RXFTH_DEFAULT | RTL_RCR_RBLEN_DEFAULT |
714 RTL_RCR_MXDMA_DEFAULT | RTL_RCR_WRAP | RTL_RCR_AB |
715 RTL_RCR_AM | RTL_RCR_APM | RTL_RCR_AAP );
716 writel ( rcr, rtl->regs + RTL_RCR );
718 /* Fill receive ring */
719 realtek_refill_rx ( rtl );
721 /* Update link state */
722 realtek_check_link ( netdev );
726 realtek_destroy_buffer ( rtl );
728 realtek_destroy_ring ( rtl, &rtl->rx );
730 realtek_destroy_ring ( rtl, &rtl->tx );
736 * Close network device
738 * @v netdev Network device
740 static void realtek_close ( struct net_device *netdev ) {
741 struct realtek_nic *rtl = netdev->priv;
744 /* Disable receiver and transmitter */
745 writeb ( 0, rtl->regs + RTL_CR );
747 /* Destroy receive buffer */
748 realtek_destroy_buffer ( rtl );
750 /* Destroy receive descriptor ring */
751 realtek_destroy_ring ( rtl, &rtl->rx );
753 /* Discard any unused receive buffers */
754 for ( i = 0 ; i < RTL_NUM_RX_DESC ; i++ ) {
755 if ( rtl->rx_iobuf[i] )
756 free_iob ( rtl->rx_iobuf[i] );
757 rtl->rx_iobuf[i] = NULL;
760 /* Destroy transmit descriptor ring */
761 realtek_destroy_ring ( rtl, &rtl->tx );
767 * @v netdev Network device
768 * @v iobuf I/O buffer
769 * @ret rc Return status code
771 static int realtek_transmit ( struct net_device *netdev,
772 struct io_buffer *iobuf ) {
773 struct realtek_nic *rtl = netdev->priv;
774 struct realtek_descriptor *tx;
779 /* Get next transmit descriptor */
780 if ( ( rtl->tx.prod - rtl->tx.cons ) >= RTL_NUM_TX_DESC ) {
781 netdev_tx_defer ( netdev, iobuf );
784 tx_idx = ( rtl->tx.prod++ % RTL_NUM_TX_DESC );
786 /* Transmit packet */
789 /* Pad and align packet */
790 iob_pad ( iobuf, ETH_ZLEN );
791 address = virt_to_bus ( iobuf->data );
793 /* Check that card can support address */
794 if ( address & ~0xffffffffULL ) {
795 DBGC ( rtl, "REALTEK %p cannot support 64-bit TX "
796 "buffer address\n", rtl );
800 /* Add to transmit ring */
801 writel ( address, rtl->regs + RTL_TSAD ( tx_idx ) );
802 writel ( ( RTL_TSD_ERTXTH_DEFAULT | iob_len ( iobuf ) ),
803 rtl->regs + RTL_TSD ( tx_idx ) );
807 /* Populate transmit descriptor */
808 address = virt_to_bus ( iobuf->data );
809 is_last = ( tx_idx == ( RTL_NUM_TX_DESC - 1 ) );
810 tx = &rtl->tx.desc[tx_idx];
811 tx->address = cpu_to_le64 ( address );
812 tx->length = cpu_to_le16 ( iob_len ( iobuf ) );
814 tx->flags = ( cpu_to_le16 ( RTL_DESC_OWN | RTL_DESC_FS |
816 ( is_last ? cpu_to_le16 ( RTL_DESC_EOR ) : 0 ) );
819 /* Notify card that there are packets ready to transmit */
820 writeb ( RTL_TPPOLL_NPQ, rtl->regs + rtl->tppoll );
823 DBGC2 ( rtl, "REALTEK %p TX %d is [%llx,%llx)\n", rtl, tx_idx,
824 ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ),
825 ( ( ( unsigned long long ) virt_to_bus ( iobuf->data ) ) +
826 iob_len ( iobuf ) ) );
832 * Poll for completed packets
834 * @v netdev Network device
836 static void realtek_poll_tx ( struct net_device *netdev ) {
837 struct realtek_nic *rtl = netdev->priv;
838 struct realtek_descriptor *tx;
841 /* Check for completed packets */
842 while ( rtl->tx.cons != rtl->tx.prod ) {
844 /* Get next transmit descriptor */
845 tx_idx = ( rtl->tx.cons % RTL_NUM_TX_DESC );
847 /* Stop if descriptor is still in use */
850 /* Check ownership bit in transmit status register */
851 if ( ! ( readl ( rtl->regs + RTL_TSD ( tx_idx ) ) &
857 /* Check ownership bit in descriptor */
858 tx = &rtl->tx.desc[tx_idx];
859 if ( tx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
863 DBGC2 ( rtl, "REALTEK %p TX %d complete\n", rtl, tx_idx );
865 /* Complete TX descriptor */
867 netdev_tx_complete_next ( netdev );
872 * Poll for received packets (legacy mode)
874 * @v netdev Network device
876 static void realtek_legacy_poll_rx ( struct net_device *netdev ) {
877 struct realtek_nic *rtl = netdev->priv;
878 struct realtek_legacy_header *rx;
879 struct io_buffer *iobuf;
882 /* Check for received packets */
883 while ( ! ( readb ( rtl->regs + RTL_CR ) & RTL_CR_BUFE ) ) {
885 /* Extract packet from receive buffer */
886 rx = ( rtl->rx_buffer + rtl->rx_offset );
887 len = le16_to_cpu ( rx->length );
888 if ( rx->status & cpu_to_le16 ( RTL_STAT_ROK ) ) {
890 DBGC2 ( rtl, "REALTEK %p RX offset %x+%zx\n",
891 rtl, rtl->rx_offset, len );
893 /* Allocate I/O buffer */
894 iobuf = alloc_iob ( len );
896 netdev_rx_err ( netdev, NULL, -ENOMEM );
897 /* Leave packet for next poll */
901 /* Copy data to I/O buffer */
902 memcpy ( iob_put ( iobuf, len ), rx->data, len );
903 iob_unput ( iobuf, 4 /* strip CRC */ );
905 /* Hand off to network stack */
906 netdev_rx ( netdev, iobuf );
910 DBGC ( rtl, "REALTEK %p RX offset %x+%zx error %04x\n",
911 rtl, rtl->rx_offset, len,
912 le16_to_cpu ( rx->status ) );
913 netdev_rx_err ( netdev, NULL, -EIO );
916 /* Update buffer offset */
917 rtl->rx_offset = ( rtl->rx_offset + sizeof ( *rx ) + len );
918 rtl->rx_offset = ( ( rtl->rx_offset + 3 ) & ~3 );
919 rtl->rx_offset = ( rtl->rx_offset % RTL_RXBUF_LEN );
920 writew ( ( rtl->rx_offset - 16 ), rtl->regs + RTL_CAPR );
922 /* Give chip time to react before rechecking RTL_CR */
923 readw ( rtl->regs + RTL_CAPR );
928 * Poll for received packets
930 * @v netdev Network device
932 static void realtek_poll_rx ( struct net_device *netdev ) {
933 struct realtek_nic *rtl = netdev->priv;
934 struct realtek_descriptor *rx;
935 struct io_buffer *iobuf;
939 /* Poll receive buffer if in legacy mode */
941 realtek_legacy_poll_rx ( netdev );
945 /* Check for received packets */
946 while ( rtl->rx.cons != rtl->rx.prod ) {
948 /* Get next receive descriptor */
949 rx_idx = ( rtl->rx.cons % RTL_NUM_RX_DESC );
950 rx = &rtl->rx.desc[rx_idx];
952 /* Stop if descriptor is still in use */
953 if ( rx->flags & cpu_to_le16 ( RTL_DESC_OWN ) )
956 /* Populate I/O buffer */
957 iobuf = rtl->rx_iobuf[rx_idx];
958 rtl->rx_iobuf[rx_idx] = NULL;
959 len = ( le16_to_cpu ( rx->length ) & RTL_DESC_SIZE_MASK );
960 iob_put ( iobuf, ( len - 4 /* strip CRC */ ) );
962 /* Hand off to network stack */
963 if ( rx->flags & cpu_to_le16 ( RTL_DESC_RES ) ) {
964 DBGC ( rtl, "REALTEK %p RX %d error (length %zd, "
965 "flags %04x)\n", rtl, rx_idx, len,
966 le16_to_cpu ( rx->flags ) );
967 netdev_rx_err ( netdev, iobuf, -EIO );
969 DBGC2 ( rtl, "REALTEK %p RX %d complete (length "
970 "%zd)\n", rtl, rx_idx, len );
971 netdev_rx ( netdev, iobuf );
978 * Poll for completed and received packets
980 * @v netdev Network device
982 static void realtek_poll ( struct net_device *netdev ) {
983 struct realtek_nic *rtl = netdev->priv;
986 /* Check for and acknowledge interrupts */
987 isr = readw ( rtl->regs + RTL_ISR );
990 writew ( isr, rtl->regs + RTL_ISR );
992 /* Poll for TX completions, if applicable */
993 if ( isr & ( RTL_IRQ_TER | RTL_IRQ_TOK ) )
994 realtek_poll_tx ( netdev );
996 /* Poll for RX completionsm, if applicable */
997 if ( isr & ( RTL_IRQ_RER | RTL_IRQ_ROK ) )
998 realtek_poll_rx ( netdev );
1000 /* Check link state, if applicable */
1001 if ( isr & RTL_IRQ_PUN_LINKCHG )
1002 realtek_check_link ( netdev );
1004 /* Refill RX ring */
1005 realtek_refill_rx ( rtl );
1009 * Enable or disable interrupts
1011 * @v netdev Network device
1012 * @v enable Interrupts should be enabled
1014 static void realtek_irq ( struct net_device *netdev, int enable ) {
1015 struct realtek_nic *rtl = netdev->priv;
1018 /* Set interrupt mask */
1019 imr = ( enable ? ( RTL_IRQ_PUN_LINKCHG | RTL_IRQ_TER | RTL_IRQ_TOK |
1020 RTL_IRQ_RER | RTL_IRQ_ROK ) : 0 );
1021 writew ( imr, rtl->regs + RTL_IMR );
1024 /** Realtek network device operations */
1025 static struct net_device_operations realtek_operations = {
1026 .open = realtek_open,
1027 .close = realtek_close,
1028 .transmit = realtek_transmit,
1029 .poll = realtek_poll,
1033 /******************************************************************************
1037 ******************************************************************************
1041 * Detect device type
1043 * @v rtl Realtek device
1045 static void realtek_detect ( struct realtek_nic *rtl ) {
1049 uint16_t check_cpcr;
1051 /* The RX Packet Maximum Size register is present only on
1052 * 8169. Try to set to our intended MTU.
1054 rms = RTL_RX_MAX_LEN;
1055 writew ( rms, rtl->regs + RTL_RMS );
1056 check_rms = readw ( rtl->regs + RTL_RMS );
1058 /* The C+ Command register is present only on 8169 and 8139C+.
1059 * Try to enable C+ mode and PCI Dual Address Cycle (for
1060 * 64-bit systems), if supported.
1062 * Note that enabling DAC seems to cause bizarre behaviour
1063 * (lockups, garbage data on the wire) on some systems, even
1064 * if only 32-bit addresses are used.
1066 cpcr = readw ( rtl->regs + RTL_CPCR );
1067 cpcr |= ( RTL_CPCR_MULRW | RTL_CPCR_CPRX | RTL_CPCR_CPTX );
1068 if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) )
1069 cpcr |= RTL_CPCR_DAC;
1070 writew ( cpcr, rtl->regs + RTL_CPCR );
1071 check_cpcr = readw ( rtl->regs + RTL_CPCR );
1073 /* Detect device type */
1074 if ( check_rms == rms ) {
1075 DBGC ( rtl, "REALTEK %p appears to be an RTL8169\n", rtl );
1076 rtl->have_phy_regs = 1;
1077 rtl->tppoll = RTL_TPPOLL_8169;
1079 if ( ( check_cpcr == cpcr ) && ( cpcr != 0xffff ) ) {
1080 DBGC ( rtl, "REALTEK %p appears to be an RTL8139C+\n",
1082 rtl->tppoll = RTL_TPPOLL_8139CP;
1084 DBGC ( rtl, "REALTEK %p appears to be an RTL8139\n",
1095 * @ret rc Return status code
1097 static int realtek_probe ( struct pci_device *pci ) {
1098 struct net_device *netdev;
1099 struct realtek_nic *rtl;
1103 /* Allocate and initialise net device */
1104 netdev = alloc_etherdev ( sizeof ( *rtl ) );
1109 netdev_init ( netdev, &realtek_operations );
1111 pci_set_drvdata ( pci, netdev );
1112 netdev->dev = &pci->dev;
1113 memset ( rtl, 0, sizeof ( *rtl ) );
1114 realtek_init_ring ( &rtl->tx, RTL_NUM_TX_DESC, RTL_TNPDS );
1115 realtek_init_ring ( &rtl->rx, RTL_NUM_RX_DESC, RTL_RDSAR );
1117 /* Fix up PCI device */
1118 adjust_pci_device ( pci );
1121 rtl->regs = ioremap ( pci->membase, RTL_BAR_SIZE );
1122 if ( ! rtl->regs ) {
1128 if ( ( rc = realtek_reset ( rtl ) ) != 0 )
1131 /* Detect device type */
1132 realtek_detect ( rtl );
1134 /* Initialise EEPROM */
1135 if ( ( rc = realtek_init_eeprom ( netdev ) ) == 0 ) {
1137 /* Read MAC address from EEPROM */
1138 if ( ( rc = nvs_read ( &rtl->eeprom.nvs, RTL_EEPROM_MAC,
1139 netdev->hw_addr, ETH_ALEN ) ) != 0 ) {
1140 DBGC ( rtl, "REALTEK %p could not read MAC address: "
1141 "%s\n", rtl, strerror ( rc ) );
1147 /* EEPROM not present. Fall back to reading the
1148 * current ID register value, which will hopefully
1149 * have been programmed by the platform firmware.
1151 for ( i = 0 ; i < ETH_ALEN ; i++ )
1152 netdev->hw_addr[i] = readb ( rtl->regs + RTL_IDR0 + i );
1155 /* Initialise and reset MII interface */
1156 mii_init ( &rtl->mii, &realtek_mii_operations );
1157 if ( ( rc = realtek_phy_reset ( rtl ) ) != 0 )
1160 /* Register network device */
1161 if ( ( rc = register_netdev ( netdev ) ) != 0 )
1162 goto err_register_netdev;
1164 /* Set initial link state */
1165 realtek_check_link ( netdev );
1167 /* Register non-volatile options, if applicable */
1168 if ( rtl->nvo.nvs ) {
1169 if ( ( rc = register_nvo ( &rtl->nvo,
1170 netdev_settings ( netdev ) ) ) != 0)
1171 goto err_register_nvo;
1177 unregister_netdev ( netdev );
1178 err_register_netdev:
1181 realtek_reset ( rtl );
1183 iounmap ( rtl->regs );
1185 netdev_nullify ( netdev );
1186 netdev_put ( netdev );
1196 static void realtek_remove ( struct pci_device *pci ) {
1197 struct net_device *netdev = pci_get_drvdata ( pci );
1198 struct realtek_nic *rtl = netdev->priv;
1200 /* Unregister non-volatile options, if applicable */
1202 unregister_nvo ( &rtl->nvo );
1204 /* Unregister network device */
1205 unregister_netdev ( netdev );
1208 realtek_reset ( rtl );
1210 /* Free network device */
1211 iounmap ( rtl->regs );
1212 netdev_nullify ( netdev );
1213 netdev_put ( netdev );
1216 /** Realtek PCI device IDs */
1217 static struct pci_device_id realtek_nics[] = {
1218 PCI_ROM ( 0x0001, 0x8168, "clone8169", "Cloned 8169", 0 ),
1219 PCI_ROM ( 0x018a, 0x0106, "fpc0106tx", "LevelOne FPC-0106TX", 0 ),
1220 PCI_ROM ( 0x021b, 0x8139, "hne300", "Compaq HNE-300", 0 ),
1221 PCI_ROM ( 0x02ac, 0x1012, "s1012", "SpeedStream 1012", 0 ),
1222 PCI_ROM ( 0x0357, 0x000a, "ttpmon", "TTTech TTP-Monitoring", 0 ),
1223 PCI_ROM ( 0x10ec, 0x8129, "rtl8129", "RTL-8129", 0 ),
1224 PCI_ROM ( 0x10ec, 0x8136, "rtl8136", "RTL8101E/RTL8102E", 0 ),
1225 PCI_ROM ( 0x10ec, 0x8138, "rtl8138", "RT8139 (B/C)", 0 ),
1226 PCI_ROM ( 0x10ec, 0x8139, "rtl8139", "RTL-8139/8139C/8139C+", 0 ),
1227 PCI_ROM ( 0x10ec, 0x8167, "rtl8167", "RTL-8110SC/8169SC", 0 ),
1228 PCI_ROM ( 0x10ec, 0x8168, "rtl8168", "RTL8111/8168B", 0 ),
1229 PCI_ROM ( 0x10ec, 0x8169, "rtl8169", "RTL-8169", 0 ),
1230 PCI_ROM ( 0x1113, 0x1211, "smc1211", "SMC2-1211TX", 0 ),
1231 PCI_ROM ( 0x1186, 0x1300, "dfe538", "DFE530TX+/DFE538TX", 0 ),
1232 PCI_ROM ( 0x1186, 0x1340, "dfe690", "DFE-690TXD", 0 ),
1233 PCI_ROM ( 0x1186, 0x4300, "dge528t", "DGE-528T", 0 ),
1234 PCI_ROM ( 0x11db, 0x1234, "sega8139", "Sega Enterprises 8139", 0 ),
1235 PCI_ROM ( 0x1259, 0xa117, "allied8139", "Allied Telesyn 8139", 0 ),
1236 PCI_ROM ( 0x1259, 0xa11e, "allied81xx", "Allied Telesyn 81xx", 0 ),
1237 PCI_ROM ( 0x1259, 0xc107, "allied8169", "Allied Telesyn 8169", 0 ),
1238 PCI_ROM ( 0x126c, 0x1211, "northen8139","Northern Telecom 8139", 0 ),
1239 PCI_ROM ( 0x13d1, 0xab06, "fe2000vx", "Abocom FE2000VX", 0 ),
1240 PCI_ROM ( 0x1432, 0x9130, "edi8139", "Edimax 8139", 0 ),
1241 PCI_ROM ( 0x14ea, 0xab06, "fnw3603tx", "Planex FNW-3603-TX", 0 ),
1242 PCI_ROM ( 0x14ea, 0xab07, "fnw3800tx", "Planex FNW-3800-TX", 0 ),
1243 PCI_ROM ( 0x1500, 0x1360, "delta8139", "Delta Electronics 8139", 0 ),
1244 PCI_ROM ( 0x16ec, 0x0116, "usr997902", "USR997902", 0 ),
1245 PCI_ROM ( 0x1737, 0x1032, "linksys8169","Linksys 8169", 0 ),
1246 PCI_ROM ( 0x1743, 0x8139, "rolf100", "Peppercorn ROL/F-100", 0 ),
1247 PCI_ROM ( 0x4033, 0x1360, "addron8139", "Addtron 8139", 0 ),
1248 PCI_ROM ( 0xffff, 0x8139, "clonse8139", "Cloned 8139", 0 ),
1251 /** Realtek PCI driver */
1252 struct pci_driver realtek_driver __pci_driver = {
1253 .ids = realtek_nics,
1254 .id_count = ( sizeof ( realtek_nics ) / sizeof ( realtek_nics[0] ) ),
1255 .probe = realtek_probe,
1256 .remove = realtek_remove,