2 * Copyright (c) 2010 Andrei Faur <da3drus@gmail.com>
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
21 FILE_LICENCE ( GPL2_OR_LATER );
26 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
29 * Set the number of Tx and Rx buffers, using Log_2(# buffers).
30 * Set default values to 16 Tx buffers and 32 Rx buffers.
32 #define PCNET32_LOG_TX_BUFFERS 4
33 #define PCNET32_LOG_RX_BUFFERS 5
35 /* Maximum number of descriptor rings is 512 */
36 #define PCNET32_LOG_MAX_TX_BUFFERS 9
37 #define PCNET32_LOG_MAX_RX_BUFFERS 9
39 #define TX_RING_SIZE ( 1 << ( PCNET32_LOG_TX_BUFFERS ) )
40 #define TX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_TX_BUFFERS ) )
42 #define RX_RING_SIZE ( 1 << ( PCNET32_LOG_RX_BUFFERS ) )
43 #define RX_MAX_RING_SIZE ( 1 << ( PCNET32_LOG_MAX_RX_BUFFERS ) )
45 #define RX_RING_BYTES ( RX_RING_SIZE * sizeof(struct pcnet32_rx_desc ) )
46 #define TX_RING_BYTES ( TX_RING_SIZE * sizeof(struct pcnet32_tx_desc ) )
48 #define PKT_BUF_SIZE 1536
50 #define RX_RING_ALIGN 16
51 #define TX_RING_ALIGN 16
53 #define INIT_BLOCK_ALIGN 32
55 #define PCNET32_WIO_RDP 0x10
56 #define PCNET32_WIO_RAP 0x12
57 #define PCNET32_WIO_RESET 0x14
58 #define PCNET32_WIO_BDP 0x16
60 #define PCNET32_DWIO_RDP 0x10
61 #define PCNET32_DWIO_RAP 0x14
62 #define PCNET32_DWIO_RESET 0x18
63 #define PCNET32_DWIO_BDP 0x1C
65 #define PCNET32_PORT_AUI 0x00
66 #define PCNET32_PORT_10BT 0x01
67 #define PCNET32_PORT_GPSI 0x02
68 #define PCNET32_PORT_MII 0x03
70 #define PCNET32_PORT_PORTSEL 0x03
71 #define PCNET32_PORT_ASEL 0x04
72 #define PCNET32_PORT_100 0x40
73 #define PCNET32_PORT_FD 0x80
75 #define PCNET32_SWSTYLE_LANCE 0x00
76 #define PCNET32_SWSTYLE_ILACC 0x01
77 #define PCNET32_SWSTYLE_PCNET32 0x02
79 #define PCNET32_MAX_PHYS 32
81 #ifndef PCI_VENDOR_ID_AT
82 #define PCI_VENDOR_ID_AT 0x1259
85 #ifndef PCI_SUBDEVICE_ID_AT_2700FX
86 #define PCI_SUBDEVICE_ID_AT_2700FX 0x2701
89 #ifndef PCI_SUBDEVICE_ID_AT_2701FX
90 #define PCI_SUBDEVICE_ID_AT_2701FX 0x2703
93 struct pcnet32_rx_desc {
101 struct pcnet32_tx_desc {
109 struct pcnet32_init_block {
119 struct pcnet32_access {
120 u16 ( *read_csr ) ( unsigned long, int );
121 void ( *write_csr ) ( unsigned long, int, u16 );
122 u16 ( *read_bcr ) ( unsigned long, int );
123 void ( *write_bcr ) ( unsigned long, int, u16 );
124 u16 ( *read_rap ) ( unsigned long );
125 void ( *write_rap ) ( unsigned long, u16 );
126 void ( *reset ) ( unsigned long );
129 struct pcnet32_private {
130 struct pcnet32_init_block init_block __attribute__((aligned(32)));
131 struct pci_device *pci_dev;
132 struct net_device *netdev;
134 struct io_buffer *rx_iobuf[RX_RING_SIZE];
135 struct io_buffer *tx_iobuf[TX_RING_SIZE];
137 struct pcnet32_rx_desc *rx_base;
138 struct pcnet32_tx_desc *tx_base;
142 uint32_t tx_fill_ctr;
144 struct pcnet32_access *a;
149 unsigned short chip_version;
154 enum pcnet32_desc_status_bit {
156 StartOfPacket = (1 << 9),
157 EndOfPacket = (1 << 8)
160 enum pcnet32_register_content {
161 /* CSR0 bits - Controller status register */
166 IntEnable = (1 << 6),
172 /* CSR3 bits - Controller status register */
173 BablMask = (1 << 14),
174 MissFrameMask = (1 << 12),
175 MemErrMask = (1 << 11),
176 RxIntMask = (1 << 10),
177 TxIntMask = (1 << 9),
178 InitDoneMask = (1 << 8)
182 #endif /* _PCNET32_H_ */