2 * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
20 FILE_LICENCE ( GPL2_OR_LATER );
27 #include <ipxe/netdevice.h>
28 #include <ipxe/ethernet.h>
29 #include <ipxe/if_ether.h>
30 #include <ipxe/iobuf.h>
31 #include <ipxe/malloc.h>
34 #include <ipxe/bitbash.h>
35 #include <ipxe/spi_bit.h>
36 #include <ipxe/threewire.h>
41 * National Semiconductor "MacPhyter" network card driver
43 * Based on the following datasheets:
45 * http://www.ti.com/lit/ds/symlink/dp83820.pdf
46 * http://www.datasheets.org.uk/indexdl/Datasheet-03/DSA0041338.pdf
50 /******************************************************************************
54 ******************************************************************************
57 /** Pin mapping for SPI bit-bashing interface */
58 static const uint8_t natsemi_eeprom_bits[] = {
59 [SPI_BIT_SCLK] = NATSEMI_MEAR_EECLK,
60 [SPI_BIT_MOSI] = NATSEMI_MEAR_EEDI,
61 [SPI_BIT_MISO] = NATSEMI_MEAR_EEDO,
62 [SPI_BIT_SS(0)] = NATSEMI_MEAR_EESEL,
68 * @v basher Bit-bashing interface
69 * @v bit_id Bit number
70 * @ret zero Input is a logic 0
71 * @ret non-zero Input is a logic 1
73 static int natsemi_spi_read_bit ( struct bit_basher *basher,
74 unsigned int bit_id ) {
75 struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
77 uint32_t mask = natsemi_eeprom_bits[bit_id];
80 DBG_DISABLE ( DBGLVL_IO );
81 reg = readl ( natsemi->regs + NATSEMI_MEAR );
82 DBG_ENABLE ( DBGLVL_IO );
83 return ( reg & mask );
87 * Set/clear output bit
89 * @v basher Bit-bashing interface
90 * @v bit_id Bit number
91 * @v data Value to write
93 static void natsemi_spi_write_bit ( struct bit_basher *basher,
94 unsigned int bit_id, unsigned long data ) {
95 struct natsemi_nic *natsemi = container_of ( basher, struct natsemi_nic,
97 uint32_t mask = natsemi_eeprom_bits[bit_id];
100 DBG_DISABLE ( DBGLVL_IO );
101 reg = readl ( natsemi->regs + NATSEMI_MEAR );
103 reg |= ( data & mask );
104 writel ( reg, natsemi->regs + NATSEMI_MEAR );
105 DBG_ENABLE ( DBGLVL_IO );
108 /** SPI bit-bashing interface */
109 static struct bit_basher_operations natsemi_basher_ops = {
110 .read = natsemi_spi_read_bit,
111 .write = natsemi_spi_write_bit,
117 * @v natsemi National Semiconductor device
119 static void natsemi_init_eeprom ( struct natsemi_nic *natsemi ) {
121 /* Initialise SPI bit-bashing interface */
122 natsemi->spibit.basher.op = &natsemi_basher_ops;
123 natsemi->spibit.bus.mode = SPI_MODE_THREEWIRE;
124 natsemi->spibit.endianness =
125 ( ( natsemi->flags & NATSEMI_EEPROM_LITTLE_ENDIAN ) ?
126 SPI_BIT_LITTLE_ENDIAN : SPI_BIT_BIG_ENDIAN );
127 init_spi_bit_basher ( &natsemi->spibit );
129 /* Initialise EEPROM device */
130 init_at93c06 ( &natsemi->eeprom, 16 );
131 natsemi->eeprom.bus = &natsemi->spibit.bus;
135 * Get hardware address from sane EEPROM data
137 * @v natsemi National Semiconductor device
138 * @v eeprom EEPROM data
139 * @v hw_addr Hardware address to fill in
141 static void natsemi_hwaddr_sane ( struct natsemi_nic *natsemi,
142 const uint16_t *eeprom, uint16_t *hw_addr ) {
145 /* Copy MAC address from EEPROM data */
146 for ( i = ( ( ETH_ALEN / 2 ) - 1 ) ; i >= 0 ; i-- )
147 *(hw_addr++) = eeprom[ NATSEMI_EEPROM_MAC_SANE + i ];
149 DBGC ( natsemi, "NATSEMI %p has sane EEPROM layout\n", natsemi );
153 * Get hardware address from insane EEPROM data
155 * @v natsemi National Semiconductor device
156 * @v eeprom EEPROM data
157 * @v hw_addr Hardware address to fill in
159 static void natsemi_hwaddr_insane ( struct natsemi_nic *natsemi,
160 const uint16_t *eeprom,
161 uint16_t *hw_addr ) {
166 /* Copy MAC address from EEPROM data */
167 for ( i = 0 ; i < ( ETH_ALEN / 2 ) ; i++ ) {
168 offset = ( NATSEMI_EEPROM_MAC_INSANE + i );
169 word = ( ( le16_to_cpu ( eeprom[ offset ] ) >> 15 ) |
170 ( le16_to_cpu ( eeprom[ offset + 1 ] << 1 ) ) );
171 hw_addr[i] = cpu_to_le16 ( word );
174 DBGC ( natsemi, "NATSEMI %p has insane EEPROM layout\n", natsemi );
178 * Get hardware address from EEPROM
180 * @v natsemi National Semiconductor device
181 * @v hw_addr Hardware address to fill in
182 * @ret rc Return status code
184 static int natsemi_hwaddr ( struct natsemi_nic *natsemi, void *hw_addr ) {
185 uint16_t buf[NATSEMI_EEPROM_SIZE];
186 void ( * extract ) ( struct natsemi_nic *natsemi,
187 const uint16_t *eeprom, uint16_t *hw_addr );
190 /* Read EEPROM contents */
191 if ( ( rc = nvs_read ( &natsemi->eeprom.nvs, 0, buf,
192 sizeof ( buf ) ) ) != 0 ) {
193 DBGC ( natsemi, "NATSEMI %p could not read EEPROM: %s\n",
194 natsemi, strerror ( rc ) );
197 DBGC2 ( natsemi, "NATSEMI %p EEPROM contents:\n", natsemi );
198 DBGC2_HDA ( natsemi, 0, buf, sizeof ( buf ) );
200 /* Extract MAC address from EEPROM contents */
201 extract = ( ( natsemi->flags & NATSEMI_EEPROM_INSANE ) ?
202 natsemi_hwaddr_insane : natsemi_hwaddr_sane );
203 extract ( natsemi, buf, hw_addr );
208 /******************************************************************************
212 ******************************************************************************
216 * Reset controller chip
218 * @v natsemi National Semiconductor device
219 * @ret rc Return status code
221 static int natsemi_soft_reset ( struct natsemi_nic *natsemi ) {
225 writel ( NATSEMI_CR_RST, natsemi->regs + NATSEMI_CR );
227 /* Wait for reset to complete */
228 for ( i = 0 ; i < NATSEMI_RESET_MAX_WAIT_MS ; i++ ) {
230 /* If reset is not complete, delay 1ms and retry */
231 if ( readl ( natsemi->regs + NATSEMI_CR ) & NATSEMI_CR_RST ) {
239 DBGC ( natsemi, "NATSEMI %p timed out waiting for reset\n", natsemi );
244 * Reload configuration from EEPROM
246 * @v natsemi National Semiconductor device
247 * @ret rc Return status code
249 static int natsemi_reload_config ( struct natsemi_nic *natsemi ) {
252 /* Initiate reload */
253 writel ( NATSEMI_PTSCR_EELOAD_EN, natsemi->regs + NATSEMI_PTSCR );
255 /* Wait for reload to complete */
256 for ( i = 0 ; i < NATSEMI_EELOAD_MAX_WAIT_MS ; i++ ) {
258 /* If reload is not complete, delay 1ms and retry */
259 if ( readl ( natsemi->regs + NATSEMI_PTSCR ) &
260 NATSEMI_PTSCR_EELOAD_EN ) {
268 DBGC ( natsemi, "NATSEMI %p timed out waiting for configuration "
269 "reload\n", natsemi );
276 * @v natsemi National Semiconductor device
277 * @ret rc Return status code
279 static int natsemi_reset ( struct natsemi_nic *natsemi ) {
283 /* Perform soft reset */
284 if ( ( rc = natsemi_soft_reset ( natsemi ) ) != 0 )
287 /* Reload configuration from EEPROM */
288 if ( ( rc = natsemi_reload_config ( natsemi ) ) != 0 )
291 /* Configure 64-bit operation, if applicable */
292 cfg = readl ( natsemi->regs + NATSEMI_CFG );
293 if ( natsemi->flags & NATSEMI_64BIT ) {
294 cfg |= ( NATSEMI_CFG_M64ADDR | NATSEMI_CFG_EXTSTS_EN );
295 if ( ! ( cfg & NATSEMI_CFG_PCI64_DET ) )
296 cfg &= ~NATSEMI_CFG_DATA64_EN;
298 writel ( cfg, natsemi->regs + NATSEMI_CFG );
300 /* Invalidate link status cache to force an update */
303 DBGC ( natsemi, "NATSEMI %p using configuration %08x\n",
308 /******************************************************************************
312 ******************************************************************************
318 * @v netdev Network device
320 static void natsemi_check_link ( struct net_device *netdev ) {
321 struct natsemi_nic *natsemi = netdev->priv;
324 /* Read link status */
325 cfg = readl ( natsemi->regs + NATSEMI_CFG );
327 /* Do nothing unless link status has changed */
328 if ( cfg == natsemi->cfg )
331 /* Set gigabit mode (if applicable) */
332 if ( natsemi->flags & NATSEMI_1000 ) {
333 cfg &= ~NATSEMI_CFG_MODE_1000;
334 if ( ! ( cfg & NATSEMI_CFG_SPDSTS1 ) )
335 cfg |= NATSEMI_CFG_MODE_1000;
336 writel ( cfg, natsemi->regs + NATSEMI_CFG );
339 /* Update link status */
341 DBGC ( natsemi, "NATSEMI %p link status is %08x\n", natsemi, cfg );
343 /* Update network device */
344 if ( cfg & NATSEMI_CFG_LNKSTS ) {
345 netdev_link_up ( netdev );
347 netdev_link_down ( netdev );
351 /******************************************************************************
353 * Network device interface
355 ******************************************************************************
359 * Set perfect match filter address
361 * @v natsemi National Semiconductor device
364 static void natsemi_pmatch ( struct natsemi_nic *natsemi, const void *mac ) {
365 const uint16_t *pmatch = mac;
370 for ( i = 0 ; i < ETH_ALEN ; i += sizeof ( *pmatch ) ) {
372 /* Select receive filter register address */
373 rfaddr = ( NATSEMI_RFADDR_PMATCH_BASE + i );
374 rfcr = readl ( natsemi->regs + NATSEMI_RFCR );
375 rfcr &= ~NATSEMI_RFCR_RFADDR_MASK;
376 rfcr |= NATSEMI_RFCR_RFADDR ( rfaddr );
377 writel ( rfcr, natsemi->regs + NATSEMI_RFCR );
379 /* Write receive filter data */
380 writel ( ( le16_to_cpu ( *(pmatch++) ) | NATSEMI_RFDR_BMASK ),
381 natsemi->regs + NATSEMI_RFDR );
386 * Create descriptor ring
388 * @v natsemi National Semiconductor device
389 * @v ring Descriptor ring
390 * @ret rc Return status code
392 static int natsemi_create_ring ( struct natsemi_nic *natsemi,
393 struct natsemi_ring *ring ) {
394 size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
395 union natsemi_descriptor *desc;
396 union natsemi_descriptor *linked_desc;
403 /* Calculate descriptor offset */
404 offset = ( ( natsemi->flags & NATSEMI_64BIT ) ? 0 :
405 offsetof ( typeof ( desc[i].d32pad ), d32 ) );
407 /* Allocate descriptor ring. Align ring on its own size to
408 * ensure that it can't possibly cross the boundary of 32-bit
411 ring->desc = malloc_dma ( len, len );
412 if ( ! ring->desc ) {
416 address = ( virt_to_bus ( ring->desc ) + offset );
418 /* Check address is usable by card */
419 if ( ! natsemi_address_ok ( natsemi, address ) ) {
420 DBGC ( natsemi, "NATSEMI %p cannot support 64-bit ring "
421 "address\n", natsemi );
426 /* Initialise descriptor ring */
427 memset ( ring->desc, 0, len );
428 for ( i = 0 ; i < ring->count ; i++ ) {
429 linked_desc = &ring->desc [ ( i + 1 ) % ring->count ];
430 link = ( virt_to_bus ( linked_desc ) + offset );
431 if ( natsemi->flags & NATSEMI_64BIT ) {
432 ring->desc[i].d64.link = cpu_to_le64 ( link );
434 ring->desc[i].d32pad.d32.link = cpu_to_le32 ( link );
438 /* Program ring address */
439 writel ( ( address & 0xffffffffUL ), natsemi->regs + ring->reg );
440 if ( natsemi->flags & NATSEMI_64BIT ) {
441 if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
442 writel ( ( ( ( uint64_t ) address ) >> 32 ),
443 natsemi->regs + ring->reg + 4 );
445 writel ( 0, natsemi->regs + ring->reg + 4 );
449 DBGC ( natsemi, "NATSEMI %p ring %02x is at [%08llx,%08llx)\n",
451 ( ( unsigned long long ) virt_to_bus ( ring->desc ) ),
452 ( ( unsigned long long ) virt_to_bus ( ring->desc ) + len ) );
457 free_dma ( ring->desc, len );
464 * Destroy descriptor ring
466 * @v natsemi National Semiconductor device
467 * @v ring Descriptor ring
469 static void natsemi_destroy_ring ( struct natsemi_nic *natsemi,
470 struct natsemi_ring *ring ) {
471 size_t len = ( ring->count * sizeof ( ring->desc[0] ) );
473 /* Clear ring address */
474 writel ( 0, natsemi->regs + ring->reg );
475 if ( natsemi->flags & NATSEMI_64BIT )
476 writel ( 0, natsemi->regs + ring->reg + 4 );
478 /* Free descriptor ring */
479 free_dma ( ring->desc, len );
486 * Refill receive descriptor ring
488 * @v netdev Network device
490 static void natsemi_refill_rx ( struct net_device *netdev ) {
491 struct natsemi_nic *natsemi = netdev->priv;
492 union natsemi_descriptor *rx;
493 struct io_buffer *iobuf;
497 while ( ( natsemi->rx.prod - natsemi->rx.cons ) < NATSEMI_NUM_RX_DESC ){
499 /* Allocate I/O buffer */
500 iobuf = alloc_iob ( NATSEMI_RX_MAX_LEN );
502 /* Wait for next refill */
506 /* Check address is usable by card */
507 address = virt_to_bus ( iobuf->data );
508 if ( ! natsemi_address_ok ( natsemi, address ) ) {
509 DBGC ( natsemi, "NATSEMI %p cannot support 64-bit RX "
510 "buffer address\n", natsemi );
511 netdev_rx_err ( netdev, iobuf, -ENOTSUP );
515 /* Get next receive descriptor */
516 rx_idx = ( natsemi->rx.prod++ % NATSEMI_NUM_RX_DESC );
517 rx = &natsemi->rx.desc[rx_idx];
519 /* Populate receive descriptor */
520 if ( natsemi->flags & NATSEMI_64BIT ) {
521 rx->d64.bufptr = cpu_to_le64 ( address );
523 rx->d32pad.d32.bufptr = cpu_to_le32 ( address );
526 rx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_INTR |
527 NATSEMI_RX_MAX_LEN );
530 /* Record I/O buffer */
531 assert ( natsemi->rx_iobuf[rx_idx] == NULL );
532 natsemi->rx_iobuf[rx_idx] = iobuf;
534 /* Notify card that there are descriptors available */
535 writel ( NATSEMI_CR_RXE, natsemi->regs + NATSEMI_CR );
537 DBGC2 ( natsemi, "NATSEMI %p RX %d is [%llx,%llx)\n", natsemi,
538 rx_idx, ( ( unsigned long long ) address ),
539 ( ( unsigned long long ) address + NATSEMI_RX_MAX_LEN));
544 * Open network device
546 * @v netdev Network device
547 * @ret rc Return status code
549 static int natsemi_open ( struct net_device *netdev ) {
550 struct natsemi_nic *natsemi = netdev->priv;
553 /* Set MAC address */
554 natsemi_pmatch ( natsemi, netdev->ll_addr );
556 /* Create transmit descriptor ring */
557 if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->tx ) ) != 0 )
560 /* Set transmit configuration */
561 writel ( ( NATSEMI_TXCFG_CSI | NATSEMI_TXCFG_HBI | NATSEMI_TXCFG_ATP |
562 NATSEMI_TXCFG_ECRETRY | NATSEMI_TXCFG_MXDMA_DEFAULT |
563 NATSEMI_TXCFG_FLTH_DEFAULT | NATSEMI_TXCFG_DRTH_DEFAULT ),
564 ( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
565 NATSEMI_TXCFG_64 : NATSEMI_TXCFG_32 ) ) );
567 /* Create receive descriptor ring */
568 if ( ( rc = natsemi_create_ring ( natsemi, &natsemi->rx ) ) != 0 )
571 /* Set receive configuration */
572 writel ( ( NATSEMI_RXCFG_ARP | NATSEMI_RXCFG_ATX | NATSEMI_RXCFG_ALP |
573 NATSEMI_RXCFG_MXDMA_DEFAULT | NATSEMI_RXCFG_DRTH_DEFAULT ),
574 ( natsemi->regs + ( ( natsemi->flags & NATSEMI_64BIT ) ?
575 NATSEMI_RXCFG_64 : NATSEMI_RXCFG_32 ) ) );
577 /* Set receive filter configuration */
578 writel ( ( NATSEMI_RFCR_RFEN | NATSEMI_RFCR_AAB | NATSEMI_RFCR_AAM |
579 NATSEMI_RFCR_AAU ), natsemi->regs + NATSEMI_RFCR );
581 /* Fill receive ring */
582 natsemi_refill_rx ( netdev );
584 /* Unmask transmit and receive interrupts. (Interrupts will
585 * not be generated unless enabled via the IER.)
587 writel ( ( NATSEMI_IRQ_TXDESC | NATSEMI_IRQ_RXDESC ),
588 natsemi->regs + NATSEMI_IMR );
590 /* Update link state */
591 natsemi_check_link ( netdev );
595 natsemi_destroy_ring ( natsemi, &natsemi->rx );
597 natsemi_destroy_ring ( natsemi, &natsemi->tx );
603 * Close network device
605 * @v netdev Network device
607 static void natsemi_close ( struct net_device *netdev ) {
608 struct natsemi_nic *natsemi = netdev->priv;
611 /* Mask transmit and receive interrupts */
612 writel ( 0, natsemi->regs + NATSEMI_IMR );
614 /* Reset and disable transmitter and receiver */
615 writel ( ( NATSEMI_CR_RXR | NATSEMI_CR_TXR ),
616 natsemi->regs + NATSEMI_CR );
618 /* Discard any unused receive buffers */
619 for ( i = 0 ; i < NATSEMI_NUM_RX_DESC ; i++ ) {
620 if ( natsemi->rx_iobuf[i] )
621 free_iob ( natsemi->rx_iobuf[i] );
622 natsemi->rx_iobuf[i] = NULL;
625 /* Destroy receive descriptor ring */
626 natsemi_destroy_ring ( natsemi, &natsemi->rx );
628 /* Destroy transmit descriptor ring */
629 natsemi_destroy_ring ( natsemi, &natsemi->tx );
635 * @v netdev Network device
636 * @v iobuf I/O buffer
637 * @ret rc Return status code
639 static int natsemi_transmit ( struct net_device *netdev,
640 struct io_buffer *iobuf ) {
641 struct natsemi_nic *natsemi = netdev->priv;
642 union natsemi_descriptor *tx;
646 /* Check address is usable by card */
647 address = virt_to_bus ( iobuf->data );
648 if ( ! natsemi_address_ok ( natsemi, address ) ) {
649 DBGC ( natsemi, "NATSEMI %p cannot support 64-bit TX buffer "
650 "address\n", natsemi );
654 /* Get next transmit descriptor */
655 if ( ( natsemi->tx.prod - natsemi->tx.cons ) >= NATSEMI_NUM_TX_DESC ) {
656 DBGC ( natsemi, "NATSEMI %p out of transmit descriptors\n",
660 tx_idx = ( natsemi->tx.prod++ % NATSEMI_NUM_TX_DESC );
661 tx = &natsemi->tx.desc[tx_idx];
663 /* Populate transmit descriptor */
664 if ( natsemi->flags & NATSEMI_64BIT ) {
665 tx->d64.bufptr = cpu_to_le64 ( address );
667 tx->d32pad.d32.bufptr = cpu_to_le32 ( address );
670 tx->common.cmdsts = cpu_to_le32 ( NATSEMI_DESC_OWN | NATSEMI_DESC_INTR |
674 /* Notify card that there are packets ready to transmit */
675 writel ( NATSEMI_CR_TXE, natsemi->regs + NATSEMI_CR );
677 DBGC2 ( natsemi, "NATSEMI %p TX %d is [%llx,%llx)\n", natsemi, tx_idx,
678 ( ( unsigned long long ) address ),
679 ( ( unsigned long long ) address + iob_len ( iobuf ) ) );
685 * Poll for completed packets
687 * @v netdev Network device
689 static void natsemi_poll_tx ( struct net_device *netdev ) {
690 struct natsemi_nic *natsemi = netdev->priv;
691 union natsemi_descriptor *tx;
694 /* Check for completed packets */
695 while ( natsemi->tx.cons != natsemi->tx.prod ) {
697 /* Get next transmit descriptor */
698 tx_idx = ( natsemi->tx.cons % NATSEMI_NUM_TX_DESC );
699 tx = &natsemi->tx.desc[tx_idx];
701 /* Stop if descriptor is still in use */
702 if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OWN ) )
705 /* Complete TX descriptor */
706 if ( tx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
707 DBGC2 ( natsemi, "NATSEMI %p TX %d complete\n",
709 netdev_tx_complete_next ( netdev );
711 DBGC ( natsemi, "NATSEMI %p TX %d completion error "
712 "(%08x)\n", natsemi, tx_idx,
713 le32_to_cpu ( tx->common.cmdsts ) );
714 netdev_tx_complete_next_err ( netdev, -EIO );
721 * Poll for received packets
723 * @v netdev Network device
725 static void natsemi_poll_rx ( struct net_device *netdev ) {
726 struct natsemi_nic *natsemi = netdev->priv;
727 union natsemi_descriptor *rx;
728 struct io_buffer *iobuf;
732 /* Check for received packets */
733 while ( natsemi->rx.cons != natsemi->rx.prod ) {
735 /* Get next receive descriptor */
736 rx_idx = ( natsemi->rx.cons % NATSEMI_NUM_RX_DESC );
737 rx = &natsemi->rx.desc[rx_idx];
739 /* Stop if descriptor is still in use */
740 if ( ! ( rx->common.cmdsts & NATSEMI_DESC_OWN ) )
743 /* Populate I/O buffer */
744 iobuf = natsemi->rx_iobuf[rx_idx];
745 natsemi->rx_iobuf[rx_idx] = NULL;
746 len = ( le32_to_cpu ( rx->common.cmdsts ) &
747 NATSEMI_DESC_SIZE_MASK );
748 iob_put ( iobuf, len - 4 /* strip CRC */ );
750 /* Hand off to network stack */
751 if ( rx->common.cmdsts & cpu_to_le32 ( NATSEMI_DESC_OK ) ) {
752 DBGC2 ( natsemi, "NATSEMI %p RX %d complete (length "
753 "%zd)\n", natsemi, rx_idx, len );
754 netdev_rx ( netdev, iobuf );
756 DBGC ( natsemi, "NATSEMI %p RX %d error (length %zd, "
757 "status %08x)\n", natsemi, rx_idx, len,
758 le32_to_cpu ( rx->common.cmdsts ) );
759 netdev_rx_err ( netdev, iobuf, -EIO );
766 * Poll for completed and received packets
768 * @v netdev Network device
770 static void natsemi_poll ( struct net_device *netdev ) {
771 struct natsemi_nic *natsemi = netdev->priv;
774 /* Poll for link state. The PHY interrupt seems not to
775 * function as expected, and polling for the link state is
776 * only a single register read.
778 natsemi_check_link ( netdev );
780 /* Check for and acknowledge interrupts */
781 isr = readl ( natsemi->regs + NATSEMI_ISR );
785 /* Poll for TX completions, if applicable */
786 if ( isr & NATSEMI_IRQ_TXDESC )
787 natsemi_poll_tx ( netdev );
789 /* Poll for RX completionsm, if applicable */
790 if ( isr & NATSEMI_IRQ_RXDESC )
791 natsemi_poll_rx ( netdev );
794 natsemi_refill_rx ( netdev );
798 * Enable or disable interrupts
800 * @v netdev Network device
801 * @v enable Interrupts should be enabled
803 static void natsemi_irq ( struct net_device *netdev, int enable ) {
804 struct natsemi_nic *natsemi = netdev->priv;
806 /* Enable or disable interrupts */
807 writel ( ( enable ? NATSEMI_IER_IE : 0 ), natsemi->regs + NATSEMI_IER );
810 /** National Semiconductor network device operations */
811 static struct net_device_operations natsemi_operations = {
812 .open = natsemi_open,
813 .close = natsemi_close,
814 .transmit = natsemi_transmit,
815 .poll = natsemi_poll,
819 /******************************************************************************
823 ******************************************************************************
830 * @ret rc Return status code
832 static int natsemi_probe ( struct pci_device *pci ) {
833 struct net_device *netdev;
834 struct natsemi_nic *natsemi;
837 /* Allocate and initialise net device */
838 netdev = alloc_etherdev ( sizeof ( *natsemi ) );
843 netdev_init ( netdev, &natsemi_operations );
844 natsemi = netdev->priv;
845 pci_set_drvdata ( pci, netdev );
846 netdev->dev = &pci->dev;
847 memset ( natsemi, 0, sizeof ( *natsemi ) );
848 natsemi->flags = pci->id->driver_data;
849 natsemi_init_ring ( &natsemi->tx, NATSEMI_NUM_TX_DESC, NATSEMI_TXDP );
850 natsemi_init_ring ( &natsemi->rx, NATSEMI_NUM_RX_DESC, NATSEMI_RXDP );
852 /* Fix up PCI device */
853 adjust_pci_device ( pci );
856 natsemi->regs = ioremap ( pci->membase, NATSEMI_BAR_SIZE );
857 if ( ! natsemi->regs ) {
863 if ( ( rc = natsemi_reset ( natsemi ) ) != 0 )
866 /* Initialise EEPROM */
867 natsemi_init_eeprom ( natsemi );
869 /* Read initial MAC address */
870 if ( ( rc = natsemi_hwaddr ( natsemi, netdev->hw_addr ) ) != 0 )
873 /* Register network device */
874 if ( ( rc = register_netdev ( netdev ) ) != 0 )
875 goto err_register_netdev;
877 /* Set initial link state */
878 natsemi_check_link ( netdev );
882 unregister_netdev ( netdev );
885 natsemi_reset ( natsemi );
887 iounmap ( natsemi->regs );
889 netdev_nullify ( netdev );
890 netdev_put ( netdev );
900 static void natsemi_remove ( struct pci_device *pci ) {
901 struct net_device *netdev = pci_get_drvdata ( pci );
902 struct natsemi_nic *natsemi = netdev->priv;
904 /* Unregister network device */
905 unregister_netdev ( netdev );
908 natsemi_reset ( natsemi );
910 /* Free network device */
911 iounmap ( natsemi->regs );
912 netdev_nullify ( netdev );
913 netdev_put ( netdev );
916 /** Flags for DP83815 */
917 #define DP83815_FLAGS ( NATSEMI_EEPROM_LITTLE_ENDIAN | NATSEMI_EEPROM_INSANE )
919 /** Flags for DP83820 */
920 #define DP83820_FLAGS ( NATSEMI_64BIT | NATSEMI_1000 )
922 /** National Semiconductor PCI device IDs */
923 static struct pci_device_id natsemi_nics[] = {
924 PCI_ROM ( 0x100b, 0x0020, "dp83815", "DP83815", DP83815_FLAGS ),
925 PCI_ROM ( 0x100b, 0x0022, "dp83820", "DP83820", DP83820_FLAGS ),
928 /** National Semiconductor PCI driver */
929 struct pci_driver natsemi_driver __pci_driver = {
931 .id_count = ( sizeof ( natsemi_nics ) / sizeof ( natsemi_nics[0] ) ),
932 .probe = natsemi_probe,
933 .remove = natsemi_remove,