2 * Copyright (C) 2012 Michael Brown <mbrown@fensystems.co.uk>.
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License as
6 * published by the Free Software Foundation; either version 2 of the
7 * License, or (at your option) any later version.
9 * This program is distributed in the hope that it will be useful, but
10 * WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
12 * General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, write to the Free Software
16 * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA
19 * You can also choose to distribute this program under the terms of
20 * the Unmodified Binary Distribution Licence (as given in the file
21 * COPYING.UBDL), provided that you have satisfied its requirements.
24 FILE_LICENCE ( GPL2_OR_LATER_OR_UBDL );
31 #include <ipxe/netdevice.h>
32 #include <ipxe/ethernet.h>
33 #include <ipxe/if_ether.h>
34 #include <ipxe/iobuf.h>
35 #include <ipxe/malloc.h>
37 #include <ipxe/profile.h>
42 * Intel 10/100/1000 network card driver
46 /** VM transmit profiler */
47 static struct profiler intel_vm_tx_profiler __profiler =
48 { .name = "intel.vm_tx" };
50 /** VM receive refill profiler */
51 static struct profiler intel_vm_refill_profiler __profiler =
52 { .name = "intel.vm_refill" };
54 /** VM poll profiler */
55 static struct profiler intel_vm_poll_profiler __profiler =
56 { .name = "intel.vm_poll" };
58 /******************************************************************************
62 ******************************************************************************
66 * Read data from EEPROM
69 * @v address Address from which to read
71 * @v len Length of data buffer
72 * @ret rc Return status code
74 static int intel_read_eeprom ( struct nvs_device *nvs, unsigned int address,
75 void *data, size_t len ) {
76 struct intel_nic *intel =
77 container_of ( nvs, struct intel_nic, eeprom );
80 uint16_t *data_word = data;
82 /* Sanity check. We advertise a blocksize of one word, so
83 * should only ever receive single-word requests.
85 assert ( len == sizeof ( *data_word ) );
88 writel ( ( INTEL_EERD_START | ( address << intel->eerd_addr_shift ) ),
89 intel->regs + INTEL_EERD );
91 /* Wait for read to complete */
92 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
94 /* If read is not complete, delay 1ms and retry */
95 value = readl ( intel->regs + INTEL_EERD );
96 if ( ! ( value & intel->eerd_done ) ) {
102 *data_word = cpu_to_le16 ( INTEL_EERD_DATA ( value ) );
106 DBGC ( intel, "INTEL %p timed out waiting for EEPROM read\n", intel );
111 * Write data to EEPROM
114 * @v address Address to which to write
115 * @v data Data buffer
116 * @v len Length of data buffer
117 * @ret rc Return status code
119 static int intel_write_eeprom ( struct nvs_device *nvs,
120 unsigned int address __unused,
121 const void *data __unused,
122 size_t len __unused ) {
123 struct intel_nic *intel =
124 container_of ( nvs, struct intel_nic, eeprom );
126 DBGC ( intel, "INTEL %p EEPROM write not supported\n", intel );
133 * @v intel Intel device
134 * @ret rc Return status code
136 static int intel_init_eeprom ( struct intel_nic *intel ) {
140 /* The NIC automatically detects the type of attached EEPROM.
141 * The EERD register provides access to only a single word at
142 * a time, so we pretend to have a single-word block size.
144 * The EEPROM size may be larger than the minimum size, but
145 * this doesn't matter to us since we access only the first
148 intel->eeprom.word_len_log2 = INTEL_EEPROM_WORD_LEN_LOG2;
149 intel->eeprom.size = INTEL_EEPROM_MIN_SIZE_WORDS;
150 intel->eeprom.block_size = 1;
151 intel->eeprom.read = intel_read_eeprom;
152 intel->eeprom.write = intel_write_eeprom;
154 /* The layout of the EERD register was changed at some point
155 * to accommodate larger EEPROMs. Read from address zero (for
156 * which the request layouts are compatible) to determine
157 * which type of register we have.
159 writel ( INTEL_EERD_START, intel->regs + INTEL_EERD );
160 for ( i = 0 ; i < INTEL_EEPROM_MAX_WAIT_MS ; i++ ) {
161 value = readl ( intel->regs + INTEL_EERD );
162 if ( value & INTEL_EERD_DONE_LARGE ) {
163 DBGC ( intel, "INTEL %p has large-format EERD\n",
165 intel->eerd_done = INTEL_EERD_DONE_LARGE;
166 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_LARGE;
169 if ( value & INTEL_EERD_DONE_SMALL ) {
170 DBGC ( intel, "INTEL %p has small-format EERD\n",
172 intel->eerd_done = INTEL_EERD_DONE_SMALL;
173 intel->eerd_addr_shift = INTEL_EERD_ADDR_SHIFT_SMALL;
179 DBGC ( intel, "INTEL %p timed out waiting for initial EEPROM read "
180 "(value %08x)\n", intel, value );
184 /******************************************************************************
188 ******************************************************************************
192 * Fetch initial MAC address from EEPROM
194 * @v intel Intel device
195 * @v hw_addr Hardware address to fill in
196 * @ret rc Return status code
198 static int intel_fetch_mac_eeprom ( struct intel_nic *intel,
202 /* Initialise EEPROM */
203 if ( ( rc = intel_init_eeprom ( intel ) ) != 0 )
206 /* Read base MAC address from EEPROM */
207 if ( ( rc = nvs_read ( &intel->eeprom, INTEL_EEPROM_MAC,
208 hw_addr, ETH_ALEN ) ) != 0 ) {
209 DBGC ( intel, "INTEL %p could not read EEPROM base MAC "
210 "address: %s\n", intel, strerror ( rc ) );
214 /* Adjust MAC address for multi-port devices */
215 hw_addr[ETH_ALEN-1] ^= intel->port;
217 DBGC ( intel, "INTEL %p has EEPROM MAC address %s (port %d)\n",
218 intel, eth_ntoa ( hw_addr ), intel->port );
223 * Fetch initial MAC address
225 * @v intel Intel device
226 * @v hw_addr Hardware address to fill in
227 * @ret rc Return status code
229 static int intel_fetch_mac ( struct intel_nic *intel, uint8_t *hw_addr ) {
230 union intel_receive_address mac;
233 /* Read current address from RAL0/RAH0 */
234 mac.reg.low = cpu_to_le32 ( readl ( intel->regs + INTEL_RAL0 ) );
235 mac.reg.high = cpu_to_le32 ( readl ( intel->regs + INTEL_RAH0 ) );
236 DBGC ( intel, "INTEL %p has autoloaded MAC address %s\n",
237 intel, eth_ntoa ( mac.raw ) );
239 /* Use current address if valid */
240 if ( is_valid_ether_addr ( mac.raw ) ) {
241 memcpy ( hw_addr, mac.raw, ETH_ALEN );
245 /* Otherwise, try to read address from EEPROM */
246 if ( ( rc = intel_fetch_mac_eeprom ( intel, hw_addr ) ) == 0 )
249 DBGC ( intel, "INTEL %p has no MAC address to use\n", intel );
253 /******************************************************************************
257 ******************************************************************************
263 * @v intel Intel device
264 * @ret rc Return status code
266 static int intel_reset ( struct intel_nic *intel ) {
272 /* Force RX and TX packet buffer allocation, to work around an
273 * errata in ICH devices.
275 if ( intel->flags & INTEL_PBS_ERRATA ) {
276 DBGC ( intel, "INTEL %p WARNING: applying ICH PBS/PBA errata\n",
278 pbs = readl ( intel->regs + INTEL_PBS );
279 pba = readl ( intel->regs + INTEL_PBA );
280 writel ( 0x08, intel->regs + INTEL_PBA );
281 writel ( 0x10, intel->regs + INTEL_PBS );
282 DBGC ( intel, "INTEL %p PBS %#08x->%#08x PBA %#08x->%#08x\n",
283 intel, pbs, readl ( intel->regs + INTEL_PBS ),
284 pba, readl ( intel->regs + INTEL_PBA ) );
287 /* Always reset MAC. Required to reset the TX and RX rings. */
288 ctrl = readl ( intel->regs + INTEL_CTRL );
289 writel ( ( ctrl | INTEL_CTRL_RST ), intel->regs + INTEL_CTRL );
290 mdelay ( INTEL_RESET_DELAY_MS );
292 /* Set a sensible default configuration */
293 ctrl |= ( INTEL_CTRL_SLU | INTEL_CTRL_ASDE );
294 ctrl &= ~( INTEL_CTRL_LRST | INTEL_CTRL_FRCSPD | INTEL_CTRL_FRCDPLX );
295 writel ( ctrl, intel->regs + INTEL_CTRL );
296 mdelay ( INTEL_RESET_DELAY_MS );
298 /* If link is already up, do not attempt to reset the PHY. On
299 * some models (notably ICH), performing a PHY reset seems to
300 * drop the link speed to 10Mbps.
302 status = readl ( intel->regs + INTEL_STATUS );
303 if ( status & INTEL_STATUS_LU ) {
304 DBGC ( intel, "INTEL %p MAC reset (ctrl %08x)\n",
309 /* Reset PHY and MAC simultaneously */
310 writel ( ( ctrl | INTEL_CTRL_RST | INTEL_CTRL_PHY_RST ),
311 intel->regs + INTEL_CTRL );
312 mdelay ( INTEL_RESET_DELAY_MS );
314 /* PHY reset is not self-clearing on all models */
315 writel ( ctrl, intel->regs + INTEL_CTRL );
316 mdelay ( INTEL_RESET_DELAY_MS );
318 DBGC ( intel, "INTEL %p MAC+PHY reset (ctrl %08x)\n", intel, ctrl );
322 /******************************************************************************
326 ******************************************************************************
332 * @v netdev Network device
334 static void intel_check_link ( struct net_device *netdev ) {
335 struct intel_nic *intel = netdev->priv;
338 /* Read link status */
339 status = readl ( intel->regs + INTEL_STATUS );
340 DBGC ( intel, "INTEL %p link status is %08x\n", intel, status );
342 /* Update network device */
343 if ( status & INTEL_STATUS_LU ) {
344 netdev_link_up ( netdev );
346 netdev_link_down ( netdev );
350 /******************************************************************************
354 ******************************************************************************
358 * Populate transmit descriptor
360 * @v tx Transmit descriptor
361 * @v addr Data buffer address
362 * @v len Length of data
364 void intel_describe_tx ( struct intel_descriptor *tx, physaddr_t addr,
367 /* Populate transmit descriptor */
368 tx->address = cpu_to_le64 ( addr );
369 tx->length = cpu_to_le16 ( len );
371 tx->command = ( INTEL_DESC_CMD_RS | INTEL_DESC_CMD_IFCS |
372 INTEL_DESC_CMD_EOP );
377 * Populate advanced transmit descriptor
379 * @v tx Transmit descriptor
380 * @v addr Data buffer address
381 * @v len Length of data
383 void intel_describe_tx_adv ( struct intel_descriptor *tx, physaddr_t addr,
386 /* Populate advanced transmit descriptor */
387 tx->address = cpu_to_le64 ( addr );
388 tx->length = cpu_to_le16 ( len );
389 tx->flags = INTEL_DESC_FL_DTYP_DATA;
390 tx->command = ( INTEL_DESC_CMD_DEXT | INTEL_DESC_CMD_RS |
391 INTEL_DESC_CMD_IFCS | INTEL_DESC_CMD_EOP );
392 tx->status = cpu_to_le32 ( INTEL_DESC_STATUS_PAYLEN ( len ) );
396 * Populate receive descriptor
398 * @v rx Receive descriptor
399 * @v addr Data buffer address
400 * @v len Length of data
402 void intel_describe_rx ( struct intel_descriptor *rx, physaddr_t addr,
403 size_t len __unused ) {
405 /* Populate transmit descriptor */
406 rx->address = cpu_to_le64 ( addr );
411 /******************************************************************************
413 * Network device interface
415 ******************************************************************************
419 * Create descriptor ring
421 * @v intel Intel device
422 * @v ring Descriptor ring
423 * @ret rc Return status code
425 int intel_create_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
429 /* Allocate descriptor ring. Align ring on its own size to
430 * prevent any possible page-crossing errors due to hardware
433 ring->desc = malloc_dma ( ring->len, ring->len );
437 /* Initialise descriptor ring */
438 memset ( ring->desc, 0, ring->len );
440 /* Program ring address */
441 address = virt_to_bus ( ring->desc );
442 writel ( ( address & 0xffffffffUL ),
443 ( intel->regs + ring->reg + INTEL_xDBAL ) );
444 if ( sizeof ( physaddr_t ) > sizeof ( uint32_t ) ) {
445 writel ( ( ( ( uint64_t ) address ) >> 32 ),
446 ( intel->regs + ring->reg + INTEL_xDBAH ) );
448 writel ( 0, intel->regs + ring->reg + INTEL_xDBAH );
451 /* Program ring length */
452 writel ( ring->len, ( intel->regs + ring->reg + INTEL_xDLEN ) );
454 /* Reset head and tail pointers */
455 writel ( 0, ( intel->regs + ring->reg + INTEL_xDH ) );
456 writel ( 0, ( intel->regs + ring->reg + INTEL_xDT ) );
459 dctl = readl ( intel->regs + ring->reg + INTEL_xDCTL );
460 dctl |= INTEL_xDCTL_ENABLE;
461 writel ( dctl, intel->regs + ring->reg + INTEL_xDCTL );
463 DBGC ( intel, "INTEL %p ring %05x is at [%08llx,%08llx)\n",
464 intel, ring->reg, ( ( unsigned long long ) address ),
465 ( ( unsigned long long ) address + ring->len ) );
471 * Destroy descriptor ring
473 * @v intel Intel device
474 * @v ring Descriptor ring
476 void intel_destroy_ring ( struct intel_nic *intel, struct intel_ring *ring ) {
478 /* Clear ring length */
479 writel ( 0, ( intel->regs + ring->reg + INTEL_xDLEN ) );
481 /* Clear ring address */
482 writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAL ) );
483 writel ( 0, ( intel->regs + ring->reg + INTEL_xDBAH ) );
485 /* Free descriptor ring */
486 free_dma ( ring->desc, ring->len );
493 * Refill receive descriptor ring
495 * @v intel Intel device
497 void intel_refill_rx ( struct intel_nic *intel ) {
498 struct intel_descriptor *rx;
499 struct io_buffer *iobuf;
501 unsigned int rx_tail;
503 unsigned int refilled = 0;
506 while ( ( intel->rx.prod - intel->rx.cons ) < INTEL_RX_FILL ) {
508 /* Allocate I/O buffer */
509 iobuf = alloc_iob ( INTEL_RX_MAX_LEN );
511 /* Wait for next refill */
515 /* Get next receive descriptor */
516 rx_idx = ( intel->rx.prod++ % INTEL_NUM_RX_DESC );
517 rx = &intel->rx.desc[rx_idx];
519 /* Populate receive descriptor */
520 address = virt_to_bus ( iobuf->data );
521 intel->rx.describe ( rx, address, 0 );
523 /* Record I/O buffer */
524 assert ( intel->rx_iobuf[rx_idx] == NULL );
525 intel->rx_iobuf[rx_idx] = iobuf;
527 DBGC2 ( intel, "INTEL %p RX %d is [%llx,%llx)\n", intel, rx_idx,
528 ( ( unsigned long long ) address ),
529 ( ( unsigned long long ) address + INTEL_RX_MAX_LEN ) );
533 /* Push descriptors to card, if applicable */
536 rx_tail = ( intel->rx.prod % INTEL_NUM_RX_DESC );
537 profile_start ( &intel_vm_refill_profiler );
538 writel ( rx_tail, intel->regs + intel->rx.reg + INTEL_xDT );
539 profile_stop ( &intel_vm_refill_profiler );
540 profile_exclude ( &intel_vm_refill_profiler );
545 * Discard unused receive I/O buffers
547 * @v intel Intel device
549 void intel_empty_rx ( struct intel_nic *intel ) {
552 for ( i = 0 ; i < INTEL_NUM_RX_DESC ; i++ ) {
553 if ( intel->rx_iobuf[i] )
554 free_iob ( intel->rx_iobuf[i] );
555 intel->rx_iobuf[i] = NULL;
560 * Open network device
562 * @v netdev Network device
563 * @ret rc Return status code
565 static int intel_open ( struct net_device *netdev ) {
566 struct intel_nic *intel = netdev->priv;
567 union intel_receive_address mac;
572 /* Create transmit descriptor ring */
573 if ( ( rc = intel_create_ring ( intel, &intel->tx ) ) != 0 )
576 /* Create receive descriptor ring */
577 if ( ( rc = intel_create_ring ( intel, &intel->rx ) ) != 0 )
580 /* Program MAC address */
581 memset ( &mac, 0, sizeof ( mac ) );
582 memcpy ( mac.raw, netdev->ll_addr, sizeof ( mac.raw ) );
583 writel ( le32_to_cpu ( mac.reg.low ), intel->regs + INTEL_RAL0 );
584 writel ( ( le32_to_cpu ( mac.reg.high ) | INTEL_RAH0_AV ),
585 intel->regs + INTEL_RAH0 );
587 /* Enable transmitter */
588 tctl = readl ( intel->regs + INTEL_TCTL );
589 tctl &= ~( INTEL_TCTL_CT_MASK | INTEL_TCTL_COLD_MASK );
590 tctl |= ( INTEL_TCTL_EN | INTEL_TCTL_PSP | INTEL_TCTL_CT_DEFAULT |
591 INTEL_TCTL_COLD_DEFAULT );
592 writel ( tctl, intel->regs + INTEL_TCTL );
594 /* Enable receiver */
595 rctl = readl ( intel->regs + INTEL_RCTL );
596 rctl &= ~( INTEL_RCTL_BSIZE_BSEX_MASK );
597 rctl |= ( INTEL_RCTL_EN | INTEL_RCTL_UPE | INTEL_RCTL_MPE |
598 INTEL_RCTL_BAM | INTEL_RCTL_BSIZE_2048 | INTEL_RCTL_SECRC );
599 writel ( rctl, intel->regs + INTEL_RCTL );
601 /* Fill receive ring */
602 intel_refill_rx ( intel );
604 /* Update link state */
605 intel_check_link ( netdev );
607 /* Apply required errata */
608 if ( intel->flags & INTEL_VMWARE ) {
609 DBGC ( intel, "INTEL %p applying VMware errata workaround\n",
611 intel->force_icr = INTEL_IRQ_RXT0;
616 intel_destroy_ring ( intel, &intel->rx );
618 intel_destroy_ring ( intel, &intel->tx );
624 * Close network device
626 * @v netdev Network device
628 static void intel_close ( struct net_device *netdev ) {
629 struct intel_nic *intel = netdev->priv;
631 /* Disable receiver */
632 writel ( 0, intel->regs + INTEL_RCTL );
634 /* Disable transmitter */
635 writel ( 0, intel->regs + INTEL_TCTL );
637 /* Destroy receive descriptor ring */
638 intel_destroy_ring ( intel, &intel->rx );
640 /* Discard any unused receive buffers */
641 intel_empty_rx ( intel );
643 /* Destroy transmit descriptor ring */
644 intel_destroy_ring ( intel, &intel->tx );
646 /* Reset the NIC, to flush the transmit and receive FIFOs */
647 intel_reset ( intel );
653 * @v netdev Network device
654 * @v iobuf I/O buffer
655 * @ret rc Return status code
657 int intel_transmit ( struct net_device *netdev, struct io_buffer *iobuf ) {
658 struct intel_nic *intel = netdev->priv;
659 struct intel_descriptor *tx;
661 unsigned int tx_tail;
665 /* Get next transmit descriptor */
666 if ( ( intel->tx.prod - intel->tx.cons ) >= INTEL_TX_FILL ) {
667 DBGC ( intel, "INTEL %p out of transmit descriptors\n", intel );
670 tx_idx = ( intel->tx.prod++ % INTEL_NUM_TX_DESC );
671 tx_tail = ( intel->tx.prod % INTEL_NUM_TX_DESC );
672 tx = &intel->tx.desc[tx_idx];
674 /* Populate transmit descriptor */
675 address = virt_to_bus ( iobuf->data );
676 len = iob_len ( iobuf );
677 intel->tx.describe ( tx, address, len );
680 /* Notify card that there are packets ready to transmit */
681 profile_start ( &intel_vm_tx_profiler );
682 writel ( tx_tail, intel->regs + intel->tx.reg + INTEL_xDT );
683 profile_stop ( &intel_vm_tx_profiler );
684 profile_exclude ( &intel_vm_tx_profiler );
686 DBGC2 ( intel, "INTEL %p TX %d is [%llx,%llx)\n", intel, tx_idx,
687 ( ( unsigned long long ) address ),
688 ( ( unsigned long long ) address + len ) );
694 * Poll for completed packets
696 * @v netdev Network device
698 void intel_poll_tx ( struct net_device *netdev ) {
699 struct intel_nic *intel = netdev->priv;
700 struct intel_descriptor *tx;
703 /* Check for completed packets */
704 while ( intel->tx.cons != intel->tx.prod ) {
706 /* Get next transmit descriptor */
707 tx_idx = ( intel->tx.cons % INTEL_NUM_TX_DESC );
708 tx = &intel->tx.desc[tx_idx];
710 /* Stop if descriptor is still in use */
711 if ( ! ( tx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
714 DBGC2 ( intel, "INTEL %p TX %d complete\n", intel, tx_idx );
716 /* Complete TX descriptor */
717 netdev_tx_complete_next ( netdev );
723 * Poll for received packets
725 * @v netdev Network device
727 void intel_poll_rx ( struct net_device *netdev ) {
728 struct intel_nic *intel = netdev->priv;
729 struct intel_descriptor *rx;
730 struct io_buffer *iobuf;
734 /* Check for received packets */
735 while ( intel->rx.cons != intel->rx.prod ) {
737 /* Get next receive descriptor */
738 rx_idx = ( intel->rx.cons % INTEL_NUM_RX_DESC );
739 rx = &intel->rx.desc[rx_idx];
741 /* Stop if descriptor is still in use */
742 if ( ! ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_DD ) ) )
745 /* Populate I/O buffer */
746 iobuf = intel->rx_iobuf[rx_idx];
747 intel->rx_iobuf[rx_idx] = NULL;
748 len = le16_to_cpu ( rx->length );
749 iob_put ( iobuf, len );
751 /* Hand off to network stack */
752 if ( rx->status & cpu_to_le32 ( INTEL_DESC_STATUS_RXE ) ) {
753 DBGC ( intel, "INTEL %p RX %d error (length %zd, "
754 "status %08x)\n", intel, rx_idx, len,
755 le32_to_cpu ( rx->status ) );
756 netdev_rx_err ( netdev, iobuf, -EIO );
758 DBGC2 ( intel, "INTEL %p RX %d complete (length %zd)\n",
759 intel, rx_idx, len );
760 netdev_rx ( netdev, iobuf );
767 * Poll for completed and received packets
769 * @v netdev Network device
771 static void intel_poll ( struct net_device *netdev ) {
772 struct intel_nic *intel = netdev->priv;
775 /* Check for and acknowledge interrupts */
776 profile_start ( &intel_vm_poll_profiler );
777 icr = readl ( intel->regs + INTEL_ICR );
778 profile_stop ( &intel_vm_poll_profiler );
779 profile_exclude ( &intel_vm_poll_profiler );
780 icr |= intel->force_icr;
784 /* Poll for TX completions, if applicable */
785 if ( icr & INTEL_IRQ_TXDW )
786 intel_poll_tx ( netdev );
788 /* Poll for RX completions, if applicable */
789 if ( icr & ( INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) )
790 intel_poll_rx ( netdev );
792 /* Report receive overruns */
793 if ( icr & INTEL_IRQ_RXO )
794 netdev_rx_err ( netdev, NULL, -ENOBUFS );
796 /* Check link state, if applicable */
797 if ( icr & INTEL_IRQ_LSC )
798 intel_check_link ( netdev );
800 /* Check for unexpected interrupts */
801 if ( icr & ~( INTEL_IRQ_TXDW | INTEL_IRQ_TXQE | INTEL_IRQ_LSC |
802 INTEL_IRQ_RXDMT0 | INTEL_IRQ_RXT0 | INTEL_IRQ_RXO ) ) {
803 DBGC ( intel, "INTEL %p unexpected ICR %08x\n", intel, icr );
804 /* Report as a TX error */
805 netdev_tx_err ( netdev, NULL, -ENOTSUP );
809 intel_refill_rx ( intel );
813 * Enable or disable interrupts
815 * @v netdev Network device
816 * @v enable Interrupts should be enabled
818 static void intel_irq ( struct net_device *netdev, int enable ) {
819 struct intel_nic *intel = netdev->priv;
822 mask = ( INTEL_IRQ_TXDW | INTEL_IRQ_LSC | INTEL_IRQ_RXT0 );
824 writel ( mask, intel->regs + INTEL_IMS );
826 writel ( mask, intel->regs + INTEL_IMC );
830 /** Intel network device operations */
831 static struct net_device_operations intel_operations = {
833 .close = intel_close,
834 .transmit = intel_transmit,
839 /******************************************************************************
843 ******************************************************************************
850 * @ret rc Return status code
852 static int intel_probe ( struct pci_device *pci ) {
853 struct net_device *netdev;
854 struct intel_nic *intel;
857 /* Allocate and initialise net device */
858 netdev = alloc_etherdev ( sizeof ( *intel ) );
863 netdev_init ( netdev, &intel_operations );
864 intel = netdev->priv;
865 pci_set_drvdata ( pci, netdev );
866 netdev->dev = &pci->dev;
867 memset ( intel, 0, sizeof ( *intel ) );
868 intel->port = PCI_FUNC ( pci->busdevfn );
869 intel->flags = pci->id->driver_data;
870 intel_init_ring ( &intel->tx, INTEL_NUM_TX_DESC, INTEL_TD,
872 intel_init_ring ( &intel->rx, INTEL_NUM_RX_DESC, INTEL_RD,
875 /* Fix up PCI device */
876 adjust_pci_device ( pci );
879 intel->regs = ioremap ( pci->membase, INTEL_BAR_SIZE );
880 if ( ! intel->regs ) {
886 if ( ( rc = intel_reset ( intel ) ) != 0 )
889 /* Fetch MAC address */
890 if ( ( rc = intel_fetch_mac ( intel, netdev->hw_addr ) ) != 0 )
893 /* Register network device */
894 if ( ( rc = register_netdev ( netdev ) ) != 0 )
895 goto err_register_netdev;
897 /* Set initial link state */
898 intel_check_link ( netdev );
902 unregister_netdev ( netdev );
905 intel_reset ( intel );
907 iounmap ( intel->regs );
909 netdev_nullify ( netdev );
910 netdev_put ( netdev );
920 static void intel_remove ( struct pci_device *pci ) {
921 struct net_device *netdev = pci_get_drvdata ( pci );
922 struct intel_nic *intel = netdev->priv;
924 /* Unregister network device */
925 unregister_netdev ( netdev );
928 intel_reset ( intel );
930 /* Free network device */
931 iounmap ( intel->regs );
932 netdev_nullify ( netdev );
933 netdev_put ( netdev );
936 /** Intel PCI device IDs */
937 static struct pci_device_id intel_nics[] = {
938 PCI_ROM ( 0x8086, 0x0438, "dh8900cc", "DH8900CC", 0 ),
939 PCI_ROM ( 0x8086, 0x043a, "dh8900cc-f", "DH8900CC Fiber", 0 ),
940 PCI_ROM ( 0x8086, 0x043c, "dh8900cc-b", "DH8900CC Backplane", 0 ),
941 PCI_ROM ( 0x8086, 0x0440, "dh8900cc-s", "DH8900CC SFP", 0 ),
942 PCI_ROM ( 0x8086, 0x1000, "82542-f", "82542 (Fiber)", 0 ),
943 PCI_ROM ( 0x8086, 0x1001, "82543gc-f", "82543GC (Fiber)", 0 ),
944 PCI_ROM ( 0x8086, 0x1004, "82543gc", "82543GC (Copper)", 0 ),
945 PCI_ROM ( 0x8086, 0x1008, "82544ei", "82544EI (Copper)", 0 ),
946 PCI_ROM ( 0x8086, 0x1009, "82544ei-f", "82544EI (Fiber)", 0 ),
947 PCI_ROM ( 0x8086, 0x100c, "82544gc", "82544GC (Copper)", 0 ),
948 PCI_ROM ( 0x8086, 0x100d, "82544gc-l", "82544GC (LOM)", 0 ),
949 PCI_ROM ( 0x8086, 0x100e, "82540em", "82540EM", 0 ),
950 PCI_ROM ( 0x8086, 0x100f, "82545em", "82545EM (Copper)", INTEL_VMWARE ),
951 PCI_ROM ( 0x8086, 0x1010, "82546eb", "82546EB (Copper)", 0 ),
952 PCI_ROM ( 0x8086, 0x1011, "82545em-f", "82545EM (Fiber)", 0 ),
953 PCI_ROM ( 0x8086, 0x1012, "82546eb-f", "82546EB (Fiber)", 0 ),
954 PCI_ROM ( 0x8086, 0x1013, "82541ei", "82541EI", 0 ),
955 PCI_ROM ( 0x8086, 0x1014, "82541er", "82541ER", 0 ),
956 PCI_ROM ( 0x8086, 0x1015, "82540em-l", "82540EM (LOM)", 0 ),
957 PCI_ROM ( 0x8086, 0x1016, "82540ep-m", "82540EP (Mobile)", 0 ),
958 PCI_ROM ( 0x8086, 0x1017, "82540ep", "82540EP", 0 ),
959 PCI_ROM ( 0x8086, 0x1018, "82541ei", "82541EI", 0 ),
960 PCI_ROM ( 0x8086, 0x1019, "82547ei", "82547EI", 0 ),
961 PCI_ROM ( 0x8086, 0x101a, "82547ei-m", "82547EI (Mobile)", 0 ),
962 PCI_ROM ( 0x8086, 0x101d, "82546eb", "82546EB", 0 ),
963 PCI_ROM ( 0x8086, 0x101e, "82540ep-m", "82540EP (Mobile)", 0 ),
964 PCI_ROM ( 0x8086, 0x1026, "82545gm", "82545GM", 0 ),
965 PCI_ROM ( 0x8086, 0x1027, "82545gm-1", "82545GM", 0 ),
966 PCI_ROM ( 0x8086, 0x1028, "82545gm-2", "82545GM", 0 ),
967 PCI_ROM ( 0x8086, 0x1049, "82566mm", "82566MM", INTEL_PBS_ERRATA ),
968 PCI_ROM ( 0x8086, 0x104a, "82566dm", "82566DM", INTEL_PBS_ERRATA ),
969 PCI_ROM ( 0x8086, 0x104b, "82566dc", "82566DC", INTEL_PBS_ERRATA ),
970 PCI_ROM ( 0x8086, 0x104c, "82562v", "82562V", INTEL_PBS_ERRATA ),
971 PCI_ROM ( 0x8086, 0x104d, "82566mc", "82566MC", INTEL_PBS_ERRATA ),
972 PCI_ROM ( 0x8086, 0x105e, "82571eb", "82571EB", 0 ),
973 PCI_ROM ( 0x8086, 0x105f, "82571eb-1", "82571EB", 0 ),
974 PCI_ROM ( 0x8086, 0x1060, "82571eb-2", "82571EB", 0 ),
975 PCI_ROM ( 0x8086, 0x1075, "82547gi", "82547GI", 0 ),
976 PCI_ROM ( 0x8086, 0x1076, "82541gi", "82541GI", 0 ),
977 PCI_ROM ( 0x8086, 0x1077, "82541gi-1", "82541GI", 0 ),
978 PCI_ROM ( 0x8086, 0x1078, "82541er", "82541ER", 0 ),
979 PCI_ROM ( 0x8086, 0x1079, "82546gb", "82546GB", 0 ),
980 PCI_ROM ( 0x8086, 0x107a, "82546gb-1", "82546GB", 0 ),
981 PCI_ROM ( 0x8086, 0x107b, "82546gb-2", "82546GB", 0 ),
982 PCI_ROM ( 0x8086, 0x107c, "82541pi", "82541PI", 0 ),
983 PCI_ROM ( 0x8086, 0x107d, "82572ei", "82572EI (Copper)", 0 ),
984 PCI_ROM ( 0x8086, 0x107e, "82572ei-f", "82572EI (Fiber)", 0 ),
985 PCI_ROM ( 0x8086, 0x107f, "82572ei", "82572EI", 0 ),
986 PCI_ROM ( 0x8086, 0x108a, "82546gb-3", "82546GB", 0 ),
987 PCI_ROM ( 0x8086, 0x108b, "82573v", "82573V (Copper)", 0 ),
988 PCI_ROM ( 0x8086, 0x108c, "82573e", "82573E (Copper)", 0 ),
989 PCI_ROM ( 0x8086, 0x1096, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
990 PCI_ROM ( 0x8086, 0x1098, "80003es2lan-s", "80003ES2LAN (Serdes)", 0 ),
991 PCI_ROM ( 0x8086, 0x1099, "82546gb-4", "82546GB (Copper)", 0 ),
992 PCI_ROM ( 0x8086, 0x109a, "82573l", "82573L", 0 ),
993 PCI_ROM ( 0x8086, 0x10a4, "82571eb", "82571EB", 0 ),
994 PCI_ROM ( 0x8086, 0x10a5, "82571eb", "82571EB (Fiber)", 0 ),
995 PCI_ROM ( 0x8086, 0x10a7, "82575eb", "82575EB", 0 ),
996 PCI_ROM ( 0x8086, 0x10a9, "82575eb", "82575EB Backplane", 0 ),
997 PCI_ROM ( 0x8086, 0x10b5, "82546gb", "82546GB (Copper)", 0 ),
998 PCI_ROM ( 0x8086, 0x10b9, "82572ei", "82572EI (Copper)", 0 ),
999 PCI_ROM ( 0x8086, 0x10ba, "80003es2lan", "80003ES2LAN (Copper)", 0 ),
1000 PCI_ROM ( 0x8086, 0x10bb, "80003es2lan", "80003ES2LAN (Serdes)", 0 ),
1001 PCI_ROM ( 0x8086, 0x10bc, "82571eb", "82571EB (Copper)", 0 ),
1002 PCI_ROM ( 0x8086, 0x10bd, "82566dm-2", "82566DM-2", 0 ),
1003 PCI_ROM ( 0x8086, 0x10bf, "82567lf", "82567LF", 0 ),
1004 PCI_ROM ( 0x8086, 0x10c0, "82562v-2", "82562V-2", 0 ),
1005 PCI_ROM ( 0x8086, 0x10c2, "82562g-2", "82562G-2", 0 ),
1006 PCI_ROM ( 0x8086, 0x10c3, "82562gt-2", "82562GT-2", 0 ),
1007 PCI_ROM ( 0x8086, 0x10c4, "82562gt", "82562GT", INTEL_PBS_ERRATA ),
1008 PCI_ROM ( 0x8086, 0x10c5, "82562g", "82562G", INTEL_PBS_ERRATA ),
1009 PCI_ROM ( 0x8086, 0x10c9, "82576", "82576", 0 ),
1010 PCI_ROM ( 0x8086, 0x10cb, "82567v", "82567V", 0 ),
1011 PCI_ROM ( 0x8086, 0x10cc, "82567lm-2", "82567LM-2", 0 ),
1012 PCI_ROM ( 0x8086, 0x10cd, "82567lf-2", "82567LF-2", 0 ),
1013 PCI_ROM ( 0x8086, 0x10ce, "82567v-2", "82567V-2", 0 ),
1014 PCI_ROM ( 0x8086, 0x10d3, "82574l", "82574L", 0 ),
1015 PCI_ROM ( 0x8086, 0x10d5, "82571pt", "82571PT PT Quad", 0 ),
1016 PCI_ROM ( 0x8086, 0x10d6, "82575gb", "82575GB", 0 ),
1017 PCI_ROM ( 0x8086, 0x10d9, "82571eb-d", "82571EB Dual Mezzanine", 0 ),
1018 PCI_ROM ( 0x8086, 0x10da, "82571eb-q", "82571EB Quad Mezzanine", 0 ),
1019 PCI_ROM ( 0x8086, 0x10de, "82567lm-3", "82567LM-3", 0 ),
1020 PCI_ROM ( 0x8086, 0x10df, "82567lf-3", "82567LF-3", 0 ),
1021 PCI_ROM ( 0x8086, 0x10e5, "82567lm-4", "82567LM-4", 0 ),
1022 PCI_ROM ( 0x8086, 0x10e6, "82576", "82576", 0 ),
1023 PCI_ROM ( 0x8086, 0x10e7, "82576-2", "82576", 0 ),
1024 PCI_ROM ( 0x8086, 0x10e8, "82576-3", "82576", 0 ),
1025 PCI_ROM ( 0x8086, 0x10ea, "82577lm", "82577LM", 0 ),
1026 PCI_ROM ( 0x8086, 0x10eb, "82577lc", "82577LC", 0 ),
1027 PCI_ROM ( 0x8086, 0x10ef, "82578dm", "82578DM", 0 ),
1028 PCI_ROM ( 0x8086, 0x10f0, "82578dc", "82578DC", 0 ),
1029 PCI_ROM ( 0x8086, 0x10f5, "82567lm", "82567LM", 0 ),
1030 PCI_ROM ( 0x8086, 0x10f6, "82574l", "82574L", 0 ),
1031 PCI_ROM ( 0x8086, 0x1501, "82567v-3", "82567V-3", INTEL_PBS_ERRATA ),
1032 PCI_ROM ( 0x8086, 0x1502, "82579lm", "82579LM", 0 ),
1033 PCI_ROM ( 0x8086, 0x1503, "82579v", "82579V", 0 ),
1034 PCI_ROM ( 0x8086, 0x150a, "82576ns", "82576NS", 0 ),
1035 PCI_ROM ( 0x8086, 0x150c, "82583v", "82583V", 0 ),
1036 PCI_ROM ( 0x8086, 0x150d, "82576-4", "82576 Backplane", 0 ),
1037 PCI_ROM ( 0x8086, 0x150e, "82580", "82580", 0 ),
1038 PCI_ROM ( 0x8086, 0x150f, "82580-f", "82580 Fiber", 0 ),
1039 PCI_ROM ( 0x8086, 0x1510, "82580-b", "82580 Backplane", 0 ),
1040 PCI_ROM ( 0x8086, 0x1511, "82580-s", "82580 SFP", 0 ),
1041 PCI_ROM ( 0x8086, 0x1516, "82580-2", "82580", 0 ),
1042 PCI_ROM ( 0x8086, 0x1518, "82576ns", "82576NS SerDes", 0 ),
1043 PCI_ROM ( 0x8086, 0x1521, "i350", "I350", 0 ),
1044 PCI_ROM ( 0x8086, 0x1522, "i350-f", "I350 Fiber", 0 ),
1045 PCI_ROM ( 0x8086, 0x1523, "i350-b", "I350 Backplane", 0 ),
1046 PCI_ROM ( 0x8086, 0x1524, "i350-2", "I350", 0 ),
1047 PCI_ROM ( 0x8086, 0x1525, "82567v-4", "82567V-4", 0 ),
1048 PCI_ROM ( 0x8086, 0x1526, "82576-5", "82576", 0 ),
1049 PCI_ROM ( 0x8086, 0x1527, "82580-f2", "82580 Fiber", 0 ),
1050 PCI_ROM ( 0x8086, 0x1533, "i210", "I210", 0 ),
1051 PCI_ROM ( 0x8086, 0x153a, "i217lm", "I217-LM", 0 ),
1052 PCI_ROM ( 0x8086, 0x153b, "i217v", "I217-V", 0 ),
1053 PCI_ROM ( 0x8086, 0x1559, "i218v", "I218-V", 0),
1054 PCI_ROM ( 0x8086, 0x155a, "i218lm", "I218-LM", 0),
1055 PCI_ROM ( 0x8086, 0x15a0, "i218lm-2", "I218-LM", 0 ),
1056 PCI_ROM ( 0x8086, 0x15a1, "i218v-2", "I218-V", 0 ),
1057 PCI_ROM ( 0x8086, 0x15a2, "i218lm-3", "I218-LM", 0 ),
1058 PCI_ROM ( 0x8086, 0x15a3, "i218v-3", "I218-V", 0 ),
1059 PCI_ROM ( 0x8086, 0x294c, "82566dc-2", "82566DC-2", 0 ),
1060 PCI_ROM ( 0x8086, 0x2e6e, "cemedia", "CE Media Processor", 0 ),
1063 /** Intel PCI driver */
1064 struct pci_driver intel_driver __pci_driver = {
1066 .id_count = ( sizeof ( intel_nics ) / sizeof ( intel_nics[0] ) ),
1067 .probe = intel_probe,
1068 .remove = intel_remove,