1 /*******************************************************************************
3 Intel(R) 82576 Virtual Function Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 FILE_LICENCE ( GPL2_ONLY );
43 #include <ipxe/malloc.h>
44 #include <ipxe/if_ether.h>
46 #include <ipxe/ethernet.h>
47 #include <ipxe/iobuf.h>
48 #include <ipxe/netdevice.h>
50 #include "igbvf_osdep.h"
51 #include "igbvf_regs.h"
52 #include "igbvf_defines.h"
56 #define E1000_DEV_ID_82576_VF 0x10CA
57 #define E1000_DEV_ID_I350_VF 0x1520
59 #define E1000_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */
61 /* Additional Descriptor Control definitions */
62 #define E1000_TXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Tx Queue */
63 #define E1000_RXDCTL_QUEUE_ENABLE 0x02000000 /* Enable specific Rx Queue */
65 /* SRRCTL bit definitions */
66 #define E1000_SRRCTL_BSIZEPKT_SHIFT 10 /* Shift _right_ */
67 #define E1000_SRRCTL_BSIZEHDRSIZE_MASK 0x00000F00
68 #define E1000_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* Shift _left_ */
69 #define E1000_SRRCTL_DESCTYPE_LEGACY 0x00000000
70 #define E1000_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000
71 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000
72 #define E1000_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000
73 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION 0x06000000
74 #define E1000_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000
75 #define E1000_SRRCTL_DESCTYPE_MASK 0x0E000000
76 #define E1000_SRRCTL_DROP_EN 0x80000000
78 #define E1000_SRRCTL_BSIZEPKT_MASK 0x0000007F
79 #define E1000_SRRCTL_BSIZEHDR_MASK 0x00003F00
81 /* Interrupt Defines */
82 #define E1000_EICR 0x01580 /* Ext. Interrupt Cause Read - R/clr */
83 #define E1000_EITR(_n) (0x01680 + ((_n) << 2))
84 #define E1000_EICS 0x01520 /* Ext. Interrupt Cause Set - W0 */
85 #define E1000_EIMS 0x01524 /* Ext. Interrupt Mask Set/Read - RW */
86 #define E1000_EIMC 0x01528 /* Ext. Interrupt Mask Clear - WO */
87 #define E1000_EIAC 0x0152C /* Ext. Interrupt Auto Clear - RW */
88 #define E1000_EIAM 0x01530 /* Ext. Interrupt Ack Auto Clear Mask - RW */
89 #define E1000_IVAR0 0x01700 /* Interrupt Vector Allocation (array) - RW */
90 #define E1000_IVAR_MISC 0x01740 /* IVAR for "other" causes - RW */
91 #define E1000_IVAR_VALID 0x80
93 /* Receive Descriptor - Advanced */
94 union e1000_adv_rx_desc {
96 u64 pkt_addr; /* Packet buffer address */
97 u64 hdr_addr; /* Header buffer address */
104 u16 pkt_info; /* RSS type, Packet type */
105 u16 hdr_info; /* Split Header,
106 * header buffer length */
110 u32 rss; /* RSS Hash */
112 u16 ip_id; /* IP id */
113 u16 csum; /* Packet Checksum */
118 u32 status_error; /* ext status/error */
119 u16 length; /* Packet length */
120 u16 vlan; /* VLAN tag */
122 } wb; /* writeback */
125 #define E1000_RXDADV_HDRBUFLEN_MASK 0x7FE0
126 #define E1000_RXDADV_HDRBUFLEN_SHIFT 5
128 /* Transmit Descriptor - Advanced */
129 union e1000_adv_tx_desc {
131 u64 buffer_addr; /* Address of descriptor's data buf */
136 u64 rsvd; /* Reserved */
142 /* Adv Transmit Descriptor Config Masks */
143 #define E1000_ADVTXD_DTYP_CTXT 0x00200000 /* Advanced Context Descriptor */
144 #define E1000_ADVTXD_DTYP_DATA 0x00300000 /* Advanced Data Descriptor */
145 #define E1000_ADVTXD_DCMD_EOP 0x01000000 /* End of Packet */
146 #define E1000_ADVTXD_DCMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
147 #define E1000_ADVTXD_DCMD_RS 0x08000000 /* Report Status */
148 #define E1000_ADVTXD_DCMD_DEXT 0x20000000 /* Descriptor extension (1=Adv) */
149 #define E1000_ADVTXD_DCMD_VLE 0x40000000 /* VLAN pkt enable */
150 #define E1000_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */
151 #define E1000_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */
153 /* Context descriptors */
154 struct e1000_adv_tx_context_desc {
161 #define E1000_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */
162 #define E1000_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */
163 #define E1000_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */
164 #define E1000_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */
165 #define E1000_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */
167 enum e1000_mac_type {
170 e1000_num_macs /* List is 1-based, so subtract 1 for true count. */
173 struct e1000_vf_stats {
205 #include "igbvf_mbx.h"
207 struct e1000_mac_operations {
208 /* Function pointers for the MAC. */
209 s32 (*init_params)(struct e1000_hw *);
210 s32 (*check_for_link)(struct e1000_hw *);
211 void (*clear_vfta)(struct e1000_hw *);
212 s32 (*get_bus_info)(struct e1000_hw *);
213 s32 (*get_link_up_info)(struct e1000_hw *, u16 *, u16 *);
214 void (*update_mc_addr_list)(struct e1000_hw *, u8 *, u32);
215 s32 (*reset_hw)(struct e1000_hw *);
216 s32 (*init_hw)(struct e1000_hw *);
217 s32 (*setup_link)(struct e1000_hw *);
218 void (*write_vfta)(struct e1000_hw *, u32, u32);
219 void (*mta_set)(struct e1000_hw *, u32);
220 void (*rar_set)(struct e1000_hw *, u8*, u32);
221 s32 (*read_mac_addr)(struct e1000_hw *);
224 struct e1000_mac_info {
225 struct e1000_mac_operations ops;
229 enum e1000_mac_type type;
234 bool get_link_status;
237 enum e1000_bus_type {
238 e1000_bus_type_unknown = 0,
241 e1000_bus_type_pci_express,
242 e1000_bus_type_reserved
245 enum e1000_bus_speed {
246 e1000_bus_speed_unknown = 0,
252 e1000_bus_speed_2500,
253 e1000_bus_speed_5000,
254 e1000_bus_speed_reserved
257 enum e1000_bus_width {
258 e1000_bus_width_unknown = 0,
259 e1000_bus_width_pcie_x1,
260 e1000_bus_width_pcie_x2,
261 e1000_bus_width_pcie_x4 = 4,
262 e1000_bus_width_pcie_x8 = 8,
265 e1000_bus_width_reserved
268 struct e1000_bus_info {
269 enum e1000_bus_type type;
270 enum e1000_bus_speed speed;
271 enum e1000_bus_width width;
277 struct e1000_mbx_operations {
278 s32 (*init_params)(struct e1000_hw *hw);
279 s32 (*read)(struct e1000_hw *, u32 *, u16, u16);
280 s32 (*write)(struct e1000_hw *, u32 *, u16, u16);
281 s32 (*read_posted)(struct e1000_hw *, u32 *, u16, u16);
282 s32 (*write_posted)(struct e1000_hw *, u32 *, u16, u16);
283 s32 (*check_for_msg)(struct e1000_hw *, u16);
284 s32 (*check_for_ack)(struct e1000_hw *, u16);
285 s32 (*check_for_rst)(struct e1000_hw *, u16);
288 struct e1000_mbx_stats {
297 struct e1000_mbx_info {
298 struct e1000_mbx_operations ops;
299 struct e1000_mbx_stats stats;
305 struct e1000_dev_spec_vf {
314 u8 __iomem *flash_address;
315 unsigned long io_base;
317 struct e1000_mac_info mac;
318 struct e1000_bus_info bus;
319 struct e1000_mbx_info mbx;
322 struct e1000_dev_spec_vf vf;
326 u16 subsystem_vendor_id;
327 u16 subsystem_device_id;
333 enum e1000_promisc_type {
334 e1000_promisc_disabled = 0, /* all promisc modes disabled */
335 e1000_promisc_unicast = 1, /* unicast promiscuous enabled */
336 e1000_promisc_multicast = 2, /* multicast promiscuous enabled */
337 e1000_promisc_enabled = 3, /* both uni and multicast promisc */
338 e1000_num_promisc_types
341 /* These functions must be implemented by drivers */
342 s32 igbvf_read_pcie_cap_reg(struct e1000_hw *hw, u32 reg, u16 *value);
343 void igbvf_vfta_set_vf(struct e1000_hw *, u16, bool);
344 void igbvf_rlpml_set_vf(struct e1000_hw *, u16);
345 s32 igbvf_promisc_set_vf(struct e1000_hw *, enum e1000_promisc_type);
346 #endif /* _IGBVF_VF_H_ */