1 /*******************************************************************************
3 Intel(R) 82576 Virtual Function Linux driver
4 Copyright(c) 1999 - 2008 Intel Corporation.
6 This program is free software; you can redistribute it and/or modify it
7 under the terms and conditions of the GNU General Public License,
8 version 2, as published by the Free Software Foundation.
10 This program is distributed in the hope it will be useful, but WITHOUT
11 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
15 You should have received a copy of the GNU General Public License along with
16 this program; if not, write to the Free Software Foundation, Inc.,
17 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
19 The full GNU General Public License is included in this distribution in
20 the file called "COPYING".
23 Linux NICS <linux.nics@intel.com>
24 e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
25 Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
27 *******************************************************************************/
29 FILE_LICENCE ( GPL2_ONLY );
31 /* glue for the OS-dependent part of igbvf
32 * includes register access macros
35 #ifndef _IGBVF_OSDEP_H_
36 #define _IGBVF_OSDEP_H_
38 #define u8 unsigned char
39 #define bool boolean_t
40 #define dma_addr_t unsigned long
41 #define __le16 uint16_t
42 #define __le32 uint32_t
43 #define __le64 uint64_t
47 #define ____cacheline_aligned_in_smp
49 #define msleep(x) mdelay(x)
53 typedef int spinlock_t;
59 #define usec_delay(x) udelay(x)
60 #define msec_delay(x) mdelay(x)
61 #define msec_delay_irq(x) mdelay(x)
63 #define PCI_COMMAND_REGISTER PCI_COMMAND
64 #define CMD_MEM_WRT_INVALIDATE PCI_COMMAND_INVALIDATE
65 #define ETH_ADDR_LEN ETH_ALEN
68 #define DEBUGOUT(S) if (0) { printf(S); }
69 #define DEBUGOUT1(S, A...) if (0) { printf(S, A); }
71 #define DEBUGFUNC(F) DEBUGOUT(F "\n")
72 #define DEBUGOUT2 DEBUGOUT1
73 #define DEBUGOUT3 DEBUGOUT2
74 #define DEBUGOUT7 DEBUGOUT3
76 #define E1000_WRITE_REG(a, reg, value) do { \
77 writel((value), ((a)->hw_addr + reg)); } while (0)
79 #define E1000_READ_REG(a, reg) (readl((a)->hw_addr + reg))
81 #define E1000_WRITE_REG_ARRAY(a, reg, offset, value) do { \
82 writel((value), ((a)->hw_addr + reg + ((offset) << 2))); } while (0)
84 #define E1000_READ_REG_ARRAY(a, reg, offset) ( \
85 readl((a)->hw_addr + reg + ((offset) << 2)))
87 #define E1000_READ_REG_ARRAY_DWORD E1000_READ_REG_ARRAY
88 #define E1000_WRITE_REG_ARRAY_DWORD E1000_WRITE_REG_ARRAY
90 #define E1000_WRITE_REG_ARRAY_WORD(a, reg, offset, value) ( \
91 writew((value), ((a)->hw_addr + reg + ((offset) << 1))))
93 #define E1000_READ_REG_ARRAY_WORD(a, reg, offset) ( \
94 readw((a)->hw_addr + reg + ((offset) << 1)))
96 #define E1000_WRITE_REG_ARRAY_BYTE(a, reg, offset, value) ( \
97 writeb((value), ((a)->hw_addr + reg + (offset))))
99 #define E1000_READ_REG_ARRAY_BYTE(a, reg, offset) ( \
100 readb((a)->hw_addr + reg + (offset)))
102 #define E1000_WRITE_REG_IO(a, reg, offset) do { \
103 outl(reg, ((a)->io_base)); \
104 outl(offset, ((a)->io_base + 4)); } while(0)
106 #define E1000_WRITE_FLUSH(a) E1000_READ_REG(a, E1000_STATUS)
108 #define E1000_WRITE_FLASH_REG(a, reg, value) ( \
109 writel((value), ((a)->flash_address + reg)))
111 #define E1000_WRITE_FLASH_REG16(a, reg, value) ( \
112 writew((value), ((a)->flash_address + reg)))
114 #define E1000_READ_FLASH_REG(a, reg) (readl((a)->flash_address + reg))
116 #define E1000_READ_FLASH_REG16(a, reg) (readw((a)->flash_address + reg))
118 #endif /* _IGBVF_OSDEP_H_ */